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gerrit-public.fairphone.software / toolchain / llvm-project / ca38c762e46c22566f09e41712c2ea3ea2e1240a / . / llvm / test / CodeGen / X86 / inline-asm-avx512vl-v-constraint.ll
blob: 4b01814b2e200c7b3662f595993701c30cd4dafe [file] [log] [blame]
Matthias Braun6b898be2017-08-02 00:28:10 +0000[diff] [blame]1; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx512vl | FileCheck %s
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]2
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]3define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]4entry:
5; CHECK: vmovhlps %xmm17, %xmm16, %xmm16
6 %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
7 ret <4 x float> %0
8}
9
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]10define <4 x float> @testxmm_2(<4 x float> %_xmm0, i64 %_l) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]11entry:
12; CHECK: vmovapd %xmm16, %xmm16
13 %0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l)
14 ret <4 x float> %0
15}
16
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]17define <4 x float> @testxmm_3(<4 x float> %_xmm0, i64 %_l) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]18entry:
19; CHECK: vminpd %xmm16, %xmm16, %xmm16
20 %0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, i64 %_l)
21 ret <4 x float> %0
22}
23
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]24define i64 @testxmm_4(<4 x float> %_xmm0, i64 %_l) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]25entry:
26; CHECK: vmulsd %xmm17, %xmm16, %xmm16
27 %0 = tail call i64 asm "vmulsd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
28 ret i64 %0
29}
30
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]31define <4 x float> @testxmm_5(<4 x float> %_xmm0, i64 %_l) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]32entry:
33; CHECK: vpabsq %xmm16, %xmm16
34 %0 = tail call <4 x float> asm "vpabsq $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l)
35 ret <4 x float> %0
36}
37
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]38define <4 x float> @testxmm_6(<4 x float> %_xmm0, i64 %_l) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]39entry:
40; CHECK: vpandd %xmm16, %xmm17, %xmm16
41 %0 = tail call <4 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l)
42 ret <4 x float> %0
43}
44
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]45define <4 x float> @testxmm_7(<4 x float> %_xmm0, i64 %_l) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]46entry:
47; CHECK: vpandnd %xmm16, %xmm17, %xmm16
48 %0 = tail call <4 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l)
49 ret <4 x float> %0
50}
51
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]52define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]53entry:
54; CHECK: vmovsldup %ymm16, %ymm16
55 %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
56 ret <8 x float> %0
57}
58
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]59define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]60entry:
61; CHECK: vmovapd %ymm16, %ymm16
62 %0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
63 ret <8 x float> %0
64}
65
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]66define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]67entry:
68; CHECK: vminpd %ymm16, %ymm16, %ymm16
69 %0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm1)
70 ret <8 x float> %0
71}
72
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]73define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]74entry:
75; CHECK: vpabsq %ymm16, %ymm16
76 %0 = tail call <8 x float> asm "vpabsq $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
77 ret <8 x float> %0
78}
79
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]80define <8 x float> @testymm_5(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]81entry:
82; CHECK: vpandd %ymm16, %ymm17, %ymm16
83 %0 = tail call <8 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
84 ret <8 x float> %0
85}
86
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]87define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]88entry:
89; CHECK: vpandnd %ymm16, %ymm17, %ymm16
90 %0 = tail call <8 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
91 ret <8 x float> %0
92}
93
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]94define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]95entry:
96; CHECK: vpminud %ymm16, %ymm17, %ymm16
97 %0 = tail call <8 x float> asm "vpminud $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
98 ret <8 x float> %0
99}
100
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]101define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]102entry:
103; CHECK: vpmaxsd %ymm16, %ymm17, %ymm16
104 %0 = tail call <8 x float> asm "vpmaxsd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0)
105 ret <8 x float> %0
106}
107
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]108define <8 x float> @testymm_9(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]109entry:
110; CHECK: vmovups %ymm16, %ymm16
111 %0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
112 ret <8 x float> %0
113}
114
Francis Visoiu Mistrih9d7bb0c2017-11-28 17:15:09 +0000[diff] [blame]115define <8 x float> @testymm_10(<8 x float> %_ymm0, <8 x float> %_ymm1) {
Michael Zuckerman3eeac2d2016-10-10 05:48:56 +0000[diff] [blame]116entry:
117; CHECK: vmovupd %ymm16, %ymm16
118 %0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1)
119 ret <8 x float> %0
120}
121