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gerrit-public.fairphone.software / toolchain / llvm-project / cb1ed400a42e065c522e2b59044e4af85055113b / . / llvm / test / tools / llvm-mca / X86 / variable-blend-read-after-ld-1.s
blob: 2dcd2e50955fd523a9d6ce57796ebd9a7cb18e88 [file] [log] [blame]
Simon Pilgrim96855ec2018-04-22 14:43:12 +0000[diff] [blame]1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SANDY
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]3
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]4# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=IVY
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]5
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]6# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]7
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]8# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDWELL
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]9
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]10# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]11
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]12# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]13
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]14# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]15
16vaddps %xmm0, %xmm0, %xmm1
17vblendvps %xmm1, (%rdi), %xmm2, %xmm3
18
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]19# BDWELL: Iterations: 1
20# BDWELL-NEXT: Instructions: 2
21# BDWELL-NEXT: Total Cycles: 10
22# BDWELL-NEXT: Dispatch Width: 4
23# BDWELL-NEXT: IPC: 0.20
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]24
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]25# BTVER2: Iterations: 1
26# BTVER2-NEXT: Instructions: 2
27# BTVER2-NEXT: Total Cycles: 11
28# BTVER2-NEXT: Dispatch Width: 2
29# BTVER2-NEXT: IPC: 0.18
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]30
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]31# HASWELL: Iterations: 1
32# HASWELL-NEXT: Instructions: 2
33# HASWELL-NEXT: Total Cycles: 11
34# HASWELL-NEXT: Dispatch Width: 4
35# HASWELL-NEXT: IPC: 0.18
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]36
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]37# IVY: Iterations: 1
38# IVY-NEXT: Instructions: 2
39# IVY-NEXT: Total Cycles: 11
40# IVY-NEXT: Dispatch Width: 4
41# IVY-NEXT: IPC: 0.18
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]42
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]43# SANDY: Iterations: 1
44# SANDY-NEXT: Instructions: 2
45# SANDY-NEXT: Total Cycles: 11
46# SANDY-NEXT: Dispatch Width: 4
47# SANDY-NEXT: IPC: 0.18
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]48
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]49# ZNVER1: Iterations: 1
50# ZNVER1-NEXT: Instructions: 2
51# ZNVER1-NEXT: Total Cycles: 11
52# ZNVER1-NEXT: Dispatch Width: 4
53# ZNVER1-NEXT: IPC: 0.18
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]54
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]55# SKYLAKE: Iterations: 1
56# SKYLAKE-NEXT: Instructions: 2
57# SKYLAKE-NEXT: Total Cycles: 11
58# SKYLAKE-NEXT: Dispatch Width: 6
59# SKYLAKE-NEXT: IPC: 0.18
Andrea Di Biagio01043622018-03-30 13:38:37 +0000[diff] [blame]60
Andrea Di Biagiocb1ed402018-05-21 17:11:56 +0000[diff] [blame^]61# BTVER2: Timeline view:
62# BTVER2-NEXT: 0
63# BTVER2-NEXT: Index 0123456789
64
65# HASWELL: Timeline view:
66# HASWELL-NEXT: 0
67# HASWELL-NEXT: Index 0123456789
68
69# IVY: Timeline view:
70# IVY-NEXT: 0
71# IVY-NEXT: Index 0123456789
72
73# SANDY: Timeline view:
74# SANDY-NEXT: 0
75# SANDY-NEXT: Index 0123456789
76
77# SKYLAKE: Timeline view:
78# SKYLAKE-NEXT: 0
79# SKYLAKE-NEXT: Index 0123456789
80
81# ZNVER1: Timeline view:
82# ZNVER1-NEXT: 0
83# ZNVER1-NEXT: Index 0123456789
84
85# BDWELL: Timeline view:
86# BDWELL-NEXT: Index 0123456789
87
88# BTVER2: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1
89# BTVER2-NEXT: [0,1] .DeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3
90
91# HASWELL: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1
92# HASWELL-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3
93
94# IVY: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1
95# IVY-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3
96
97# SANDY: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1
98# SANDY-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3
99
100# ZNVER1: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1
101# ZNVER1-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3
102
103# BDWELL: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1
104# BDWELL-NEXT: [0,1] DeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3
105
106# SKYLAKE: [0,0] DeeeeER . vaddps %xmm0, %xmm0, %xmm1
107# SKYLAKE-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3
108
109# ALL: Average Wait times (based on the timeline view):
110# ALL-NEXT: [0]: Executions
111# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
112# ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
113# ALL-NEXT: [3]: Average time elapsed from WB until retire stage
114
115# BDWELL: [0] [1] [2] [3]
116# BDWELL-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1
117# BDWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
118
119# HASWELL: [0] [1] [2] [3]
120# HASWELL-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1
121# HASWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
122
123# IVY: [0] [1] [2] [3]
124# IVY-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1
125# IVY-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
126
127# SANDY: [0] [1] [2] [3]
128# SANDY-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1
129# SANDY-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
130
131# SKYLAKE: [0] [1] [2] [3]
132# SKYLAKE-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1
133# SKYLAKE-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
134
135# ZNVER1: [0] [1] [2] [3]
136# ZNVER1-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1
137# ZNVER1-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
138
139# BTVER2: [0] [1] [2] [3]
140# BTVER2-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1
141# BTVER2-NEXT: 1. 1 1.0 1.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
142