| Alex Bradbury | cd26560 | 2019-01-22 12:11:53 +0000 | [diff] [blame^] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ |
| 3 | ; RUN: | FileCheck -check-prefix=RV64I %s |
| 4 | |
| 5 | ; This test case is significantly simplified from the submitted .ll but |
| 6 | ; demonstrates the same issue. At the time of this problem report, an infinite |
| 7 | ; loop would be created in DAGCombine, converting ANY_EXTEND to SIGN_EXTEND |
| 8 | ; and back again. |
| 9 | |
| 10 | ; TODO: This test case is also an example of where it would be cheaper to |
| 11 | ; select SRLW, but the current lowering strategy fails to do so. |
| 12 | |
| 13 | define signext i8 @foo(i32 %a, i32 %b) nounwind { |
| 14 | ; RV64I-LABEL: foo: |
| 15 | ; RV64I: # %bb.0: |
| 16 | ; RV64I-NEXT: slli a1, a1, 32 |
| 17 | ; RV64I-NEXT: srli a1, a1, 32 |
| 18 | ; RV64I-NEXT: slli a0, a0, 32 |
| 19 | ; RV64I-NEXT: srli a0, a0, 32 |
| 20 | ; RV64I-NEXT: srl a0, a0, a1 |
| 21 | ; RV64I-NEXT: slli a0, a0, 56 |
| 22 | ; RV64I-NEXT: srai a0, a0, 56 |
| 23 | ; RV64I-NEXT: ret |
| 24 | %1 = lshr i32 %a, %b |
| 25 | %2 = trunc i32 %1 to i8 |
| 26 | ret i8 %2 |
| 27 | } |