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Ahmed Bougacha6756a2c2016-07-27 14:31:55 +00001//===- AArch64InstructionSelector.cpp ----------------------------*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the targeting of the InstructionSelector class for
11/// AArch64.
12/// \todo This should be generated by TableGen.
13//===----------------------------------------------------------------------===//
14
15#include "AArch64InstructionSelector.h"
16#include "AArch64InstrInfo.h"
17#include "AArch64RegisterBankInfo.h"
18#include "AArch64RegisterInfo.h"
19#include "AArch64Subtarget.h"
Tim Northoverbdf16242016-10-10 21:50:00 +000020#include "AArch64TargetMachine.h"
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +000021#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineInstr.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/IR/Type.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/raw_ostream.h"
29
30#define DEBUG_TYPE "aarch64-isel"
31
32using namespace llvm;
33
34#ifndef LLVM_BUILD_GLOBAL_ISEL
35#error "You shouldn't build this"
36#endif
37
38AArch64InstructionSelector::AArch64InstructionSelector(
Tim Northoverbdf16242016-10-10 21:50:00 +000039 const AArch64TargetMachine &TM, const AArch64Subtarget &STI,
40 const AArch64RegisterBankInfo &RBI)
41 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +000042 TRI(*STI.getRegisterInfo()), RBI(RBI) {}
43
Tim Northoverfb8d9892016-10-12 22:49:15 +000044// FIXME: This should be target-independent, inferred from the types declared
45// for each class in the bank.
46static const TargetRegisterClass *
47getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
48 const RegisterBankInfo &RBI) {
49 if (RB.getID() == AArch64::GPRRegBankID) {
50 if (Ty.getSizeInBits() <= 32)
51 return &AArch64::GPR32RegClass;
52 if (Ty.getSizeInBits() == 64)
53 return &AArch64::GPR64RegClass;
54 return nullptr;
55 }
56
57 if (RB.getID() == AArch64::FPRRegBankID) {
58 if (Ty.getSizeInBits() == 32)
59 return &AArch64::FPR32RegClass;
60 if (Ty.getSizeInBits() == 64)
61 return &AArch64::FPR64RegClass;
62 if (Ty.getSizeInBits() == 128)
63 return &AArch64::FPR128RegClass;
64 return nullptr;
65 }
66
67 return nullptr;
68}
69
Ahmed Bougacha59e160a2016-08-16 14:37:40 +000070/// Check whether \p I is a currently unsupported binary operation:
71/// - it has an unsized type
72/// - an operand is not a vreg
73/// - all operands are not in the same bank
74/// These are checks that should someday live in the verifier, but right now,
75/// these are mostly limitations of the aarch64 selector.
76static bool unsupportedBinOp(const MachineInstr &I,
77 const AArch64RegisterBankInfo &RBI,
78 const MachineRegisterInfo &MRI,
79 const AArch64RegisterInfo &TRI) {
Tim Northover0f140c72016-09-09 11:46:34 +000080 LLT Ty = MRI.getType(I.getOperand(0).getReg());
Tim Northover32a078a2016-09-15 10:09:59 +000081 if (!Ty.isValid()) {
82 DEBUG(dbgs() << "Generic binop register should be typed\n");
Ahmed Bougacha59e160a2016-08-16 14:37:40 +000083 return true;
84 }
85
86 const RegisterBank *PrevOpBank = nullptr;
87 for (auto &MO : I.operands()) {
88 // FIXME: Support non-register operands.
89 if (!MO.isReg()) {
90 DEBUG(dbgs() << "Generic inst non-reg operands are unsupported\n");
91 return true;
92 }
93
94 // FIXME: Can generic operations have physical registers operands? If
95 // so, this will need to be taught about that, and we'll need to get the
96 // bank out of the minimal class for the register.
97 // Either way, this needs to be documented (and possibly verified).
98 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
99 DEBUG(dbgs() << "Generic inst has physical register operand\n");
100 return true;
101 }
102
103 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
104 if (!OpBank) {
105 DEBUG(dbgs() << "Generic register has no bank or class\n");
106 return true;
107 }
108
109 if (PrevOpBank && OpBank != PrevOpBank) {
110 DEBUG(dbgs() << "Generic inst operands have different banks\n");
111 return true;
112 }
113 PrevOpBank = OpBank;
114 }
115 return false;
116}
117
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000118/// Select the AArch64 opcode for the basic binary operation \p GenericOpc
119/// (such as G_OR or G_ADD), appropriate for the register bank \p RegBankID
120/// and of size \p OpSize.
121/// \returns \p GenericOpc if the combination is unsupported.
122static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
123 unsigned OpSize) {
124 switch (RegBankID) {
125 case AArch64::GPRRegBankID:
Tim Northover55782222016-10-18 20:03:48 +0000126 if (OpSize <= 32) {
127 assert((OpSize == 32 || (GenericOpc != TargetOpcode::G_SDIV &&
128 GenericOpc != TargetOpcode::G_UDIV &&
129 GenericOpc != TargetOpcode::G_LSHR &&
130 GenericOpc != TargetOpcode::G_ASHR)) &&
131 "operation should have been legalized before now");
132
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000133 switch (GenericOpc) {
134 case TargetOpcode::G_OR:
135 return AArch64::ORRWrr;
Ahmed Bougacha6db3cfe2016-07-29 16:56:25 +0000136 case TargetOpcode::G_XOR:
137 return AArch64::EORWrr;
Ahmed Bougacha61a79282016-07-28 16:58:31 +0000138 case TargetOpcode::G_AND:
139 return AArch64::ANDWrr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000140 case TargetOpcode::G_ADD:
141 return AArch64::ADDWrr;
Ahmed Bougachad7748d62016-07-28 16:58:35 +0000142 case TargetOpcode::G_SUB:
143 return AArch64::SUBWrr;
Ahmed Bougacha2ac5bf92016-08-16 14:02:47 +0000144 case TargetOpcode::G_SHL:
145 return AArch64::LSLVWr;
146 case TargetOpcode::G_LSHR:
147 return AArch64::LSRVWr;
148 case TargetOpcode::G_ASHR:
149 return AArch64::ASRVWr;
Ahmed Bougacha1d0560b2016-08-18 15:17:13 +0000150 case TargetOpcode::G_SDIV:
151 return AArch64::SDIVWr;
152 case TargetOpcode::G_UDIV:
153 return AArch64::UDIVWr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000154 default:
155 return GenericOpc;
156 }
Tim Northover55782222016-10-18 20:03:48 +0000157 } else if (OpSize == 64) {
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000158 switch (GenericOpc) {
159 case TargetOpcode::G_OR:
160 return AArch64::ORRXrr;
Ahmed Bougacha6db3cfe2016-07-29 16:56:25 +0000161 case TargetOpcode::G_XOR:
162 return AArch64::EORXrr;
Ahmed Bougacha61a79282016-07-28 16:58:31 +0000163 case TargetOpcode::G_AND:
164 return AArch64::ANDXrr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000165 case TargetOpcode::G_ADD:
Tim Northover2fda4b02016-10-10 21:49:49 +0000166 case TargetOpcode::G_GEP:
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000167 return AArch64::ADDXrr;
Ahmed Bougachad7748d62016-07-28 16:58:35 +0000168 case TargetOpcode::G_SUB:
169 return AArch64::SUBXrr;
Ahmed Bougacha2ac5bf92016-08-16 14:02:47 +0000170 case TargetOpcode::G_SHL:
171 return AArch64::LSLVXr;
172 case TargetOpcode::G_LSHR:
173 return AArch64::LSRVXr;
174 case TargetOpcode::G_ASHR:
175 return AArch64::ASRVXr;
Ahmed Bougacha1d0560b2016-08-18 15:17:13 +0000176 case TargetOpcode::G_SDIV:
177 return AArch64::SDIVXr;
178 case TargetOpcode::G_UDIV:
179 return AArch64::UDIVXr;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000180 default:
181 return GenericOpc;
182 }
183 }
Ahmed Bougacha33e19fe2016-08-18 16:05:11 +0000184 case AArch64::FPRRegBankID:
185 switch (OpSize) {
186 case 32:
187 switch (GenericOpc) {
188 case TargetOpcode::G_FADD:
189 return AArch64::FADDSrr;
190 case TargetOpcode::G_FSUB:
191 return AArch64::FSUBSrr;
192 case TargetOpcode::G_FMUL:
193 return AArch64::FMULSrr;
194 case TargetOpcode::G_FDIV:
195 return AArch64::FDIVSrr;
196 default:
197 return GenericOpc;
198 }
199 case 64:
200 switch (GenericOpc) {
201 case TargetOpcode::G_FADD:
202 return AArch64::FADDDrr;
203 case TargetOpcode::G_FSUB:
204 return AArch64::FSUBDrr;
205 case TargetOpcode::G_FMUL:
206 return AArch64::FMULDrr;
207 case TargetOpcode::G_FDIV:
208 return AArch64::FDIVDrr;
Quentin Colombet0e531272016-10-11 00:21:11 +0000209 case TargetOpcode::G_OR:
210 return AArch64::ORRv8i8;
Ahmed Bougacha33e19fe2016-08-18 16:05:11 +0000211 default:
212 return GenericOpc;
213 }
214 }
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000215 };
216 return GenericOpc;
217}
218
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000219/// Select the AArch64 opcode for the G_LOAD or G_STORE operation \p GenericOpc,
220/// appropriate for the (value) register bank \p RegBankID and of memory access
221/// size \p OpSize. This returns the variant with the base+unsigned-immediate
222/// addressing mode (e.g., LDRXui).
223/// \returns \p GenericOpc if the combination is unsupported.
224static unsigned selectLoadStoreUIOp(unsigned GenericOpc, unsigned RegBankID,
225 unsigned OpSize) {
226 const bool isStore = GenericOpc == TargetOpcode::G_STORE;
227 switch (RegBankID) {
228 case AArch64::GPRRegBankID:
229 switch (OpSize) {
Tim Northover020d1042016-10-17 18:36:53 +0000230 case 8:
231 return isStore ? AArch64::STRBBui : AArch64::LDRBBui;
232 case 16:
233 return isStore ? AArch64::STRHHui : AArch64::LDRHHui;
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000234 case 32:
235 return isStore ? AArch64::STRWui : AArch64::LDRWui;
236 case 64:
237 return isStore ? AArch64::STRXui : AArch64::LDRXui;
238 }
Quentin Colombetd2623f8e2016-10-11 00:21:14 +0000239 case AArch64::FPRRegBankID:
240 switch (OpSize) {
Tim Northover020d1042016-10-17 18:36:53 +0000241 case 8:
242 return isStore ? AArch64::STRBui : AArch64::LDRBui;
243 case 16:
244 return isStore ? AArch64::STRHui : AArch64::LDRHui;
Quentin Colombetd2623f8e2016-10-11 00:21:14 +0000245 case 32:
246 return isStore ? AArch64::STRSui : AArch64::LDRSui;
247 case 64:
248 return isStore ? AArch64::STRDui : AArch64::LDRDui;
249 }
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000250 };
251 return GenericOpc;
252}
253
Quentin Colombetcb629a82016-10-12 03:57:49 +0000254static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
255 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
256 const RegisterBankInfo &RBI) {
257
258 unsigned DstReg = I.getOperand(0).getReg();
259 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
260 assert(I.isCopy() && "Generic operators do not allow physical registers");
261 return true;
262 }
263
264 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
265 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
266 unsigned SrcReg = I.getOperand(1).getReg();
267 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
268 (void)SrcSize;
269 assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
270 "No phys reg on generic operators");
271 assert(
272 (DstSize == SrcSize ||
273 // Copies are a mean to setup initial types, the number of
274 // bits may not exactly match.
275 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
276 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI)) ||
277 // Copies are a mean to copy bits around, as long as we are
278 // on the same register class, that's fine. Otherwise, that
279 // means we need some SUBREG_TO_REG or AND & co.
280 (((DstSize + 31) / 32 == (SrcSize + 31) / 32) && DstSize > SrcSize)) &&
281 "Copy with different width?!");
282 assert((DstSize <= 64 || RegBank.getID() == AArch64::FPRRegBankID) &&
283 "GPRs cannot get more than 64-bit width values");
284 const TargetRegisterClass *RC = nullptr;
285
286 if (RegBank.getID() == AArch64::FPRRegBankID) {
287 if (DstSize <= 32)
288 RC = &AArch64::FPR32RegClass;
289 else if (DstSize <= 64)
290 RC = &AArch64::FPR64RegClass;
291 else if (DstSize <= 128)
292 RC = &AArch64::FPR128RegClass;
293 else {
294 DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n');
295 return false;
296 }
297 } else {
298 assert(RegBank.getID() == AArch64::GPRRegBankID &&
299 "Bitcast for the flags?");
300 RC =
301 DstSize <= 32 ? &AArch64::GPR32allRegClass : &AArch64::GPR64allRegClass;
302 }
303
304 // No need to constrain SrcReg. It will get constrained when
305 // we hit another of its use or its defs.
306 // Copies do not have constraints.
307 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
308 DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
309 << " operand\n");
310 return false;
311 }
312 I.setDesc(TII.get(AArch64::COPY));
313 return true;
314}
315
Tim Northover69271c62016-10-12 22:49:11 +0000316static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) {
317 if (!DstTy.isScalar() || !SrcTy.isScalar())
318 return GenericOpc;
319
320 const unsigned DstSize = DstTy.getSizeInBits();
321 const unsigned SrcSize = SrcTy.getSizeInBits();
322
323 switch (DstSize) {
324 case 32:
325 switch (SrcSize) {
326 case 32:
327 switch (GenericOpc) {
328 case TargetOpcode::G_SITOFP:
329 return AArch64::SCVTFUWSri;
330 case TargetOpcode::G_UITOFP:
331 return AArch64::UCVTFUWSri;
332 case TargetOpcode::G_FPTOSI:
333 return AArch64::FCVTZSUWSr;
334 case TargetOpcode::G_FPTOUI:
335 return AArch64::FCVTZUUWSr;
336 default:
337 return GenericOpc;
338 }
339 case 64:
340 switch (GenericOpc) {
341 case TargetOpcode::G_SITOFP:
342 return AArch64::SCVTFUXSri;
343 case TargetOpcode::G_UITOFP:
344 return AArch64::UCVTFUXSri;
345 case TargetOpcode::G_FPTOSI:
346 return AArch64::FCVTZSUWDr;
347 case TargetOpcode::G_FPTOUI:
348 return AArch64::FCVTZUUWDr;
349 default:
350 return GenericOpc;
351 }
352 default:
353 return GenericOpc;
354 }
355 case 64:
356 switch (SrcSize) {
357 case 32:
358 switch (GenericOpc) {
359 case TargetOpcode::G_SITOFP:
360 return AArch64::SCVTFUWDri;
361 case TargetOpcode::G_UITOFP:
362 return AArch64::UCVTFUWDri;
363 case TargetOpcode::G_FPTOSI:
364 return AArch64::FCVTZSUXSr;
365 case TargetOpcode::G_FPTOUI:
366 return AArch64::FCVTZUUXSr;
367 default:
368 return GenericOpc;
369 }
370 case 64:
371 switch (GenericOpc) {
372 case TargetOpcode::G_SITOFP:
373 return AArch64::SCVTFUXDri;
374 case TargetOpcode::G_UITOFP:
375 return AArch64::UCVTFUXDri;
376 case TargetOpcode::G_FPTOSI:
377 return AArch64::FCVTZSUXDr;
378 case TargetOpcode::G_FPTOUI:
379 return AArch64::FCVTZUUXDr;
380 default:
381 return GenericOpc;
382 }
383 default:
384 return GenericOpc;
385 }
386 default:
387 return GenericOpc;
388 };
389 return GenericOpc;
390}
391
Tim Northover6c02ad52016-10-12 22:49:04 +0000392static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
393 switch (P) {
394 default:
395 llvm_unreachable("Unknown condition code!");
396 case CmpInst::ICMP_NE:
397 return AArch64CC::NE;
398 case CmpInst::ICMP_EQ:
399 return AArch64CC::EQ;
400 case CmpInst::ICMP_SGT:
401 return AArch64CC::GT;
402 case CmpInst::ICMP_SGE:
403 return AArch64CC::GE;
404 case CmpInst::ICMP_SLT:
405 return AArch64CC::LT;
406 case CmpInst::ICMP_SLE:
407 return AArch64CC::LE;
408 case CmpInst::ICMP_UGT:
409 return AArch64CC::HI;
410 case CmpInst::ICMP_UGE:
411 return AArch64CC::HS;
412 case CmpInst::ICMP_ULT:
413 return AArch64CC::LO;
414 case CmpInst::ICMP_ULE:
415 return AArch64CC::LS;
416 }
417}
418
Tim Northover7dd378d2016-10-12 22:49:07 +0000419static void changeFCMPPredToAArch64CC(CmpInst::Predicate P,
420 AArch64CC::CondCode &CondCode,
421 AArch64CC::CondCode &CondCode2) {
422 CondCode2 = AArch64CC::AL;
423 switch (P) {
424 default:
425 llvm_unreachable("Unknown FP condition!");
426 case CmpInst::FCMP_OEQ:
427 CondCode = AArch64CC::EQ;
428 break;
429 case CmpInst::FCMP_OGT:
430 CondCode = AArch64CC::GT;
431 break;
432 case CmpInst::FCMP_OGE:
433 CondCode = AArch64CC::GE;
434 break;
435 case CmpInst::FCMP_OLT:
436 CondCode = AArch64CC::MI;
437 break;
438 case CmpInst::FCMP_OLE:
439 CondCode = AArch64CC::LS;
440 break;
441 case CmpInst::FCMP_ONE:
442 CondCode = AArch64CC::MI;
443 CondCode2 = AArch64CC::GT;
444 break;
445 case CmpInst::FCMP_ORD:
446 CondCode = AArch64CC::VC;
447 break;
448 case CmpInst::FCMP_UNO:
449 CondCode = AArch64CC::VS;
450 break;
451 case CmpInst::FCMP_UEQ:
452 CondCode = AArch64CC::EQ;
453 CondCode2 = AArch64CC::VS;
454 break;
455 case CmpInst::FCMP_UGT:
456 CondCode = AArch64CC::HI;
457 break;
458 case CmpInst::FCMP_UGE:
459 CondCode = AArch64CC::PL;
460 break;
461 case CmpInst::FCMP_ULT:
462 CondCode = AArch64CC::LT;
463 break;
464 case CmpInst::FCMP_ULE:
465 CondCode = AArch64CC::LE;
466 break;
467 case CmpInst::FCMP_UNE:
468 CondCode = AArch64CC::NE;
469 break;
470 }
471}
472
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000473bool AArch64InstructionSelector::select(MachineInstr &I) const {
474 assert(I.getParent() && "Instruction should be in a basic block!");
475 assert(I.getParent()->getParent() && "Instruction should be in a function!");
476
477 MachineBasicBlock &MBB = *I.getParent();
478 MachineFunction &MF = *MBB.getParent();
479 MachineRegisterInfo &MRI = MF.getRegInfo();
480
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000481 if (!isPreISelGenericOpcode(I.getOpcode()))
Quentin Colombetcb629a82016-10-12 03:57:49 +0000482 return !I.isCopy() || selectCopy(I, TII, MRI, TRI, RBI);
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000483
484 if (I.getNumOperands() != I.getNumExplicitOperands()) {
485 DEBUG(dbgs() << "Generic instruction has unexpected implicit operands\n");
486 return false;
487 }
488
Tim Northover69271c62016-10-12 22:49:11 +0000489 unsigned Opcode = I.getOpcode();
Tim Northover32a078a2016-09-15 10:09:59 +0000490 LLT Ty =
491 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000492
Tim Northover69271c62016-10-12 22:49:11 +0000493 switch (Opcode) {
Ahmed Bougacha85505092016-07-28 17:15:15 +0000494 case TargetOpcode::G_BR: {
495 I.setDesc(TII.get(AArch64::B));
Ahmed Bougacha85505092016-07-28 17:15:15 +0000496 return true;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000497 }
498
Tim Northover5e3dbf32016-10-12 22:49:01 +0000499 case TargetOpcode::G_BRCOND: {
500 if (Ty.getSizeInBits() > 32) {
501 // We shouldn't need this on AArch64, but it would be implemented as an
502 // EXTRACT_SUBREG followed by a TBNZW because TBNZX has no encoding if the
503 // bit being tested is < 32.
504 DEBUG(dbgs() << "G_BRCOND has type: " << Ty
505 << ", expected at most 32-bits");
506 return false;
507 }
508
509 const unsigned CondReg = I.getOperand(0).getReg();
510 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
511
512 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
513 .addUse(CondReg)
514 .addImm(/*bit offset=*/0)
515 .addMBB(DestMBB);
516
517 I.eraseFromParent();
518 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
519 }
520
Tim Northover4494d692016-10-18 19:47:57 +0000521 case TargetOpcode::G_FCONSTANT:
Tim Northover4edc60d2016-10-10 21:49:42 +0000522 case TargetOpcode::G_CONSTANT: {
Tim Northover4494d692016-10-18 19:47:57 +0000523 const bool isFP = Opcode == TargetOpcode::G_FCONSTANT;
524
525 const LLT s32 = LLT::scalar(32);
526 const LLT s64 = LLT::scalar(64);
527 const LLT p0 = LLT::pointer(0, 64);
528
529 const unsigned DefReg = I.getOperand(0).getReg();
530 const LLT DefTy = MRI.getType(DefReg);
531 const unsigned DefSize = DefTy.getSizeInBits();
532 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
533
534 // FIXME: Redundant check, but even less readable when factored out.
535 if (isFP) {
536 if (Ty != s32 && Ty != s64) {
537 DEBUG(dbgs() << "Unable to materialize FP " << Ty
538 << " constant, expected: " << s32 << " or " << s64
539 << '\n');
540 return false;
541 }
542
543 if (RB.getID() != AArch64::FPRRegBankID) {
544 DEBUG(dbgs() << "Unable to materialize FP " << Ty
545 << " constant on bank: " << RB << ", expected: FPR\n");
546 return false;
547 }
548 } else {
549 if (Ty != s32 && Ty != s64 && Ty != p0) {
550 DEBUG(dbgs() << "Unable to materialize integer " << Ty
551 << " constant, expected: " << s32 << ", " << s64 << ", or "
552 << p0 << '\n');
553 return false;
554 }
555
556 if (RB.getID() != AArch64::GPRRegBankID) {
557 DEBUG(dbgs() << "Unable to materialize integer " << Ty
558 << " constant on bank: " << RB << ", expected: GPR\n");
559 return false;
560 }
561 }
562
563 const unsigned MovOpc =
564 DefSize == 32 ? AArch64::MOVi32imm : AArch64::MOVi64imm;
565
566 I.setDesc(TII.get(MovOpc));
567
568 if (isFP) {
569 const TargetRegisterClass &GPRRC =
570 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass;
571 const TargetRegisterClass &FPRRC =
572 DefSize == 32 ? AArch64::FPR32RegClass : AArch64::FPR64RegClass;
573
574 const unsigned DefGPRReg = MRI.createVirtualRegister(&GPRRC);
575 MachineOperand &RegOp = I.getOperand(0);
576 RegOp.setReg(DefGPRReg);
577
578 BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
579 TII.get(AArch64::COPY))
580 .addDef(DefReg)
581 .addUse(DefGPRReg);
582
583 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {
584 DEBUG(dbgs() << "Failed to constrain G_FCONSTANT def operand\n");
585 return false;
586 }
587
588 MachineOperand &ImmOp = I.getOperand(1);
589 // FIXME: Is going through int64_t always correct?
590 ImmOp.ChangeToImmediate(
591 ImmOp.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
592 }
593
594 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
595 return true;
Tim Northover4edc60d2016-10-10 21:49:42 +0000596 }
597
Ahmed Bougacha0306b5e2016-08-16 14:02:42 +0000598 case TargetOpcode::G_FRAME_INDEX: {
599 // allocas and G_FRAME_INDEX are only supported in addrspace(0).
Tim Northover5ae83502016-09-15 09:20:34 +0000600 if (Ty != LLT::pointer(0, 64)) {
Tim Northover0f140c72016-09-09 11:46:34 +0000601 DEBUG(dbgs() << "G_FRAME_INDEX pointer has type: " << Ty
Tim Northover5ae83502016-09-15 09:20:34 +0000602 << ", expected: " << LLT::pointer(0, 64) << '\n');
Ahmed Bougacha0306b5e2016-08-16 14:02:42 +0000603 return false;
604 }
605
606 I.setDesc(TII.get(AArch64::ADDXri));
Ahmed Bougacha0306b5e2016-08-16 14:02:42 +0000607
608 // MOs for a #0 shifted immediate.
609 I.addOperand(MachineOperand::CreateImm(0));
610 I.addOperand(MachineOperand::CreateImm(0));
611
612 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
613 }
Tim Northoverbdf16242016-10-10 21:50:00 +0000614
615 case TargetOpcode::G_GLOBAL_VALUE: {
616 auto GV = I.getOperand(1).getGlobal();
617 if (GV->isThreadLocal()) {
618 // FIXME: we don't support TLS yet.
619 return false;
620 }
621 unsigned char OpFlags = STI.ClassifyGlobalReference(GV, TM);
622 if (OpFlags & AArch64II::MO_GOT)
623 I.setDesc(TII.get(AArch64::LOADgot));
624 else {
625 I.setDesc(TII.get(AArch64::MOVaddr));
626 I.getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_PAGE);
627 MachineInstrBuilder MIB(MF, I);
628 MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(),
629 OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
630 }
631 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
632 }
633
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000634 case TargetOpcode::G_LOAD:
635 case TargetOpcode::G_STORE: {
Tim Northover0f140c72016-09-09 11:46:34 +0000636 LLT MemTy = Ty;
637 LLT PtrTy = MRI.getType(I.getOperand(1).getReg());
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000638
Tim Northover5ae83502016-09-15 09:20:34 +0000639 if (PtrTy != LLT::pointer(0, 64)) {
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000640 DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy
Tim Northover5ae83502016-09-15 09:20:34 +0000641 << ", expected: " << LLT::pointer(0, 64) << '\n');
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000642 return false;
643 }
644
645#ifndef NDEBUG
646 // Sanity-check the pointer register.
647 const unsigned PtrReg = I.getOperand(1).getReg();
648 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
649 assert(PtrRB.getID() == AArch64::GPRRegBankID &&
650 "Load/Store pointer operand isn't a GPR");
Tim Northover0f140c72016-09-09 11:46:34 +0000651 assert(MRI.getType(PtrReg).isPointer() &&
652 "Load/Store pointer operand isn't a pointer");
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000653#endif
654
655 const unsigned ValReg = I.getOperand(0).getReg();
656 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
657
658 const unsigned NewOpc =
659 selectLoadStoreUIOp(I.getOpcode(), RB.getID(), MemTy.getSizeInBits());
660 if (NewOpc == I.getOpcode())
661 return false;
662
663 I.setDesc(TII.get(NewOpc));
Ahmed Bougacha7adfac52016-07-29 16:56:16 +0000664
665 I.addOperand(MachineOperand::CreateImm(0));
666 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
667 }
668
Ahmed Bougachae4c03ab2016-08-16 14:37:46 +0000669 case TargetOpcode::G_MUL: {
670 // Reject the various things we don't support yet.
671 if (unsupportedBinOp(I, RBI, MRI, TRI))
672 return false;
673
674 const unsigned DefReg = I.getOperand(0).getReg();
675 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
676
677 if (RB.getID() != AArch64::GPRRegBankID) {
678 DEBUG(dbgs() << "G_MUL on bank: " << RB << ", expected: GPR\n");
679 return false;
680 }
681
682 unsigned ZeroReg;
683 unsigned NewOpc;
Tim Northover55782222016-10-18 20:03:48 +0000684 if (Ty.isScalar() && Ty.getSizeInBits() <= 32) {
Ahmed Bougachae4c03ab2016-08-16 14:37:46 +0000685 NewOpc = AArch64::MADDWrrr;
686 ZeroReg = AArch64::WZR;
687 } else if (Ty == LLT::scalar(64)) {
688 NewOpc = AArch64::MADDXrrr;
689 ZeroReg = AArch64::XZR;
690 } else {
691 DEBUG(dbgs() << "G_MUL has type: " << Ty << ", expected: "
692 << LLT::scalar(32) << " or " << LLT::scalar(64) << '\n');
693 return false;
694 }
695
696 I.setDesc(TII.get(NewOpc));
Ahmed Bougachae4c03ab2016-08-16 14:37:46 +0000697
698 I.addOperand(MachineOperand::CreateReg(ZeroReg, /*isDef=*/false));
699
700 // Now that we selected an opcode, we need to constrain the register
701 // operands to use appropriate classes.
702 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
703 }
704
Ahmed Bougacha33e19fe2016-08-18 16:05:11 +0000705 case TargetOpcode::G_FADD:
706 case TargetOpcode::G_FSUB:
707 case TargetOpcode::G_FMUL:
708 case TargetOpcode::G_FDIV:
709
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000710 case TargetOpcode::G_OR:
Ahmed Bougacha6db3cfe2016-07-29 16:56:25 +0000711 case TargetOpcode::G_XOR:
Ahmed Bougacha61a79282016-07-28 16:58:31 +0000712 case TargetOpcode::G_AND:
Ahmed Bougacha2ac5bf92016-08-16 14:02:47 +0000713 case TargetOpcode::G_SHL:
714 case TargetOpcode::G_LSHR:
715 case TargetOpcode::G_ASHR:
Ahmed Bougacha1d0560b2016-08-18 15:17:13 +0000716 case TargetOpcode::G_SDIV:
717 case TargetOpcode::G_UDIV:
Ahmed Bougachad7748d62016-07-28 16:58:35 +0000718 case TargetOpcode::G_ADD:
Tim Northover2fda4b02016-10-10 21:49:49 +0000719 case TargetOpcode::G_SUB:
720 case TargetOpcode::G_GEP: {
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000721 // Reject the various things we don't support yet.
Ahmed Bougacha59e160a2016-08-16 14:37:40 +0000722 if (unsupportedBinOp(I, RBI, MRI, TRI))
723 return false;
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000724
Ahmed Bougacha59e160a2016-08-16 14:37:40 +0000725 const unsigned OpSize = Ty.getSizeInBits();
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000726
727 const unsigned DefReg = I.getOperand(0).getReg();
728 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
729
730 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize);
731 if (NewOpc == I.getOpcode())
732 return false;
733
734 I.setDesc(TII.get(NewOpc));
735 // FIXME: Should the type be always reset in setDesc?
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +0000736
737 // Now that we selected an opcode, we need to constrain the register
738 // operands to use appropriate classes.
739 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
740 }
Tim Northover3d38b3a2016-10-11 20:50:21 +0000741
Tim Northoverfb8d9892016-10-12 22:49:15 +0000742 case TargetOpcode::G_TRUNC: {
743 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
744 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
745
746 const unsigned DstReg = I.getOperand(0).getReg();
747 const unsigned SrcReg = I.getOperand(1).getReg();
748
749 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
750 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
751
752 if (DstRB.getID() != SrcRB.getID()) {
753 DEBUG(dbgs() << "G_TRUNC input/output on different banks\n");
754 return false;
755 }
756
757 if (DstRB.getID() == AArch64::GPRRegBankID) {
758 const TargetRegisterClass *DstRC =
759 getRegClassForTypeOnBank(DstTy, DstRB, RBI);
760 if (!DstRC)
761 return false;
762
763 const TargetRegisterClass *SrcRC =
764 getRegClassForTypeOnBank(SrcTy, SrcRB, RBI);
765 if (!SrcRC)
766 return false;
767
768 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
769 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
770 DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
771 return false;
772 }
773
774 if (DstRC == SrcRC) {
775 // Nothing to be done
776 } else if (DstRC == &AArch64::GPR32RegClass &&
777 SrcRC == &AArch64::GPR64RegClass) {
778 I.getOperand(1).setSubReg(AArch64::sub_32);
779 } else {
780 return false;
781 }
782
783 I.setDesc(TII.get(TargetOpcode::COPY));
784 return true;
785 } else if (DstRB.getID() == AArch64::FPRRegBankID) {
786 if (DstTy == LLT::vector(4, 16) && SrcTy == LLT::vector(4, 32)) {
787 I.setDesc(TII.get(AArch64::XTNv4i16));
788 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
789 return true;
790 }
791 }
792
793 return false;
794 }
795
Tim Northover3d38b3a2016-10-11 20:50:21 +0000796 case TargetOpcode::G_ANYEXT: {
797 const unsigned DstReg = I.getOperand(0).getReg();
798 const unsigned SrcReg = I.getOperand(1).getReg();
799
Quentin Colombetcb629a82016-10-12 03:57:49 +0000800 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
801 if (RBDst.getID() != AArch64::GPRRegBankID) {
802 DEBUG(dbgs() << "G_ANYEXT on bank: " << RBDst << ", expected: GPR\n");
803 return false;
804 }
Tim Northover3d38b3a2016-10-11 20:50:21 +0000805
Quentin Colombetcb629a82016-10-12 03:57:49 +0000806 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);
807 if (RBSrc.getID() != AArch64::GPRRegBankID) {
808 DEBUG(dbgs() << "G_ANYEXT on bank: " << RBSrc << ", expected: GPR\n");
Tim Northover3d38b3a2016-10-11 20:50:21 +0000809 return false;
810 }
811
812 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
813
814 if (DstSize == 0) {
815 DEBUG(dbgs() << "G_ANYEXT operand has no size, not a gvreg?\n");
816 return false;
817 }
818
Quentin Colombetcb629a82016-10-12 03:57:49 +0000819 if (DstSize != 64 && DstSize > 32) {
Tim Northover3d38b3a2016-10-11 20:50:21 +0000820 DEBUG(dbgs() << "G_ANYEXT to size: " << DstSize
821 << ", expected: 32 or 64\n");
822 return false;
823 }
Quentin Colombetcb629a82016-10-12 03:57:49 +0000824 // At this point G_ANYEXT is just like a plain COPY, but we need
825 // to explicitly form the 64-bit value if any.
826 if (DstSize > 32) {
827 unsigned ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
828 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
829 .addDef(ExtSrc)
830 .addImm(0)
831 .addUse(SrcReg)
832 .addImm(AArch64::sub_32);
833 I.getOperand(1).setReg(ExtSrc);
Tim Northover3d38b3a2016-10-11 20:50:21 +0000834 }
Quentin Colombetcb629a82016-10-12 03:57:49 +0000835 return selectCopy(I, TII, MRI, TRI, RBI);
Tim Northover3d38b3a2016-10-11 20:50:21 +0000836 }
837
838 case TargetOpcode::G_ZEXT:
839 case TargetOpcode::G_SEXT: {
840 unsigned Opcode = I.getOpcode();
841 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
842 SrcTy = MRI.getType(I.getOperand(1).getReg());
843 const bool isSigned = Opcode == TargetOpcode::G_SEXT;
844 const unsigned DefReg = I.getOperand(0).getReg();
845 const unsigned SrcReg = I.getOperand(1).getReg();
846 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
847
848 if (RB.getID() != AArch64::GPRRegBankID) {
849 DEBUG(dbgs() << TII.getName(I.getOpcode()) << " on bank: " << RB
850 << ", expected: GPR\n");
851 return false;
852 }
853
854 MachineInstr *ExtI;
855 if (DstTy == LLT::scalar(64)) {
856 // FIXME: Can we avoid manually doing this?
857 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) {
858 DEBUG(dbgs() << "Failed to constrain " << TII.getName(Opcode)
859 << " operand\n");
860 return false;
861 }
862
863 const unsigned SrcXReg =
864 MRI.createVirtualRegister(&AArch64::GPR64RegClass);
865 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
866 .addDef(SrcXReg)
867 .addImm(0)
868 .addUse(SrcReg)
869 .addImm(AArch64::sub_32);
870
871 const unsigned NewOpc = isSigned ? AArch64::SBFMXri : AArch64::UBFMXri;
872 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
873 .addDef(DefReg)
874 .addUse(SrcXReg)
875 .addImm(0)
876 .addImm(SrcTy.getSizeInBits() - 1);
877 } else if (DstTy == LLT::scalar(32)) {
878 const unsigned NewOpc = isSigned ? AArch64::SBFMWri : AArch64::UBFMWri;
879 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
880 .addDef(DefReg)
881 .addUse(SrcReg)
882 .addImm(0)
883 .addImm(SrcTy.getSizeInBits() - 1);
884 } else {
885 return false;
886 }
887
888 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
889
890 I.eraseFromParent();
891 return true;
892 }
Tim Northoverc1d8c2b2016-10-11 22:29:23 +0000893
Tim Northover69271c62016-10-12 22:49:11 +0000894 case TargetOpcode::G_SITOFP:
895 case TargetOpcode::G_UITOFP:
896 case TargetOpcode::G_FPTOSI:
897 case TargetOpcode::G_FPTOUI: {
898 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
899 SrcTy = MRI.getType(I.getOperand(1).getReg());
900 const unsigned NewOpc = selectFPConvOpc(Opcode, DstTy, SrcTy);
901 if (NewOpc == Opcode)
902 return false;
903
904 I.setDesc(TII.get(NewOpc));
905 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
906
907 return true;
908 }
909
910
Tim Northoverc1d8c2b2016-10-11 22:29:23 +0000911 case TargetOpcode::G_INTTOPTR:
912 case TargetOpcode::G_PTRTOINT:
Quentin Colombet9de30fa2016-10-12 03:57:52 +0000913 case TargetOpcode::G_BITCAST:
914 return selectCopy(I, TII, MRI, TRI, RBI);
Tim Northover6c02ad52016-10-12 22:49:04 +0000915
916 case TargetOpcode::G_ICMP: {
917 if (Ty != LLT::scalar(1)) {
918 DEBUG(dbgs() << "G_ICMP result has type: " << Ty
919 << ", expected: " << LLT::scalar(1) << '\n');
920 return false;
921 }
922
923 unsigned CmpOpc = 0;
924 unsigned ZReg = 0;
925
926 LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
927 if (CmpTy == LLT::scalar(32)) {
928 CmpOpc = AArch64::SUBSWrr;
929 ZReg = AArch64::WZR;
930 } else if (CmpTy == LLT::scalar(64) || CmpTy.isPointer()) {
931 CmpOpc = AArch64::SUBSXrr;
932 ZReg = AArch64::XZR;
933 } else {
934 return false;
935 }
936
937 const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
938 (CmpInst::Predicate)I.getOperand(1).getPredicate());
939
940 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
941 .addDef(ZReg)
942 .addUse(I.getOperand(2).getReg())
943 .addUse(I.getOperand(3).getReg());
944
945 MachineInstr &CSetMI =
946 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
947 .addDef(I.getOperand(0).getReg())
948 .addUse(AArch64::WZR)
949 .addUse(AArch64::WZR)
950 .addImm(CC);
951
952 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
953 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
954
955 I.eraseFromParent();
956 return true;
957 }
958
Tim Northover7dd378d2016-10-12 22:49:07 +0000959 case TargetOpcode::G_FCMP: {
960 if (Ty != LLT::scalar(1)) {
961 DEBUG(dbgs() << "G_FCMP result has type: " << Ty
962 << ", expected: " << LLT::scalar(1) << '\n');
963 return false;
964 }
965
966 unsigned CmpOpc = 0;
967 LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
968 if (CmpTy == LLT::scalar(32)) {
969 CmpOpc = AArch64::FCMPSrr;
970 } else if (CmpTy == LLT::scalar(64)) {
971 CmpOpc = AArch64::FCMPDrr;
972 } else {
973 return false;
974 }
975
976 // FIXME: regbank
977
978 AArch64CC::CondCode CC1, CC2;
979 changeFCMPPredToAArch64CC(
980 (CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
981
982 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
983 .addUse(I.getOperand(2).getReg())
984 .addUse(I.getOperand(3).getReg());
985
986 const unsigned DefReg = I.getOperand(0).getReg();
987 unsigned Def1Reg = DefReg;
988 if (CC2 != AArch64CC::AL)
989 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
990
991 MachineInstr &CSetMI =
992 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
993 .addDef(Def1Reg)
994 .addUse(AArch64::WZR)
995 .addUse(AArch64::WZR)
996 .addImm(CC1);
997
998 if (CC2 != AArch64CC::AL) {
999 unsigned Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1000 MachineInstr &CSet2MI =
1001 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
1002 .addDef(Def2Reg)
1003 .addUse(AArch64::WZR)
1004 .addUse(AArch64::WZR)
1005 .addImm(CC2);
1006 MachineInstr &OrMI =
1007 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
1008 .addDef(DefReg)
1009 .addUse(Def1Reg)
1010 .addUse(Def2Reg);
1011 constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
1012 constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
1013 }
1014
1015 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
1016 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
1017
1018 I.eraseFromParent();
1019 return true;
1020 }
Ahmed Bougacha6756a2c2016-07-27 14:31:55 +00001021 }
1022
1023 return false;
1024}