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Nicolai Haehnle5d0d3032018-04-01 17:09:07 +00001//===-- AMDGPUSearchableTables.td - ------------------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11
12//===----------------------------------------------------------------------===//
13// Resource intrinsics table.
14//===----------------------------------------------------------------------===//
15
16class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> : SearchableTable {
17 let SearchableFields = ["Intr"];
18 let EnumNameField = ?;
19
20 Intrinsic Intr = !cast<Intrinsic>(intr);
21 bits<8> RsrcArg = intr.RsrcArg;
22 bit IsImage = intr.IsImage;
23}
24
25foreach intr = !listconcat(AMDGPUBufferIntrinsics,
Nicolai Haehnle2f5a7382018-04-04 10:58:54 +000026 AMDGPUImageIntrinsics,
27 AMDGPUImageDimIntrinsics,
28 AMDGPUImageDimGatherIntrinsics,
29 AMDGPUImageDimGetResInfoIntrinsics,
30 AMDGPUImageDimAtomicIntrinsics) in {
Nicolai Haehnle5d0d3032018-04-01 17:09:07 +000031 def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
32}
Nicolai Haehnle4254d452018-04-01 17:09:14 +000033
34class SourceOfDivergence<Intrinsic intr> : SearchableTable {
35 let SearchableFields = ["Intr"];
36 let EnumNameField = ?;
37
38 Intrinsic Intr = intr;
39}
40
41def : SourceOfDivergence<int_amdgcn_workitem_id_x>;
42def : SourceOfDivergence<int_amdgcn_workitem_id_y>;
43def : SourceOfDivergence<int_amdgcn_workitem_id_z>;
44def : SourceOfDivergence<int_amdgcn_interp_mov>;
45def : SourceOfDivergence<int_amdgcn_interp_p1>;
46def : SourceOfDivergence<int_amdgcn_interp_p2>;
47def : SourceOfDivergence<int_amdgcn_mbcnt_hi>;
48def : SourceOfDivergence<int_amdgcn_mbcnt_lo>;
49def : SourceOfDivergence<int_r600_read_tidig_x>;
50def : SourceOfDivergence<int_r600_read_tidig_y>;
51def : SourceOfDivergence<int_r600_read_tidig_z>;
52def : SourceOfDivergence<int_amdgcn_atomic_inc>;
53def : SourceOfDivergence<int_amdgcn_atomic_dec>;
54def : SourceOfDivergence<int_amdgcn_ds_fadd>;
55def : SourceOfDivergence<int_amdgcn_ds_fmin>;
56def : SourceOfDivergence<int_amdgcn_ds_fmax>;
57def : SourceOfDivergence<int_amdgcn_image_atomic_swap>;
58def : SourceOfDivergence<int_amdgcn_image_atomic_add>;
59def : SourceOfDivergence<int_amdgcn_image_atomic_sub>;
60def : SourceOfDivergence<int_amdgcn_image_atomic_smin>;
61def : SourceOfDivergence<int_amdgcn_image_atomic_umin>;
62def : SourceOfDivergence<int_amdgcn_image_atomic_smax>;
63def : SourceOfDivergence<int_amdgcn_image_atomic_umax>;
64def : SourceOfDivergence<int_amdgcn_image_atomic_and>;
65def : SourceOfDivergence<int_amdgcn_image_atomic_or>;
66def : SourceOfDivergence<int_amdgcn_image_atomic_xor>;
67def : SourceOfDivergence<int_amdgcn_image_atomic_inc>;
68def : SourceOfDivergence<int_amdgcn_image_atomic_dec>;
69def : SourceOfDivergence<int_amdgcn_image_atomic_cmpswap>;
70def : SourceOfDivergence<int_amdgcn_buffer_atomic_swap>;
71def : SourceOfDivergence<int_amdgcn_buffer_atomic_add>;
72def : SourceOfDivergence<int_amdgcn_buffer_atomic_sub>;
73def : SourceOfDivergence<int_amdgcn_buffer_atomic_smin>;
74def : SourceOfDivergence<int_amdgcn_buffer_atomic_umin>;
75def : SourceOfDivergence<int_amdgcn_buffer_atomic_smax>;
76def : SourceOfDivergence<int_amdgcn_buffer_atomic_umax>;
77def : SourceOfDivergence<int_amdgcn_buffer_atomic_and>;
78def : SourceOfDivergence<int_amdgcn_buffer_atomic_or>;
79def : SourceOfDivergence<int_amdgcn_buffer_atomic_xor>;
80def : SourceOfDivergence<int_amdgcn_buffer_atomic_cmpswap>;
81def : SourceOfDivergence<int_amdgcn_ps_live>;
82def : SourceOfDivergence<int_amdgcn_ds_swizzle>;
Nicolai Haehnle2f5a7382018-04-04 10:58:54 +000083
84foreach intr = AMDGPUImageDimAtomicIntrinsics in
85def : SourceOfDivergence<intr>;
86
87class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> : SearchableTable {
88 let SearchableFields = ["Intr"];
89 let EnumNameField = ?;
90
91 Intrinsic Intr = intr;
92 code D16HelperIntr =
93 !cast<code>("AMDGPUIntrinsic::SI_image_d16helper_" # intr.P.OpMod # intr.P.Dim.Name);
94}
95
96foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
97 AMDGPUImageDimGatherIntrinsics) in {
98 def : D16ImageDimIntrinsic<intr>;
99}