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gerrit-public.fairphone.software / toolchain / llvm-project / cea7c6969d777615b0a29584b1be4c90ea968944 / . / llvm / test / CodeGen / AMDGPU / fmax_legacy.f16.ll
blob: 4563ec4e1014715a0db5f641bec9450f0508a486 [file] [log] [blame]
Matt Arsenault5b9ef392018-08-24 21:24:18 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-SAFE %s
3; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-NNAN %s
4
5; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI-SAFE %s
6; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI-NNAN %s
7
8; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI-SAFE %s
9; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI-NNAN %s
10
11define half @test_fmax_legacy_ugt_f16(half %a, half %b) #0 {
12; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_f16:
13; GFX9-SAFE: ; %bb.0:
14; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
16; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
17; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
18;
19; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_f16:
20; GFX9-NNAN: ; %bb.0:
21; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
22; GFX9-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
23; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
24;
25; VI-SAFE-LABEL: test_fmax_legacy_ugt_f16:
26; VI-SAFE: ; %bb.0:
27; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
28; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
29; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
30; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
31;
32; VI-NNAN-LABEL: test_fmax_legacy_ugt_f16:
33; VI-NNAN: ; %bb.0:
34; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
35; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
36; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
37;
38; SI-SAFE-LABEL: test_fmax_legacy_ugt_f16:
39; SI-SAFE: ; %bb.0:
40; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
41; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
42; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
43; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
44; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
45; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v1, v0
46; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
47;
48; SI-NNAN-LABEL: test_fmax_legacy_ugt_f16:
49; SI-NNAN: ; %bb.0:
50; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
52; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
53; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
54; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
55; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v1
56; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
57 %cmp = fcmp ugt half %a, %b
58 %val = select i1 %cmp, half %a, half %b
59 ret half %val
60}
61
62define <2 x half> @test_fmax_legacy_ugt_v2f16(<2 x half> %a, <2 x half> %b) #0 {
63; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
64; GFX9-SAFE: ; %bb.0:
65; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
66; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
67; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
68; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2
69; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
70; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
71; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
72; GFX9-SAFE-NEXT: v_and_b32_e32 v0, 0xffff, v0
73; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v2, 16, v0
74; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
75;
76; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
77; GFX9-NNAN: ; %bb.0:
78; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
79; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v1
80; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
81;
82; VI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
83; VI-SAFE: ; %bb.0:
84; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
85; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1
86; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0
87; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2
88; VI-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
89; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
90; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v2
91; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
92; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
93; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
94;
95; VI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
96; VI-NNAN: ; %bb.0:
97; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
98; VI-NNAN-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
99; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
100; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v2
101; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
102;
103; SI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
104; SI-SAFE: ; %bb.0:
105; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
106; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
107; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
108; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
109; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
110; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
111; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
112; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
113; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
114; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v2, v0
115; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v3, v1
116; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
117;
118; SI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
119; SI-NNAN: ; %bb.0:
120; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
121; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
122; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
123; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
124; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
125; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
126; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
127; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
128; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
129; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v2
130; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v3
131; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
132 %cmp = fcmp ugt <2 x half> %a, %b
133 %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
134 ret <2 x half> %val
135}
136
137define <3 x half> @test_fmax_legacy_ugt_v3f16(<3 x half> %a, <3 x half> %b) #0 {
138; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
139; GFX9-SAFE: ; %bb.0:
140; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
141; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
142; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
143; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
144; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
145; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
146; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
147; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
148; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
149; GFX9-SAFE-NEXT: v_and_b32_e32 v0, 0xffff, v0
150; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v4, 16, v0
151; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
152;
153; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
154; GFX9-NNAN: ; %bb.0:
155; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
Matt Arsenaultcea7c692018-08-27 18:11:31 +0000[diff] [blame^]156; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v3
157; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v2
Matt Arsenault5b9ef392018-08-24 21:24:18 +0000[diff] [blame]158; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
159;
160; VI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
161; VI-SAFE: ; %bb.0:
162; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
163; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
164; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
165; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
166; VI-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
167; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
168; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
169; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
170; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
171; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v4
172; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
173; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
174;
175; VI-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
176; VI-NNAN: ; %bb.0:
177; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
178; VI-NNAN-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
179; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
180; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
181; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v4
182; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
183;
184; SI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
185; SI-SAFE: ; %bb.0:
186; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
187; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
188; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
189; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
190; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
191; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
192; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
193; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
194; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
195; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
196; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
197; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
198; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
199; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v3, v0
200; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v4, v1
201; SI-SAFE-NEXT: v_max_legacy_f32_e32 v2, v5, v2
202; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
203;
204; SI-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
205; SI-NNAN: ; %bb.0:
206; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
207; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
208; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
209; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
210; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
211; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
212; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
213; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
214; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
215; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
216; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
217; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
218; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
219; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v3
220; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v4
221; SI-NNAN-NEXT: v_max_f32_e32 v2, v2, v5
222; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
223 %cmp = fcmp ugt <3 x half> %a, %b
224 %val = select <3 x i1> %cmp, <3 x half> %a, <3 x half> %b
225 ret <3 x half> %val
226}
227
228define <4 x half> @test_fmax_legacy_ugt_v4f16(<4 x half> %a, <4 x half> %b) #0 {
229; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
230; GFX9-SAFE: ; %bb.0:
231; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
232; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
233; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
234; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6
235; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
236; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
237; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
238; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
239; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
240; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
241; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
242; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
243; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
244; GFX9-SAFE-NEXT: v_mov_b32_e32 v2, 0xffff
245; GFX9-SAFE-NEXT: v_and_b32_e32 v0, v2, v0
246; GFX9-SAFE-NEXT: v_and_b32_e32 v1, v2, v1
247; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v4, 16, v0
248; GFX9-SAFE-NEXT: v_lshl_or_b32 v1, v6, 16, v1
249; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
250;
251; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
252; GFX9-NNAN: ; %bb.0:
253; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
254; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v2
255; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v3
256; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
257;
258; VI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
259; VI-SAFE: ; %bb.0:
260; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
261; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3
262; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1
263; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6
264; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2
265; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0
266; VI-SAFE-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
267; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4
268; VI-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
269; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3
270; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
271; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2
272; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
273; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v4
274; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
275; VI-SAFE-NEXT: v_lshlrev_b32_e32 v2, 16, v6
276; VI-SAFE-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
277; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
278;
279; VI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
280; VI-NNAN: ; %bb.0:
281; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
282; VI-NNAN-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
283; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
284; VI-NNAN-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
285; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
286; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v5
287; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v4
288; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
289;
290; SI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
291; SI-SAFE: ; %bb.0:
292; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
293; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
294; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
295; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
296; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
297; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
298; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
299; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
300; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
301; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
302; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
303; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
304; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
305; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
306; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
307; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
308; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
309; SI-SAFE-NEXT: v_max_legacy_f32_e32 v3, v7, v3
310; SI-SAFE-NEXT: v_max_legacy_f32_e32 v2, v6, v2
311; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v5, v1
312; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v4, v0
313; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
314; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
315; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
316; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
317; SI-SAFE-NEXT: v_lshlrev_b32_e32 v3, 16, v3
318; SI-SAFE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
319; SI-SAFE-NEXT: v_or_b32_e32 v3, v2, v3
320; SI-SAFE-NEXT: v_or_b32_e32 v1, v0, v1
321; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v1
322; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v3
323; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
324; SI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v3
325; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
326; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
327; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
328;
329; SI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
330; SI-NNAN: ; %bb.0:
331; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
332; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
333; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
334; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
335; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
336; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v6, v6
337; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
338; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v7, v7
339; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
340; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
341; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
342; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
343; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
344; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v6, v6
345; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
346; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v7, v7
347; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
348; SI-NNAN-NEXT: v_max_f32_e32 v3, v3, v7
349; SI-NNAN-NEXT: v_max_f32_e32 v2, v2, v6
350; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v5
351; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v4
352; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
353; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
354; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
355; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
356; SI-NNAN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
357; SI-NNAN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
358; SI-NNAN-NEXT: v_or_b32_e32 v3, v2, v3
359; SI-NNAN-NEXT: v_or_b32_e32 v1, v0, v1
360; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v1
361; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v3
362; SI-NNAN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
363; SI-NNAN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
364; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
365; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
366; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
367 %cmp = fcmp ugt <4 x half> %a, %b
368 %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
369 ret <4 x half> %val
370}
371
372define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 {
373; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
374; GFX9-SAFE: ; %bb.0:
375; GFX9-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
376; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v14, 16, v7
377; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v15, 16, v3
378; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14
379; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v12, 16, v6
380; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v13, 16, v2
381; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
382; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12
383; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v10, 16, v5
384; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v11, 16, v1
385; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
386; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10
387; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v4
388; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
389; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
390; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8
391; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
392; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7
393; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
394; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6
395; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
396; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5
397; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
398; GFX9-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4
399; GFX9-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
400; GFX9-SAFE-NEXT: v_mov_b32_e32 v4, 0xffff
401; GFX9-SAFE-NEXT: v_and_b32_e32 v0, v4, v0
402; GFX9-SAFE-NEXT: v_and_b32_e32 v1, v4, v1
403; GFX9-SAFE-NEXT: v_and_b32_e32 v2, v4, v2
404; GFX9-SAFE-NEXT: v_and_b32_e32 v3, v4, v3
405; GFX9-SAFE-NEXT: v_lshl_or_b32 v0, v8, 16, v0
406; GFX9-SAFE-NEXT: v_lshl_or_b32 v1, v10, 16, v1
407; GFX9-SAFE-NEXT: v_lshl_or_b32 v2, v12, 16, v2
408; GFX9-SAFE-NEXT: v_lshl_or_b32 v3, v14, 16, v3
409; GFX9-SAFE-NEXT: s_setpc_b64 s[30:31]
410;
411; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
412; GFX9-NNAN: ; %bb.0:
413; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
Matt Arsenaultcea7c692018-08-27 18:11:31 +0000[diff] [blame^]414; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v4
415; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v5
416; GFX9-NNAN-NEXT: v_pk_max_f16 v2, v2, v6
417; GFX9-NNAN-NEXT: v_pk_max_f16 v3, v3, v7
Matt Arsenault5b9ef392018-08-24 21:24:18 +0000[diff] [blame]418; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31]
419;
420; VI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
421; VI-SAFE: ; %bb.0:
422; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
423; VI-SAFE-NEXT: v_lshrrev_b32_e32 v14, 16, v7
424; VI-SAFE-NEXT: v_lshrrev_b32_e32 v15, 16, v3
425; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14
426; VI-SAFE-NEXT: v_lshrrev_b32_e32 v12, 16, v6
427; VI-SAFE-NEXT: v_lshrrev_b32_e32 v13, 16, v2
428; VI-SAFE-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc
429; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12
430; VI-SAFE-NEXT: v_lshrrev_b32_e32 v10, 16, v5
431; VI-SAFE-NEXT: v_lshrrev_b32_e32 v11, 16, v1
432; VI-SAFE-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc
433; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10
434; VI-SAFE-NEXT: v_lshrrev_b32_e32 v8, 16, v4
435; VI-SAFE-NEXT: v_lshrrev_b32_e32 v9, 16, v0
436; VI-SAFE-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
437; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8
438; VI-SAFE-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
439; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7
440; VI-SAFE-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
441; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6
442; VI-SAFE-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
443; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5
444; VI-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
445; VI-SAFE-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4
446; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
447; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v8
448; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
449; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v10
450; VI-SAFE-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
451; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v12
452; VI-SAFE-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
453; VI-SAFE-NEXT: v_lshlrev_b32_e32 v4, 16, v14
454; VI-SAFE-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
455; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
456;
457; VI-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
458; VI-NNAN: ; %bb.0:
459; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
460; VI-NNAN-NEXT: v_max_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
461; VI-NNAN-NEXT: v_max_f16_e32 v3, v3, v7
462; VI-NNAN-NEXT: v_max_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
463; VI-NNAN-NEXT: v_max_f16_e32 v2, v2, v6
464; VI-NNAN-NEXT: v_max_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
465; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v5
466; VI-NNAN-NEXT: v_max_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
467; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v4
468; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v11
469; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v10
470; VI-NNAN-NEXT: v_or_b32_e32 v2, v2, v9
471; VI-NNAN-NEXT: v_or_b32_e32 v3, v3, v8
472; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
473;
474; SI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
475; SI-SAFE: ; %bb.0:
476; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
477; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
478; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v8, v8
479; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
480; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v9, v9
481; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
482; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v10, v10
483; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
484; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v11, v11
485; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
486; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v12, v12
487; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
488; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v13, v13
489; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
490; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v14, v14
491; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
492; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v15, v15
493; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
494; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v8, v8
495; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
496; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v9, v9
497; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
498; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v10, v10
499; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
500; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v11, v11
501; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v4
502; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v12, v12
503; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
504; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v13, v13
505; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v6
506; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v14, v14
507; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
508; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v15, v15
509; SI-SAFE-NEXT: v_max_legacy_f32_e32 v7, v15, v7
510; SI-SAFE-NEXT: v_max_legacy_f32_e32 v6, v14, v6
511; SI-SAFE-NEXT: v_max_legacy_f32_e32 v5, v13, v5
512; SI-SAFE-NEXT: v_max_legacy_f32_e32 v4, v12, v4
513; SI-SAFE-NEXT: v_max_legacy_f32_e32 v3, v11, v3
514; SI-SAFE-NEXT: v_max_legacy_f32_e32 v2, v10, v2
515; SI-SAFE-NEXT: v_max_legacy_f32_e32 v1, v9, v1
516; SI-SAFE-NEXT: v_max_legacy_f32_e32 v0, v8, v0
517; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
518; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
519; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
520; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v4, v4
521; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
522; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
523; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
524; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
525; SI-SAFE-NEXT: v_lshlrev_b32_e32 v7, 16, v7
526; SI-SAFE-NEXT: v_lshlrev_b32_e32 v5, 16, v5
527; SI-SAFE-NEXT: v_lshlrev_b32_e32 v3, 16, v3
528; SI-SAFE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
529; SI-SAFE-NEXT: v_or_b32_e32 v7, v6, v7
530; SI-SAFE-NEXT: v_or_b32_e32 v5, v4, v5
531; SI-SAFE-NEXT: v_or_b32_e32 v3, v2, v3
532; SI-SAFE-NEXT: v_or_b32_e32 v1, v0, v1
533; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v1
534; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v3
535; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v4, v5
536; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v6, v7
537; SI-SAFE-NEXT: v_lshrrev_b32_e32 v1, 16, v1
538; SI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v3
539; SI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v5
540; SI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v7
541; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
542; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v3
543; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v5, v5
544; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v7, v7
545; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
546;
547; SI-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
548; SI-NNAN: ; %bb.0:
549; SI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
550; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v8, v8
551; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
552; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v9, v9
553; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
554; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v10, v10
555; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
556; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v11, v11
557; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
558; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v12, v12
559; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
560; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v13, v13
561; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
562; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v14, v14
563; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v6, v6
564; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v15, v15
565; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v7, v7
566; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v8, v8
567; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v0
568; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v9, v9
569; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
570; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v10, v10
571; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v2
572; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v11, v11
573; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
574; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v12, v12
575; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v4
576; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v13, v13
577; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
578; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v14, v14
579; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v6, v6
580; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v15, v15
581; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v7, v7
582; SI-NNAN-NEXT: v_max_f32_e32 v7, v7, v15
583; SI-NNAN-NEXT: v_max_f32_e32 v6, v6, v14
584; SI-NNAN-NEXT: v_max_f32_e32 v5, v5, v13
585; SI-NNAN-NEXT: v_max_f32_e32 v4, v4, v12
586; SI-NNAN-NEXT: v_max_f32_e32 v3, v3, v11
587; SI-NNAN-NEXT: v_max_f32_e32 v2, v2, v10
588; SI-NNAN-NEXT: v_max_f32_e32 v1, v1, v9
589; SI-NNAN-NEXT: v_max_f32_e32 v0, v0, v8
590; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v7, v7
591; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v6, v6
592; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v5, v5
593; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v4, v4
594; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v3, v3
595; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v2, v2
596; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v1, v1
597; SI-NNAN-NEXT: v_cvt_f16_f32_e32 v0, v0
598; SI-NNAN-NEXT: v_lshlrev_b32_e32 v7, 16, v7
599; SI-NNAN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
600; SI-NNAN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
601; SI-NNAN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
602; SI-NNAN-NEXT: v_or_b32_e32 v7, v6, v7
603; SI-NNAN-NEXT: v_or_b32_e32 v5, v4, v5
604; SI-NNAN-NEXT: v_or_b32_e32 v3, v2, v3
605; SI-NNAN-NEXT: v_or_b32_e32 v1, v0, v1
606; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v0, v1
607; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v2, v3
608; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v4, v5
609; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v6, v7
610; SI-NNAN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
611; SI-NNAN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
612; SI-NNAN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
613; SI-NNAN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
614; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v1, v1
615; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v3, v3
616; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v5, v5
617; SI-NNAN-NEXT: v_cvt_f32_f16_e32 v7, v7
618; SI-NNAN-NEXT: s_setpc_b64 s[30:31]
619 %cmp = fcmp ugt <8 x half> %a, %b
620 %val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
621 ret <8 x half> %val
622}
623
624attributes #0 = { nounwind }