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gerrit-public.fairphone.software / toolchain / llvm-project / ceb1dbb41f6d7eaa3b45793d3307fe092f635167 / . / llvm / lib / Target / PowerPC / PPCScheduleG4.td
blob: fc9120dfa2905547cff531409221590424f74269 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===//
2//
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]7//
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G4 (7400) processor.
11//
12//===----------------------------------------------------------------------===//
13
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]14def G4Itineraries : ProcessorItineraries<
Evan Cheng0097dd02010-09-28 23:50:49 +0000[diff] [blame]15 [IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [], [
Hal Finkel8c33dde2012-06-12 19:01:24 +0000[diff] [blame]16 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]17 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
18 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]19 InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
20 InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>,
21 InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>,
22 InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]23 InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
24 InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
25 InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]26 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
27 InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]28 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
29 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
30 InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
31 InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
32 InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]33 InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>,
34 InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>,
Hal Finkel59607e62012-04-01 04:44:16 +0000[diff] [blame]35 InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>,
Hal Finkel679c73c2012-08-28 02:49:14 +0000[diff] [blame]36 InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>,
Hal Finkel59607e62012-04-01 04:44:16 +0000[diff] [blame]37 InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>,
Hal Finkel679c73c2012-08-28 02:49:14 +0000[diff] [blame]38 InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]39 InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>,
40 InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>,
Hal Finkel679c73c2012-08-28 02:49:14 +0000[diff] [blame]41 InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>,
42 InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]43 InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
44 InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
45 InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
Hal Finkel679c73c2012-08-28 02:49:14 +0000[diff] [blame]46 InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]47 InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
Jim Laskey74ab9962005-10-19 19:51:16 +0000[diff] [blame]48 InstrItinData<LdStLVecX , [InstrStage<2, [SLU]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]49 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]50 InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>,
51 InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>,
52 InstrItinData<LdStSync , [InstrStage<8, [SLU]>]>,
53 InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
54 InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>,
55 InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>,
56 InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>,
57 InstrItinData<SprTLBSYNC , [InstrStage<8, [SRU]>]>,
58 InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>,
59 InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>,
60 InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>,
61 InstrItinData<SprMFTB , [InstrStage<1, [SRU]>]>,
62 InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>,
63 InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>,
64 InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
65 InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
66 InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
Hal Finkel679c73c2012-08-28 02:49:14 +0000[diff] [blame]67 InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]68 InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
69 InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
70 InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
71 InstrItinData<FPFused , [InstrStage<1, [FPU1]>]>,
72 InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>,
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]73 InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
74 InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
75 InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>,
76 InstrItinData<VecComplex , [InstrStage<3, [VIU2]>]>,
77 InstrItinData<VecPerm , [InstrStage<1, [VPU]>]>,
78 InstrItinData<VecFPRound , [InstrStage<4, [VFPU]>]>,
79 InstrItinData<VecVSL , [InstrStage<1, [VIU1]>]>,
80 InstrItinData<VecVSR , [InstrStage<1, [VIU1]>]>
81]>;