Sanjay Patel | cf26c27 | 2016-10-19 18:42:12 +0000 | [diff] [blame^] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| 2 | ; RUN: opt < %s -instsimplify -S | FileCheck %s |
| 3 | |
| 4 | define i32 @negate_nuw(i32 %x) { |
| 5 | ; CHECK-LABEL: @negate_nuw( |
| 6 | ; CHECK-NEXT: ret i32 0 |
| 7 | ; |
| 8 | %neg = sub nuw i32 0, %x |
| 9 | ret i32 %neg |
| 10 | } |
| 11 | |
| 12 | define <2 x i32> @negate_nuw_vec(<2 x i32> %x) { |
| 13 | ; CHECK-LABEL: @negate_nuw_vec( |
| 14 | ; CHECK-NEXT: ret <2 x i32> zeroinitializer |
| 15 | ; |
| 16 | %neg = sub nuw <2 x i32> zeroinitializer, %x |
| 17 | ret <2 x i32> %neg |
| 18 | } |
| 19 | |
| 20 | define i8 @negate_zero_or_minsigned_nsw(i8 %x) { |
| 21 | ; CHECK-LABEL: @negate_zero_or_minsigned_nsw( |
| 22 | ; CHECK-NEXT: [[SIGNBIT:%.*]] = and i8 %x, -128 |
| 23 | ; CHECK-NEXT: [[NEG:%.*]] = sub nsw i8 0, [[SIGNBIT]] |
| 24 | ; CHECK-NEXT: ret i8 [[NEG]] |
| 25 | ; |
| 26 | %signbit = and i8 %x, 128 |
| 27 | %neg = sub nsw i8 0, %signbit |
| 28 | ret i8 %neg |
| 29 | } |
| 30 | |
| 31 | define <2 x i8> @negate_zero_or_minsigned_nsw_vec(<2 x i8> %x) { |
| 32 | ; CHECK-LABEL: @negate_zero_or_minsigned_nsw_vec( |
| 33 | ; CHECK-NEXT: [[SIGNBIT:%.*]] = shl <2 x i8> %x, <i8 7, i8 7> |
| 34 | ; CHECK-NEXT: [[NEG:%.*]] = sub nsw <2 x i8> zeroinitializer, [[SIGNBIT]] |
| 35 | ; CHECK-NEXT: ret <2 x i8> [[NEG]] |
| 36 | ; |
| 37 | %signbit = shl <2 x i8> %x, <i8 7, i8 7> |
| 38 | %neg = sub nsw <2 x i8> zeroinitializer, %signbit |
| 39 | ret <2 x i8> %neg |
| 40 | } |
| 41 | |
| 42 | define i8 @negate_zero_or_minsigned(i8 %x) { |
| 43 | ; CHECK-LABEL: @negate_zero_or_minsigned( |
| 44 | ; CHECK-NEXT: [[SIGNBIT:%.*]] = shl i8 %x, 7 |
| 45 | ; CHECK-NEXT: [[NEG:%.*]] = sub i8 0, [[SIGNBIT]] |
| 46 | ; CHECK-NEXT: ret i8 [[NEG]] |
| 47 | ; |
| 48 | %signbit = shl i8 %x, 7 |
| 49 | %neg = sub i8 0, %signbit |
| 50 | ret i8 %neg |
| 51 | } |
| 52 | |
| 53 | define <2 x i8> @negate_zero_or_minsigned_vec(<2 x i8> %x) { |
| 54 | ; CHECK-LABEL: @negate_zero_or_minsigned_vec( |
| 55 | ; CHECK-NEXT: [[SIGNBIT:%.*]] = and <2 x i8> %x, <i8 -128, i8 -128> |
| 56 | ; CHECK-NEXT: [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[SIGNBIT]] |
| 57 | ; CHECK-NEXT: ret <2 x i8> [[NEG]] |
| 58 | ; |
| 59 | %signbit = and <2 x i8> %x, <i8 128, i8 128> |
| 60 | %neg = sub <2 x i8> zeroinitializer, %signbit |
| 61 | ret <2 x i8> %neg |
| 62 | } |
| 63 | |