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Kevin Enderbyccab3172009-09-15 00:27:25 +00001//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Evan Cheng11424442011-07-26 00:24:13 +000010#include "llvm/MC/MCTargetAsmParser.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000011#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
Jim Grosbach5c932b22011-08-22 18:50:36 +000014#include "llvm/ADT/BitVector.h"
Benjamin Kramerdebe69f2011-07-08 21:06:23 +000015#include "llvm/ADT/OwningPtr.h"
Evan Cheng11424442011-07-26 00:24:13 +000016#include "llvm/ADT/STLExtras.h"
Chris Lattner00646cf2010-01-22 01:44:57 +000017#include "llvm/ADT/SmallVector.h"
Daniel Dunbar188b47b2010-08-11 06:37:20 +000018#include "llvm/ADT/StringSwitch.h"
Chris Lattner00646cf2010-01-22 01:44:57 +000019#include "llvm/ADT/Twine.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000020#include "llvm/MC/MCAsmInfo.h"
Jack Carter718da0b2013-01-30 02:24:33 +000021#include "llvm/MC/MCAssembler.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000022#include "llvm/MC/MCContext.h"
Jack Carter718da0b2013-01-30 02:24:33 +000023#include "llvm/MC/MCELFStreamer.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000024#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCParser/MCAsmLexer.h"
28#include "llvm/MC/MCParser/MCAsmParser.h"
29#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSubtargetInfo.h"
Jack Carter718da0b2013-01-30 02:24:33 +000033#include "llvm/Support/ELF.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000034#include "llvm/Support/MathExtras.h"
35#include "llvm/Support/SourceMgr.h"
36#include "llvm/Support/TargetRegistry.h"
37#include "llvm/Support/raw_ostream.h"
Evan Cheng4d1ca962011-07-08 01:53:10 +000038
Kevin Enderbyccab3172009-09-15 00:27:25 +000039using namespace llvm;
40
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +000041namespace {
Bill Wendlingee7f1f92010-11-06 21:42:12 +000042
43class ARMOperand;
Jim Grosbach624bcc72010-10-29 14:46:02 +000044
Jim Grosbach04945c42011-12-02 00:35:16 +000045enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
Jim Grosbachcd6f5e72011-11-30 01:09:44 +000046
Evan Cheng11424442011-07-26 00:24:13 +000047class ARMAsmParser : public MCTargetAsmParser {
Evan Cheng91111d22011-07-09 05:47:46 +000048 MCSubtargetInfo &STI;
Kevin Enderbyccab3172009-09-15 00:27:25 +000049 MCAsmParser &Parser;
Jim Grosbachc988e0c2012-03-05 19:33:30 +000050 const MCRegisterInfo *MRI;
Kevin Enderbyccab3172009-09-15 00:27:25 +000051
Logan Chien4ea23b52013-05-10 16:17:24 +000052 // Unwind directives state
53 SMLoc FnStartLoc;
54 SMLoc CantUnwindLoc;
55 SMLoc PersonalityLoc;
56 SMLoc HandlerDataLoc;
57 int FPReg;
58 void resetUnwindDirectiveParserState() {
59 FnStartLoc = SMLoc();
60 CantUnwindLoc = SMLoc();
61 PersonalityLoc = SMLoc();
62 HandlerDataLoc = SMLoc();
63 FPReg = -1;
64 }
65
Jim Grosbachab5830e2011-12-14 02:16:11 +000066 // Map of register aliases registers via the .req directive.
67 StringMap<unsigned> RegisterReqs;
68
Jim Grosbached16ec42011-08-29 22:24:09 +000069 struct {
70 ARMCC::CondCodes Cond; // Condition for IT block.
71 unsigned Mask:4; // Condition mask for instructions.
72 // Starting at first 1 (from lsb).
73 // '1' condition as indicated in IT.
74 // '0' inverse of condition (else).
75 // Count of instructions in IT block is
76 // 4 - trailingzeroes(mask)
77
78 bool FirstCond; // Explicit flag for when we're parsing the
79 // First instruction in the IT block. It's
80 // implied in the mask, so needs special
81 // handling.
82
83 unsigned CurPosition; // Current position in parsing of IT
84 // block. In range [0,3]. Initialized
85 // according to count of instructions in block.
86 // ~0U if no active IT block.
87 } ITState;
88 bool inITBlock() { return ITState.CurPosition != ~0U;}
Jim Grosbacha0d34d32011-09-02 23:22:08 +000089 void forwardITPosition() {
90 if (!inITBlock()) return;
91 // Move to the next instruction in the IT block, if there is one. If not,
92 // mark the block as done.
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +000093 unsigned TZ = countTrailingZeros(ITState.Mask);
Jim Grosbacha0d34d32011-09-02 23:22:08 +000094 if (++ITState.CurPosition == 5 - TZ)
95 ITState.CurPosition = ~0U; // Done with the IT block after this.
96 }
Jim Grosbached16ec42011-08-29 22:24:09 +000097
98
Kevin Enderbyccab3172009-09-15 00:27:25 +000099 MCAsmParser &getParser() const { return Parser; }
Kevin Enderbyccab3172009-09-15 00:27:25 +0000100 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101
Benjamin Kramer673824b2012-04-15 17:04:27 +0000102 bool Warning(SMLoc L, const Twine &Msg,
Dmitri Gribenko3238fb72013-05-05 00:40:33 +0000103 ArrayRef<SMRange> Ranges = None) {
Benjamin Kramer673824b2012-04-15 17:04:27 +0000104 return Parser.Warning(L, Msg, Ranges);
105 }
106 bool Error(SMLoc L, const Twine &Msg,
Dmitri Gribenko3238fb72013-05-05 00:40:33 +0000107 ArrayRef<SMRange> Ranges = None) {
Benjamin Kramer673824b2012-04-15 17:04:27 +0000108 return Parser.Error(L, Msg, Ranges);
109 }
Kevin Enderbyccab3172009-09-15 00:27:25 +0000110
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000111 int tryParseRegister();
112 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach0d6022d2011-07-26 20:41:24 +0000113 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000114 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbachd3595712011-08-03 23:50:40 +0000115 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000116 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
Jim Grosbachd3595712011-08-03 23:50:40 +0000118 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119 unsigned &ShiftAmount);
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000120 bool parseDirectiveWord(unsigned Size, SMLoc L);
121 bool parseDirectiveThumb(SMLoc L);
Jim Grosbach7f882392011-12-07 18:04:19 +0000122 bool parseDirectiveARM(SMLoc L);
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000123 bool parseDirectiveThumbFunc(SMLoc L);
124 bool parseDirectiveCode(SMLoc L);
125 bool parseDirectiveSyntax(SMLoc L);
Jim Grosbachab5830e2011-12-14 02:16:11 +0000126 bool parseDirectiveReq(StringRef Name, SMLoc L);
127 bool parseDirectiveUnreq(SMLoc L);
Jason W Kim135d2442011-12-20 17:38:12 +0000128 bool parseDirectiveArch(SMLoc L);
129 bool parseDirectiveEabiAttr(SMLoc L);
Logan Chien4ea23b52013-05-10 16:17:24 +0000130 bool parseDirectiveFnStart(SMLoc L);
131 bool parseDirectiveFnEnd(SMLoc L);
132 bool parseDirectiveCantUnwind(SMLoc L);
133 bool parseDirectivePersonality(SMLoc L);
134 bool parseDirectiveHandlerData(SMLoc L);
135 bool parseDirectiveSetFP(SMLoc L);
136 bool parseDirectivePad(SMLoc L);
137 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
Kevin Enderby146dcf22009-10-15 20:48:48 +0000138
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000139 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
Jim Grosbach3d1eac82011-08-26 21:43:41 +0000140 bool &CarrySetting, unsigned &ProcessorIMod,
141 StringRef &ITMask);
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000142 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
Bruno Cardoso Lopese6290cc2011-01-18 20:55:11 +0000143 bool &CanAcceptPredicationCode);
Jim Grosbach624bcc72010-10-29 14:46:02 +0000144
Evan Cheng4d1ca962011-07-08 01:53:10 +0000145 bool isThumb() const {
146 // FIXME: Can tablegen auto-generate this?
Evan Cheng91111d22011-07-09 05:47:46 +0000147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
Evan Cheng4d1ca962011-07-08 01:53:10 +0000148 }
Evan Cheng4d1ca962011-07-08 01:53:10 +0000149 bool isThumbOne() const {
Evan Cheng91111d22011-07-09 05:47:46 +0000150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
Evan Cheng4d1ca962011-07-08 01:53:10 +0000151 }
Jim Grosbach3e941ae2011-08-16 20:45:50 +0000152 bool isThumbTwo() const {
153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
154 }
Tim Northovera2292d02013-06-10 23:20:58 +0000155 bool hasThumb() const {
156 return STI.getFeatureBits() & ARM::HasV4TOps;
157 }
Jim Grosbachb7fa2c02011-08-16 22:20:01 +0000158 bool hasV6Ops() const {
159 return STI.getFeatureBits() & ARM::HasV6Ops;
160 }
James Molloy21efa7d2011-09-28 14:21:38 +0000161 bool hasV7Ops() const {
162 return STI.getFeatureBits() & ARM::HasV7Ops;
163 }
Joey Goulyb3f550e2013-06-26 16:58:26 +0000164 bool hasV8Ops() const {
165 return STI.getFeatureBits() & ARM::HasV8Ops;
166 }
Tim Northovera2292d02013-06-10 23:20:58 +0000167 bool hasARM() const {
168 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
169 }
170
Evan Cheng284b4672011-07-08 22:36:29 +0000171 void SwitchMode() {
Evan Cheng91111d22011-07-09 05:47:46 +0000172 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173 setAvailableFeatures(FB);
Evan Cheng284b4672011-07-08 22:36:29 +0000174 }
James Molloy21efa7d2011-09-28 14:21:38 +0000175 bool isMClass() const {
176 return STI.getFeatureBits() & ARM::FeatureMClass;
177 }
Evan Cheng4d1ca962011-07-08 01:53:10 +0000178
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000179 /// @name Auto-generated Match Functions
180 /// {
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +0000181
Chris Lattner3e4582a2010-09-06 19:11:01 +0000182#define GET_ASSEMBLER_HEADER
183#include "ARMGenAsmMatcher.inc"
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000184
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000185 /// }
186
Jim Grosbach3d1eac82011-08-26 21:43:41 +0000187 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach2d6ef442011-07-25 20:14:50 +0000188 OperandMatchResultTy parseCoprocNumOperand(
Jim Grosbach861e49c2011-02-12 01:34:40 +0000189 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach2d6ef442011-07-25 20:14:50 +0000190 OperandMatchResultTy parseCoprocRegOperand(
Jim Grosbach861e49c2011-02-12 01:34:40 +0000191 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach48399582011-10-12 17:34:41 +0000192 OperandMatchResultTy parseCoprocOptionOperand(
193 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach2d6ef442011-07-25 20:14:50 +0000194 OperandMatchResultTy parseMemBarrierOptOperand(
Bruno Cardoso Lopescdd20af2011-02-18 19:49:06 +0000195 SmallVectorImpl<MCParsedAsmOperand*>&);
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000196 OperandMatchResultTy parseInstSyncBarrierOptOperand(
197 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach2d6ef442011-07-25 20:14:50 +0000198 OperandMatchResultTy parseProcIFlagsOperand(
Bruno Cardoso Lopescdd20af2011-02-18 19:49:06 +0000199 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach2d6ef442011-07-25 20:14:50 +0000200 OperandMatchResultTy parseMSRMaskOperand(
Bruno Cardoso Lopescdd20af2011-02-18 19:49:06 +0000201 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach27c1e252011-07-21 17:23:04 +0000202 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203 StringRef Op, int Low, int High);
204 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205 return parsePKHImm(O, "lsl", 0, 31);
206 }
207 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208 return parsePKHImm(O, "asr", 1, 32);
209 }
Jim Grosbach0a547702011-07-22 17:44:50 +0000210 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach3a9cbee2011-07-25 22:20:28 +0000211 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach833b9d32011-07-27 20:15:40 +0000212 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach864b6092011-07-28 21:34:26 +0000213 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbachd3595712011-08-03 23:50:40 +0000214 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach1d9d5e92011-08-10 21:56:18 +0000215 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbache7fbce72011-10-03 23:38:36 +0000216 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbachad47cfc2011-10-18 23:02:30 +0000217 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
Jordan Rosee8f1eae2013-01-07 19:00:49 +0000218 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
219 SMLoc &EndLoc);
Bruno Cardoso Lopesab830502011-03-31 23:26:08 +0000220
221 // Asm Match Converter Methods
Chad Rosier451ef132012-08-31 22:12:31 +0000222 void cvtThumbMultiply(MCInst &Inst,
Jim Grosbach8e048492011-08-19 22:07:46 +0000223 const SmallVectorImpl<MCParsedAsmOperand*> &);
Mihai Popaad18d3c2013-08-09 10:38:32 +0000224 void cvtThumbBranches(MCInst &Inst,
225 const SmallVectorImpl<MCParsedAsmOperand*> &);
226
Jim Grosbachedaa35a2011-07-26 18:25:39 +0000227 bool validateInstruction(MCInst &Inst,
228 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
Jim Grosbachafad0532011-11-10 23:42:14 +0000229 bool processInstruction(MCInst &Inst,
Jim Grosbach8ba76c62011-08-11 17:35:48 +0000230 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
Jim Grosbach7283da92011-08-16 21:12:37 +0000231 bool shouldOmitCCOutOperand(StringRef Mnemonic,
232 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Joey Goulye8602552013-07-19 16:34:16 +0000233 bool shouldOmitPredicateOperand(StringRef Mnemonic,
234 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Joey Gouly5d0564d2013-08-02 19:18:12 +0000235 bool isDeprecated(MCInst &Inst, StringRef &Info);
Jim Grosbachedaa35a2011-07-26 18:25:39 +0000236
Kevin Enderbyccab3172009-09-15 00:27:25 +0000237public:
Jim Grosbach3e941ae2011-08-16 20:45:50 +0000238 enum ARMMatchResultTy {
Jim Grosbachb7fa2c02011-08-16 22:20:01 +0000239 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
Jim Grosbached16ec42011-08-29 22:24:09 +0000240 Match_RequiresNotITBlock,
Jim Grosbachb7fa2c02011-08-16 22:20:01 +0000241 Match_RequiresV6,
Jim Grosbach087affe2012-06-22 23:56:48 +0000242 Match_RequiresThumb2,
243#define GET_OPERAND_DIAGNOSTIC_TYPES
244#include "ARMGenAsmMatcher.inc"
245
Jim Grosbach3e941ae2011-08-16 20:45:50 +0000246 };
247
Evan Cheng91111d22011-07-09 05:47:46 +0000248 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
Logan Chien4ea23b52013-05-10 16:17:24 +0000249 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
Evan Cheng4d1ca962011-07-08 01:53:10 +0000250 MCAsmParserExtension::Initialize(_Parser);
Evan Cheng284b4672011-07-08 22:36:29 +0000251
Jim Grosbachc988e0c2012-03-05 19:33:30 +0000252 // Cache the MCRegisterInfo.
Bill Wendlingbc07a892013-06-18 07:20:20 +0000253 MRI = getContext().getRegisterInfo();
Jim Grosbachc988e0c2012-03-05 19:33:30 +0000254
Evan Cheng4d1ca962011-07-08 01:53:10 +0000255 // Initialize the set of available features.
Evan Cheng91111d22011-07-09 05:47:46 +0000256 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
Jim Grosbached16ec42011-08-29 22:24:09 +0000257
258 // Not in an ITBlock to start with.
259 ITState.CurPosition = ~0U;
Jack Carter718da0b2013-01-30 02:24:33 +0000260
261 // Set ELF header flags.
262 // FIXME: This should eventually end up somewhere else where more
263 // intelligent flag decisions can be made. For now we are just maintaining
Chandler Carruthe5d8d0d2013-01-31 23:43:14 +0000264 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
265 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
266 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
Evan Cheng4d1ca962011-07-08 01:53:10 +0000267 }
Kevin Enderbyccab3172009-09-15 00:27:25 +0000268
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000269 // Implementation of the MCTargetAsmParser interface:
270 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
Chad Rosierf0e87202012-10-25 20:41:34 +0000271 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
272 SMLoc NameLoc,
Jim Grosbachedaa35a2011-07-26 18:25:39 +0000273 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000274 bool ParseDirective(AsmToken DirectiveID);
275
Jim Grosbach231e7aa2013-02-06 06:00:11 +0000276 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
Jim Grosbach3e941ae2011-08-16 20:45:50 +0000277 unsigned checkTargetMatchPredicate(MCInst &Inst);
278
Chad Rosier49963552012-10-13 00:26:04 +0000279 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
Jim Grosbacheab1c0d2011-07-26 17:10:22 +0000280 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
Chad Rosier49963552012-10-13 00:26:04 +0000281 MCStreamer &Out, unsigned &ErrorInfo,
282 bool MatchingInlineAsm);
Kevin Enderbyccab3172009-09-15 00:27:25 +0000283};
Jim Grosbach624bcc72010-10-29 14:46:02 +0000284} // end anonymous namespace
285
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +0000286namespace {
287
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000288/// ARMOperand - Instances of this class represent a parsed ARM machine
Joel Jones54597542013-01-09 22:34:16 +0000289/// operand.
Bill Wendlingee7f1f92010-11-06 21:42:12 +0000290class ARMOperand : public MCParsedAsmOperand {
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000291 enum KindTy {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000292 k_CondCode,
293 k_CCOut,
294 k_ITCondMask,
295 k_CoprocNum,
296 k_CoprocReg,
Jim Grosbach48399582011-10-12 17:34:41 +0000297 k_CoprocOption,
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000298 k_Immediate,
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000299 k_MemBarrierOpt,
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000300 k_InstSyncBarrierOpt,
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000301 k_Memory,
302 k_PostIndexRegister,
303 k_MSRMask,
304 k_ProcIFlags,
Jim Grosbachd0637bf2011-10-07 23:56:00 +0000305 k_VectorIndex,
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000306 k_Register,
307 k_RegisterList,
308 k_DPRRegisterList,
309 k_SPRRegisterList,
Jim Grosbachad47cfc2011-10-18 23:02:30 +0000310 k_VectorList,
Jim Grosbachcd6f5e72011-11-30 01:09:44 +0000311 k_VectorListAllLanes,
Jim Grosbach04945c42011-12-02 00:35:16 +0000312 k_VectorListIndexed,
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000313 k_ShiftedRegister,
314 k_ShiftedImmediate,
315 k_ShifterImmediate,
316 k_RotateImmediate,
317 k_BitfieldDescriptor,
318 k_Token
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000319 } Kind;
320
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000321 SMLoc StartLoc, EndLoc;
Bill Wendling0ab0f672010-11-18 21:50:54 +0000322 SmallVector<unsigned, 8> Registers;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000323
Eric Christopher8996c5d2013-03-15 00:42:55 +0000324 struct CCOp {
325 ARMCC::CondCodes Val;
326 };
327
328 struct CopOp {
329 unsigned Val;
330 };
331
332 struct CoprocOptionOp {
333 unsigned Val;
334 };
335
336 struct ITMaskOp {
337 unsigned Mask:4;
338 };
339
340 struct MBOptOp {
341 ARM_MB::MemBOpt Val;
342 };
343
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000344 struct ISBOptOp {
345 ARM_ISB::InstSyncBOpt Val;
346 };
347
Eric Christopher8996c5d2013-03-15 00:42:55 +0000348 struct IFlagsOp {
349 ARM_PROC::IFlags Val;
350 };
351
352 struct MMaskOp {
353 unsigned Val;
354 };
355
356 struct TokOp {
357 const char *Data;
358 unsigned Length;
359 };
360
361 struct RegOp {
362 unsigned RegNum;
363 };
364
365 // A vector register list is a sequential list of 1 to 4 registers.
366 struct VectorListOp {
367 unsigned RegNum;
368 unsigned Count;
369 unsigned LaneIndex;
370 bool isDoubleSpaced;
371 };
372
373 struct VectorIndexOp {
374 unsigned Val;
375 };
376
377 struct ImmOp {
378 const MCExpr *Val;
379 };
380
381 /// Combined record for all forms of ARM address expressions.
382 struct MemoryOp {
383 unsigned BaseRegNum;
384 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
385 // was specified.
386 const MCConstantExpr *OffsetImm; // Offset immediate value
387 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
388 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
389 unsigned ShiftImm; // shift for OffsetReg.
390 unsigned Alignment; // 0 = no alignment specified
391 // n = alignment in bytes (2, 4, 8, 16, or 32)
392 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
393 };
394
395 struct PostIdxRegOp {
396 unsigned RegNum;
397 bool isAdd;
398 ARM_AM::ShiftOpc ShiftTy;
399 unsigned ShiftImm;
400 };
401
402 struct ShifterImmOp {
403 bool isASR;
404 unsigned Imm;
405 };
406
407 struct RegShiftedRegOp {
408 ARM_AM::ShiftOpc ShiftTy;
409 unsigned SrcReg;
410 unsigned ShiftReg;
411 unsigned ShiftImm;
412 };
413
414 struct RegShiftedImmOp {
415 ARM_AM::ShiftOpc ShiftTy;
416 unsigned SrcReg;
417 unsigned ShiftImm;
418 };
419
420 struct RotImmOp {
421 unsigned Imm;
422 };
423
424 struct BitfieldOp {
425 unsigned LSB;
426 unsigned Width;
427 };
428
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000429 union {
Eric Christopher8996c5d2013-03-15 00:42:55 +0000430 struct CCOp CC;
431 struct CopOp Cop;
432 struct CoprocOptionOp CoprocOption;
433 struct MBOptOp MBOpt;
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000434 struct ISBOptOp ISBOpt;
Eric Christopher8996c5d2013-03-15 00:42:55 +0000435 struct ITMaskOp ITMask;
436 struct IFlagsOp IFlags;
437 struct MMaskOp MMask;
438 struct TokOp Tok;
439 struct RegOp Reg;
440 struct VectorListOp VectorList;
441 struct VectorIndexOp VectorIndex;
442 struct ImmOp Imm;
443 struct MemoryOp Memory;
444 struct PostIdxRegOp PostIdxReg;
445 struct ShifterImmOp ShifterImm;
446 struct RegShiftedRegOp RegShiftedReg;
447 struct RegShiftedImmOp RegShiftedImm;
448 struct RotImmOp RotImm;
449 struct BitfieldOp Bitfield;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000450 };
Jim Grosbach624bcc72010-10-29 14:46:02 +0000451
Bill Wendlingee7f1f92010-11-06 21:42:12 +0000452 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
453public:
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000454 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
455 Kind = o.Kind;
456 StartLoc = o.StartLoc;
457 EndLoc = o.EndLoc;
458 switch (Kind) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000459 case k_CondCode:
Daniel Dunbard8042b72010-08-11 06:36:53 +0000460 CC = o.CC;
461 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000462 case k_ITCondMask:
Jim Grosbach3d1eac82011-08-26 21:43:41 +0000463 ITMask = o.ITMask;
464 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000465 case k_Token:
Daniel Dunbard8042b72010-08-11 06:36:53 +0000466 Tok = o.Tok;
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000467 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000468 case k_CCOut:
469 case k_Register:
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000470 Reg = o.Reg;
471 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000472 case k_RegisterList:
473 case k_DPRRegisterList:
474 case k_SPRRegisterList:
Bill Wendling0ab0f672010-11-18 21:50:54 +0000475 Registers = o.Registers;
Bill Wendling7cef4472010-11-06 19:56:04 +0000476 break;
Jim Grosbachad47cfc2011-10-18 23:02:30 +0000477 case k_VectorList:
Jim Grosbachcd6f5e72011-11-30 01:09:44 +0000478 case k_VectorListAllLanes:
Jim Grosbach04945c42011-12-02 00:35:16 +0000479 case k_VectorListIndexed:
Jim Grosbachad47cfc2011-10-18 23:02:30 +0000480 VectorList = o.VectorList;
481 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000482 case k_CoprocNum:
483 case k_CoprocReg:
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +0000484 Cop = o.Cop;
485 break;
Jim Grosbach48399582011-10-12 17:34:41 +0000486 case k_CoprocOption:
487 CoprocOption = o.CoprocOption;
488 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000489 case k_Immediate:
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000490 Imm = o.Imm;
491 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000492 case k_MemBarrierOpt:
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +0000493 MBOpt = o.MBOpt;
494 break;
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000495 case k_InstSyncBarrierOpt:
496 ISBOpt = o.ISBOpt;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000497 case k_Memory:
Jim Grosbach871dff72011-10-11 15:59:20 +0000498 Memory = o.Memory;
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000499 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000500 case k_PostIndexRegister:
Jim Grosbachd3595712011-08-03 23:50:40 +0000501 PostIdxReg = o.PostIdxReg;
502 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000503 case k_MSRMask:
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +0000504 MMask = o.MMask;
505 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000506 case k_ProcIFlags:
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +0000507 IFlags = o.IFlags;
Owen Anderson1d2f5ce2011-03-18 22:50:18 +0000508 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000509 case k_ShifterImmediate:
Jim Grosbach3a9cbee2011-07-25 22:20:28 +0000510 ShifterImm = o.ShifterImm;
Owen Anderson1d2f5ce2011-03-18 22:50:18 +0000511 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000512 case k_ShiftedRegister:
Jim Grosbachac798e12011-07-25 20:49:51 +0000513 RegShiftedReg = o.RegShiftedReg;
Jim Grosbach7dcd1352011-07-13 17:50:29 +0000514 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000515 case k_ShiftedImmediate:
Jim Grosbachac798e12011-07-25 20:49:51 +0000516 RegShiftedImm = o.RegShiftedImm;
Owen Andersonb595ed02011-07-21 18:54:16 +0000517 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000518 case k_RotateImmediate:
Jim Grosbach833b9d32011-07-27 20:15:40 +0000519 RotImm = o.RotImm;
520 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000521 case k_BitfieldDescriptor:
Jim Grosbach864b6092011-07-28 21:34:26 +0000522 Bitfield = o.Bitfield;
523 break;
Jim Grosbachd0637bf2011-10-07 23:56:00 +0000524 case k_VectorIndex:
525 VectorIndex = o.VectorIndex;
526 break;
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000527 }
528 }
Jim Grosbach624bcc72010-10-29 14:46:02 +0000529
Sean Callanan7ad0ad02010-04-02 22:27:05 +0000530 /// getStartLoc - Get the location of the first token of this operand.
531 SMLoc getStartLoc() const { return StartLoc; }
532 /// getEndLoc - Get the location of the last token of this operand.
533 SMLoc getEndLoc() const { return EndLoc; }
Chad Rosier143d0f72012-09-21 20:51:43 +0000534 /// getLocRange - Get the range between the first and last token of this
535 /// operand.
Benjamin Kramer673824b2012-04-15 17:04:27 +0000536 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
537
Daniel Dunbard8042b72010-08-11 06:36:53 +0000538 ARMCC::CondCodes getCondCode() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000539 assert(Kind == k_CondCode && "Invalid access!");
Daniel Dunbard8042b72010-08-11 06:36:53 +0000540 return CC.Val;
541 }
542
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +0000543 unsigned getCoproc() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000544 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +0000545 return Cop.Val;
546 }
547
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000548 StringRef getToken() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000549 assert(Kind == k_Token && "Invalid access!");
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000550 return StringRef(Tok.Data, Tok.Length);
551 }
552
553 unsigned getReg() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000554 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
Bill Wendling2cae3272010-11-09 22:44:22 +0000555 return Reg.RegNum;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +0000556 }
557
Bill Wendlingbed94652010-11-09 23:28:44 +0000558 const SmallVectorImpl<unsigned> &getRegList() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000559 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
560 Kind == k_SPRRegisterList) && "Invalid access!");
Bill Wendling0ab0f672010-11-18 21:50:54 +0000561 return Registers;
Bill Wendling7cef4472010-11-06 19:56:04 +0000562 }
563
Kevin Enderbyf5079942009-10-13 22:19:02 +0000564 const MCExpr *getImm() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000565 assert(isImm() && "Invalid access!");
Kevin Enderbyf5079942009-10-13 22:19:02 +0000566 return Imm.Val;
567 }
568
Jim Grosbachd0637bf2011-10-07 23:56:00 +0000569 unsigned getVectorIndex() const {
570 assert(Kind == k_VectorIndex && "Invalid access!");
571 return VectorIndex.Val;
572 }
573
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +0000574 ARM_MB::MemBOpt getMemBarrierOpt() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000575 assert(Kind == k_MemBarrierOpt && "Invalid access!");
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +0000576 return MBOpt.Val;
577 }
578
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000579 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
580 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
581 return ISBOpt.Val;
582 }
583
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +0000584 ARM_PROC::IFlags getProcIFlags() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000585 assert(Kind == k_ProcIFlags && "Invalid access!");
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +0000586 return IFlags.Val;
587 }
588
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +0000589 unsigned getMSRMask() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000590 assert(Kind == k_MSRMask && "Invalid access!");
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +0000591 return MMask.Val;
592 }
593
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000594 bool isCoprocNum() const { return Kind == k_CoprocNum; }
595 bool isCoprocReg() const { return Kind == k_CoprocReg; }
Jim Grosbach48399582011-10-12 17:34:41 +0000596 bool isCoprocOption() const { return Kind == k_CoprocOption; }
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000597 bool isCondCode() const { return Kind == k_CondCode; }
598 bool isCCOut() const { return Kind == k_CCOut; }
599 bool isITMask() const { return Kind == k_ITCondMask; }
600 bool isITCondCode() const { return Kind == k_CondCode; }
601 bool isImm() const { return Kind == k_Immediate; }
Mihai Popad36cbaa2013-07-03 09:21:44 +0000602 // checks whether this operand is an unsigned offset which fits is a field
603 // of specified width and scaled by a specific number of bits
604 template<unsigned width, unsigned scale>
605 bool isUnsignedOffset() const {
606 if (!isImm()) return false;
Mihai Popaad18d3c2013-08-09 10:38:32 +0000607 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
Mihai Popad36cbaa2013-07-03 09:21:44 +0000608 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
609 int64_t Val = CE->getValue();
610 int64_t Align = 1LL << scale;
611 int64_t Max = Align * ((1LL << width) - 1);
612 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
613 }
614 return false;
615 }
Mihai Popaad18d3c2013-08-09 10:38:32 +0000616 // checks whether this operand is an signed offset which fits is a field
617 // of specified width and scaled by a specific number of bits
618 template<unsigned width, unsigned scale>
619 bool isSignedOffset() const {
620 if (!isImm()) return false;
621 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
622 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
623 int64_t Val = CE->getValue();
624 int64_t Align = 1LL << scale;
625 int64_t Max = Align * ((1LL << (width-1)) - 1);
626 int64_t Min = -Align * (1LL << (width-1));
627 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
628 }
629 return false;
630 }
631
Mihai Popa8a9da5b2013-07-22 15:49:36 +0000632 // checks whether this operand is a memory operand computed as an offset
633 // applied to PC. the offset may have 8 bits of magnitude and is represented
634 // with two bits of shift. textually it may be either [pc, #imm], #imm or
635 // relocable expression...
636 bool isThumbMemPC() const {
637 int64_t Val = 0;
638 if (isImm()) {
639 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
641 if (!CE) return false;
642 Val = CE->getValue();
643 }
644 else if (isMem()) {
645 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
646 if(Memory.BaseRegNum != ARM::PC) return false;
647 Val = Memory.OffsetImm->getValue();
648 }
649 else return false;
Mihai Popad79f00b2013-08-15 15:43:06 +0000650 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
Mihai Popa8a9da5b2013-07-22 15:49:36 +0000651 }
Jim Grosbacha9d36fb2012-01-20 18:09:51 +0000652 bool isFPImm() const {
653 if (!isImm()) return false;
654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
655 if (!CE) return false;
656 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
657 return Val != -1;
658 }
Jim Grosbachea231912011-12-22 22:19:05 +0000659 bool isFBits16() const {
660 if (!isImm()) return false;
661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662 if (!CE) return false;
663 int64_t Value = CE->getValue();
664 return Value >= 0 && Value <= 16;
665 }
666 bool isFBits32() const {
667 if (!isImm()) return false;
668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
669 if (!CE) return false;
670 int64_t Value = CE->getValue();
671 return Value >= 1 && Value <= 32;
672 }
Jim Grosbach7db8d692011-09-08 22:07:06 +0000673 bool isImm8s4() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000674 if (!isImm()) return false;
Jim Grosbach7db8d692011-09-08 22:07:06 +0000675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676 if (!CE) return false;
677 int64_t Value = CE->getValue();
678 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
679 }
Quentin Colombet6f03f622013-04-17 18:46:12 +0000680 bool isImm0_4() const {
681 if (!isImm()) return false;
682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683 if (!CE) return false;
684 int64_t Value = CE->getValue();
685 return Value >= 0 && Value < 5;
686 }
Jim Grosbach0a0b3072011-08-24 21:22:15 +0000687 bool isImm0_1020s4() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000688 if (!isImm()) return false;
Jim Grosbach0a0b3072011-08-24 21:22:15 +0000689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690 if (!CE) return false;
691 int64_t Value = CE->getValue();
692 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
693 }
694 bool isImm0_508s4() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000695 if (!isImm()) return false;
Jim Grosbach0a0b3072011-08-24 21:22:15 +0000696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
697 if (!CE) return false;
698 int64_t Value = CE->getValue();
699 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
700 }
Jim Grosbach930f2f62012-04-05 20:57:13 +0000701 bool isImm0_508s4Neg() const {
702 if (!isImm()) return false;
703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704 if (!CE) return false;
705 int64_t Value = -CE->getValue();
706 // explicitly exclude zero. we want that to use the normal 0_508 version.
707 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
708 }
Jim Grosbacha6f7a1e2011-06-27 23:54:06 +0000709 bool isImm0_255() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000710 if (!isImm()) return false;
Jim Grosbacha6f7a1e2011-06-27 23:54:06 +0000711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712 if (!CE) return false;
713 int64_t Value = CE->getValue();
714 return Value >= 0 && Value < 256;
715 }
Jim Grosbach930f2f62012-04-05 20:57:13 +0000716 bool isImm0_4095() const {
717 if (!isImm()) return false;
718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
719 if (!CE) return false;
720 int64_t Value = CE->getValue();
721 return Value >= 0 && Value < 4096;
722 }
723 bool isImm0_4095Neg() const {
724 if (!isImm()) return false;
725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
726 if (!CE) return false;
727 int64_t Value = -CE->getValue();
728 return Value > 0 && Value < 4096;
729 }
Jim Grosbach9dff9f42011-12-02 23:34:39 +0000730 bool isImm0_1() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000731 if (!isImm()) return false;
Jim Grosbach9dff9f42011-12-02 23:34:39 +0000732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
733 if (!CE) return false;
734 int64_t Value = CE->getValue();
735 return Value >= 0 && Value < 2;
736 }
737 bool isImm0_3() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000738 if (!isImm()) return false;
Jim Grosbach9dff9f42011-12-02 23:34:39 +0000739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
740 if (!CE) return false;
741 int64_t Value = CE->getValue();
742 return Value >= 0 && Value < 4;
743 }
Jim Grosbach31756c22011-07-13 22:01:08 +0000744 bool isImm0_7() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000745 if (!isImm()) return false;
Jim Grosbach31756c22011-07-13 22:01:08 +0000746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747 if (!CE) return false;
748 int64_t Value = CE->getValue();
749 return Value >= 0 && Value < 8;
750 }
751 bool isImm0_15() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000752 if (!isImm()) return false;
Jim Grosbach31756c22011-07-13 22:01:08 +0000753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
754 if (!CE) return false;
755 int64_t Value = CE->getValue();
756 return Value >= 0 && Value < 16;
757 }
Jim Grosbach72e7c4f2011-07-21 23:26:25 +0000758 bool isImm0_31() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000759 if (!isImm()) return false;
Jim Grosbach72e7c4f2011-07-21 23:26:25 +0000760 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
761 if (!CE) return false;
762 int64_t Value = CE->getValue();
763 return Value >= 0 && Value < 32;
764 }
Jim Grosbach00326402011-12-08 01:30:04 +0000765 bool isImm0_63() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000766 if (!isImm()) return false;
Jim Grosbach00326402011-12-08 01:30:04 +0000767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
768 if (!CE) return false;
769 int64_t Value = CE->getValue();
770 return Value >= 0 && Value < 64;
771 }
Jim Grosbachd4b82492011-12-07 01:07:24 +0000772 bool isImm8() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000773 if (!isImm()) return false;
Jim Grosbachd4b82492011-12-07 01:07:24 +0000774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
775 if (!CE) return false;
776 int64_t Value = CE->getValue();
777 return Value == 8;
778 }
779 bool isImm16() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000780 if (!isImm()) return false;
Jim Grosbachd4b82492011-12-07 01:07:24 +0000781 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
782 if (!CE) return false;
783 int64_t Value = CE->getValue();
784 return Value == 16;
785 }
786 bool isImm32() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000787 if (!isImm()) return false;
Jim Grosbachd4b82492011-12-07 01:07:24 +0000788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
789 if (!CE) return false;
790 int64_t Value = CE->getValue();
791 return Value == 32;
792 }
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000793 bool isShrImm8() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000794 if (!isImm()) return false;
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
796 if (!CE) return false;
797 int64_t Value = CE->getValue();
798 return Value > 0 && Value <= 8;
799 }
800 bool isShrImm16() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000801 if (!isImm()) return false;
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
803 if (!CE) return false;
804 int64_t Value = CE->getValue();
805 return Value > 0 && Value <= 16;
806 }
807 bool isShrImm32() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000808 if (!isImm()) return false;
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
810 if (!CE) return false;
811 int64_t Value = CE->getValue();
812 return Value > 0 && Value <= 32;
813 }
814 bool isShrImm64() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000815 if (!isImm()) return false;
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817 if (!CE) return false;
818 int64_t Value = CE->getValue();
819 return Value > 0 && Value <= 64;
820 }
Jim Grosbachd4b82492011-12-07 01:07:24 +0000821 bool isImm1_7() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000822 if (!isImm()) return false;
Jim Grosbachd4b82492011-12-07 01:07:24 +0000823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
824 if (!CE) return false;
825 int64_t Value = CE->getValue();
826 return Value > 0 && Value < 8;
827 }
828 bool isImm1_15() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000829 if (!isImm()) return false;
Jim Grosbachd4b82492011-12-07 01:07:24 +0000830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831 if (!CE) return false;
832 int64_t Value = CE->getValue();
833 return Value > 0 && Value < 16;
834 }
835 bool isImm1_31() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000836 if (!isImm()) return false;
Jim Grosbachd4b82492011-12-07 01:07:24 +0000837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838 if (!CE) return false;
839 int64_t Value = CE->getValue();
840 return Value > 0 && Value < 32;
841 }
Jim Grosbach475c6db2011-07-25 23:09:14 +0000842 bool isImm1_16() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000843 if (!isImm()) return false;
Jim Grosbach475c6db2011-07-25 23:09:14 +0000844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845 if (!CE) return false;
846 int64_t Value = CE->getValue();
847 return Value > 0 && Value < 17;
848 }
Jim Grosbach801e0a32011-07-22 23:16:18 +0000849 bool isImm1_32() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000850 if (!isImm()) return false;
Jim Grosbach801e0a32011-07-22 23:16:18 +0000851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852 if (!CE) return false;
853 int64_t Value = CE->getValue();
854 return Value > 0 && Value < 33;
855 }
Jim Grosbachc14871c2011-11-10 19:18:01 +0000856 bool isImm0_32() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000857 if (!isImm()) return false;
Jim Grosbachc14871c2011-11-10 19:18:01 +0000858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859 if (!CE) return false;
860 int64_t Value = CE->getValue();
861 return Value >= 0 && Value < 33;
862 }
Jim Grosbach975b6412011-07-13 20:10:10 +0000863 bool isImm0_65535() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000864 if (!isImm()) return false;
Jim Grosbach975b6412011-07-13 20:10:10 +0000865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866 if (!CE) return false;
867 int64_t Value = CE->getValue();
868 return Value >= 0 && Value < 65536;
869 }
Jim Grosbach7c09e3c2011-07-19 19:13:28 +0000870 bool isImm0_65535Expr() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000871 if (!isImm()) return false;
Jim Grosbach7c09e3c2011-07-19 19:13:28 +0000872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873 // If it's not a constant expression, it'll generate a fixup and be
874 // handled later.
875 if (!CE) return true;
876 int64_t Value = CE->getValue();
877 return Value >= 0 && Value < 65536;
878 }
Jim Grosbachf1637842011-07-26 16:24:27 +0000879 bool isImm24bit() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000880 if (!isImm()) return false;
Jim Grosbachf1637842011-07-26 16:24:27 +0000881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
882 if (!CE) return false;
883 int64_t Value = CE->getValue();
884 return Value >= 0 && Value <= 0xffffff;
885 }
Jim Grosbach46dd4132011-08-17 21:51:27 +0000886 bool isImmThumbSR() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000887 if (!isImm()) return false;
Jim Grosbach46dd4132011-08-17 21:51:27 +0000888 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
889 if (!CE) return false;
890 int64_t Value = CE->getValue();
891 return Value > 0 && Value < 33;
892 }
Jim Grosbach27c1e252011-07-21 17:23:04 +0000893 bool isPKHLSLImm() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000894 if (!isImm()) return false;
Jim Grosbach27c1e252011-07-21 17:23:04 +0000895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
896 if (!CE) return false;
897 int64_t Value = CE->getValue();
898 return Value >= 0 && Value < 32;
899 }
900 bool isPKHASRImm() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000901 if (!isImm()) return false;
Jim Grosbach27c1e252011-07-21 17:23:04 +0000902 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
903 if (!CE) return false;
904 int64_t Value = CE->getValue();
905 return Value > 0 && Value <= 32;
906 }
Jiangning Liu10dd40e2012-08-02 08:13:13 +0000907 bool isAdrLabel() const {
908 // If we have an immediate that's not a constant, treat it as a label
909 // reference needing a fixup. If it is a constant, but it can't fit
910 // into shift immediate encoding, we reject it.
911 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
912 else return (isARMSOImm() || isARMSOImmNeg());
913 }
Jim Grosbach9720dcf2011-07-19 16:50:30 +0000914 bool isARMSOImm() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000915 if (!isImm()) return false;
Jim Grosbach9720dcf2011-07-19 16:50:30 +0000916 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
917 if (!CE) return false;
918 int64_t Value = CE->getValue();
919 return ARM_AM::getSOImmVal(Value) != -1;
920 }
Jim Grosbach3d785ed2011-10-28 22:50:54 +0000921 bool isARMSOImmNot() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000922 if (!isImm()) return false;
Jim Grosbach3d785ed2011-10-28 22:50:54 +0000923 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
924 if (!CE) return false;
925 int64_t Value = CE->getValue();
926 return ARM_AM::getSOImmVal(~Value) != -1;
927 }
Jim Grosbach30506252011-12-08 00:31:07 +0000928 bool isARMSOImmNeg() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000929 if (!isImm()) return false;
Jim Grosbach30506252011-12-08 00:31:07 +0000930 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
931 if (!CE) return false;
932 int64_t Value = CE->getValue();
Jim Grosbachfdaab532012-03-30 19:59:02 +0000933 // Only use this when not representable as a plain so_imm.
934 return ARM_AM::getSOImmVal(Value) == -1 &&
935 ARM_AM::getSOImmVal(-Value) != -1;
Jim Grosbach30506252011-12-08 00:31:07 +0000936 }
Jim Grosbacha6f7a1e2011-06-27 23:54:06 +0000937 bool isT2SOImm() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000938 if (!isImm()) return false;
Jim Grosbacha6f7a1e2011-06-27 23:54:06 +0000939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940 if (!CE) return false;
941 int64_t Value = CE->getValue();
942 return ARM_AM::getT2SOImmVal(Value) != -1;
943 }
Jim Grosbachb009a872011-10-28 22:36:30 +0000944 bool isT2SOImmNot() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000945 if (!isImm()) return false;
Jim Grosbachb009a872011-10-28 22:36:30 +0000946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947 if (!CE) return false;
948 int64_t Value = CE->getValue();
Mihai Popacf276b22013-08-16 11:55:44 +0000949 return ARM_AM::getT2SOImmVal(Value) == -1 &&
950 ARM_AM::getT2SOImmVal(~Value) != -1;
Jim Grosbachb009a872011-10-28 22:36:30 +0000951 }
Jim Grosbach30506252011-12-08 00:31:07 +0000952 bool isT2SOImmNeg() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000953 if (!isImm()) return false;
Jim Grosbach30506252011-12-08 00:31:07 +0000954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955 if (!CE) return false;
956 int64_t Value = CE->getValue();
Jim Grosbachfdaab532012-03-30 19:59:02 +0000957 // Only use this when not representable as a plain so_imm.
958 return ARM_AM::getT2SOImmVal(Value) == -1 &&
959 ARM_AM::getT2SOImmVal(-Value) != -1;
Jim Grosbach30506252011-12-08 00:31:07 +0000960 }
Jim Grosbach0a547702011-07-22 17:44:50 +0000961 bool isSetEndImm() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +0000962 if (!isImm()) return false;
Jim Grosbach0a547702011-07-22 17:44:50 +0000963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 if (!CE) return false;
965 int64_t Value = CE->getValue();
966 return Value == 1 || Value == 0;
967 }
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000968 bool isReg() const { return Kind == k_Register; }
969 bool isRegList() const { return Kind == k_RegisterList; }
970 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
971 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
972 bool isToken() const { return Kind == k_Token; }
973 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000974 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
Chad Rosier41099832012-09-11 23:02:35 +0000975 bool isMem() const { return Kind == k_Memory; }
Jim Grosbach6e5778f2011-10-07 23:24:09 +0000976 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
977 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
978 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
979 bool isRotImm() const { return Kind == k_RotateImmediate; }
980 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
981 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
Jim Grosbachc320c852011-08-05 21:28:30 +0000982 bool isPostIdxReg() const {
Jim Grosbachee201fa2011-11-14 17:52:47 +0000983 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
Jim Grosbachc320c852011-08-05 21:28:30 +0000984 }
Jim Grosbacha95ec992011-10-11 17:29:55 +0000985 bool isMemNoOffset(bool alignOK = false) const {
Chad Rosier41099832012-09-11 23:02:35 +0000986 if (!isMem())
Bruno Cardoso Lopesab830502011-03-31 23:26:08 +0000987 return false;
Jim Grosbachd3595712011-08-03 23:50:40 +0000988 // No offset of any kind.
Jim Grosbacha95ec992011-10-11 17:29:55 +0000989 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
990 (alignOK || Memory.Alignment == 0);
991 }
Jim Grosbach94298a92012-01-18 22:46:46 +0000992 bool isMemPCRelImm12() const {
Chad Rosier41099832012-09-11 23:02:35 +0000993 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbach94298a92012-01-18 22:46:46 +0000994 return false;
995 // Base register must be PC.
996 if (Memory.BaseRegNum != ARM::PC)
997 return false;
998 // Immediate offset in range [-4095, 4095].
999 if (!Memory.OffsetImm) return true;
1000 int64_t Val = Memory.OffsetImm->getValue();
1001 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1002 }
Jim Grosbacha95ec992011-10-11 17:29:55 +00001003 bool isAlignedMemory() const {
1004 return isMemNoOffset(true);
Bruno Cardoso Lopesab830502011-03-31 23:26:08 +00001005 }
Jim Grosbachd3595712011-08-03 23:50:40 +00001006 bool isAddrMode2() const {
Chad Rosier41099832012-09-11 23:02:35 +00001007 if (!isMem() || Memory.Alignment != 0) return false;
Jim Grosbachd3595712011-08-03 23:50:40 +00001008 // Check for register offset.
Jim Grosbach871dff72011-10-11 15:59:20 +00001009 if (Memory.OffsetRegNum) return true;
Jim Grosbachd3595712011-08-03 23:50:40 +00001010 // Immediate offset in range [-4095, 4095].
Jim Grosbach871dff72011-10-11 15:59:20 +00001011 if (!Memory.OffsetImm) return true;
1012 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbachd3595712011-08-03 23:50:40 +00001013 return Val > -4096 && Val < 4096;
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +00001014 }
Jim Grosbachcd17c122011-08-04 23:01:30 +00001015 bool isAM2OffsetImm() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001016 if (!isImm()) return false;
Jim Grosbachcd17c122011-08-04 23:01:30 +00001017 // Immediate offset in range [-4095, 4095].
1018 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1019 if (!CE) return false;
1020 int64_t Val = CE->getValue();
Mihai Popac1d119e2013-06-11 09:48:35 +00001021 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
Jim Grosbachcd17c122011-08-04 23:01:30 +00001022 }
Jim Grosbach5b96b802011-08-10 20:29:19 +00001023 bool isAddrMode3() const {
Jim Grosbach8648c102011-12-19 23:06:24 +00001024 // If we have an immediate that's not a constant, treat it as a label
1025 // reference needing a fixup. If it is a constant, it's something else
1026 // and we reject it.
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001027 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbach8648c102011-12-19 23:06:24 +00001028 return true;
Chad Rosier41099832012-09-11 23:02:35 +00001029 if (!isMem() || Memory.Alignment != 0) return false;
Jim Grosbach5b96b802011-08-10 20:29:19 +00001030 // No shifts are legal for AM3.
Jim Grosbach871dff72011-10-11 15:59:20 +00001031 if (Memory.ShiftType != ARM_AM::no_shift) return false;
Jim Grosbach5b96b802011-08-10 20:29:19 +00001032 // Check for register offset.
Jim Grosbach871dff72011-10-11 15:59:20 +00001033 if (Memory.OffsetRegNum) return true;
Jim Grosbach5b96b802011-08-10 20:29:19 +00001034 // Immediate offset in range [-255, 255].
Jim Grosbach871dff72011-10-11 15:59:20 +00001035 if (!Memory.OffsetImm) return true;
1036 int64_t Val = Memory.OffsetImm->getValue();
Silviu Baranga5a719f92012-05-11 09:10:54 +00001037 // The #-0 offset is encoded as INT32_MIN, and we have to check
1038 // for this too.
1039 return (Val > -256 && Val < 256) || Val == INT32_MIN;
Jim Grosbach5b96b802011-08-10 20:29:19 +00001040 }
1041 bool isAM3Offset() const {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00001042 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
Jim Grosbach5b96b802011-08-10 20:29:19 +00001043 return false;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00001044 if (Kind == k_PostIndexRegister)
Jim Grosbach5b96b802011-08-10 20:29:19 +00001045 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1046 // Immediate offset in range [-255, 255].
1047 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048 if (!CE) return false;
1049 int64_t Val = CE->getValue();
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00001050 // Special case, #-0 is INT32_MIN.
1051 return (Val > -256 && Val < 256) || Val == INT32_MIN;
Jim Grosbach5b96b802011-08-10 20:29:19 +00001052 }
Jim Grosbachd3595712011-08-03 23:50:40 +00001053 bool isAddrMode5() const {
Jim Grosbachfb2f1d62011-11-01 01:24:45 +00001054 // If we have an immediate that's not a constant, treat it as a label
1055 // reference needing a fixup. If it is a constant, it's something else
1056 // and we reject it.
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001057 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbachfb2f1d62011-11-01 01:24:45 +00001058 return true;
Chad Rosier41099832012-09-11 23:02:35 +00001059 if (!isMem() || Memory.Alignment != 0) return false;
Jim Grosbachd3595712011-08-03 23:50:40 +00001060 // Check for register offset.
Jim Grosbach871dff72011-10-11 15:59:20 +00001061 if (Memory.OffsetRegNum) return false;
Jim Grosbachd3595712011-08-03 23:50:40 +00001062 // Immediate offset in range [-1020, 1020] and a multiple of 4.
Jim Grosbach871dff72011-10-11 15:59:20 +00001063 if (!Memory.OffsetImm) return true;
1064 int64_t Val = Memory.OffsetImm->getValue();
Owen Anderson967674d2011-08-29 19:36:44 +00001065 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
Jim Grosbachfb2f1d62011-11-01 01:24:45 +00001066 Val == INT32_MIN;
Bill Wendling8d2aa032010-11-08 23:49:57 +00001067 }
Jim Grosbach05541f42011-09-19 22:21:13 +00001068 bool isMemTBB() const {
Chad Rosier41099832012-09-11 23:02:35 +00001069 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001070 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
Jim Grosbach05541f42011-09-19 22:21:13 +00001071 return false;
1072 return true;
1073 }
1074 bool isMemTBH() const {
Chad Rosier41099832012-09-11 23:02:35 +00001075 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001076 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1077 Memory.Alignment != 0 )
Jim Grosbach05541f42011-09-19 22:21:13 +00001078 return false;
1079 return true;
1080 }
Jim Grosbachd3595712011-08-03 23:50:40 +00001081 bool isMemRegOffset() const {
Chad Rosier41099832012-09-11 23:02:35 +00001082 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
Bill Wendling092a7bd2010-12-14 03:36:38 +00001083 return false;
Daniel Dunbar7ed45592011-01-18 05:34:11 +00001084 return true;
Bill Wendling092a7bd2010-12-14 03:36:38 +00001085 }
Jim Grosbache0ebc1c2011-09-07 23:10:15 +00001086 bool isT2MemRegOffset() const {
Chad Rosier41099832012-09-11 23:02:35 +00001087 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001088 Memory.Alignment != 0)
Jim Grosbache0ebc1c2011-09-07 23:10:15 +00001089 return false;
1090 // Only lsl #{0, 1, 2, 3} allowed.
Jim Grosbach871dff72011-10-11 15:59:20 +00001091 if (Memory.ShiftType == ARM_AM::no_shift)
Jim Grosbache0ebc1c2011-09-07 23:10:15 +00001092 return true;
Jim Grosbach871dff72011-10-11 15:59:20 +00001093 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
Jim Grosbache0ebc1c2011-09-07 23:10:15 +00001094 return false;
1095 return true;
1096 }
Jim Grosbachd3595712011-08-03 23:50:40 +00001097 bool isMemThumbRR() const {
1098 // Thumb reg+reg addressing is simple. Just two registers, a base and
1099 // an offset. No shifts, negations or any other complicating factors.
Chad Rosier41099832012-09-11 23:02:35 +00001100 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001101 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
Bill Wendling811c9362010-11-30 07:44:32 +00001102 return false;
Jim Grosbach871dff72011-10-11 15:59:20 +00001103 return isARMLowRegister(Memory.BaseRegNum) &&
1104 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
Jim Grosbach3fe94e32011-08-19 17:55:24 +00001105 }
1106 bool isMemThumbRIs4() const {
Chad Rosier41099832012-09-11 23:02:35 +00001107 if (!isMem() || Memory.OffsetRegNum != 0 ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001108 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
Jim Grosbach3fe94e32011-08-19 17:55:24 +00001109 return false;
1110 // Immediate offset, multiple of 4 in range [0, 124].
Jim Grosbach871dff72011-10-11 15:59:20 +00001111 if (!Memory.OffsetImm) return true;
1112 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach23983d62011-08-19 18:13:48 +00001113 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1114 }
Jim Grosbach26d35872011-08-19 18:55:51 +00001115 bool isMemThumbRIs2() const {
Chad Rosier41099832012-09-11 23:02:35 +00001116 if (!isMem() || Memory.OffsetRegNum != 0 ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001117 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
Jim Grosbach26d35872011-08-19 18:55:51 +00001118 return false;
1119 // Immediate offset, multiple of 4 in range [0, 62].
Jim Grosbach871dff72011-10-11 15:59:20 +00001120 if (!Memory.OffsetImm) return true;
1121 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach26d35872011-08-19 18:55:51 +00001122 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1123 }
Jim Grosbacha32c7532011-08-19 18:49:59 +00001124 bool isMemThumbRIs1() const {
Chad Rosier41099832012-09-11 23:02:35 +00001125 if (!isMem() || Memory.OffsetRegNum != 0 ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001126 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
Jim Grosbacha32c7532011-08-19 18:49:59 +00001127 return false;
1128 // Immediate offset in range [0, 31].
Jim Grosbach871dff72011-10-11 15:59:20 +00001129 if (!Memory.OffsetImm) return true;
1130 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbacha32c7532011-08-19 18:49:59 +00001131 return Val >= 0 && Val <= 31;
1132 }
Jim Grosbach23983d62011-08-19 18:13:48 +00001133 bool isMemThumbSPI() const {
Chad Rosier41099832012-09-11 23:02:35 +00001134 if (!isMem() || Memory.OffsetRegNum != 0 ||
Jim Grosbacha95ec992011-10-11 17:29:55 +00001135 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
Jim Grosbach23983d62011-08-19 18:13:48 +00001136 return false;
1137 // Immediate offset, multiple of 4 in range [0, 1020].
Jim Grosbach871dff72011-10-11 15:59:20 +00001138 if (!Memory.OffsetImm) return true;
1139 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach23983d62011-08-19 18:13:48 +00001140 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
Bill Wendling811c9362010-11-30 07:44:32 +00001141 }
Jim Grosbach7db8d692011-09-08 22:07:06 +00001142 bool isMemImm8s4Offset() const {
Jim Grosbach8648c102011-12-19 23:06:24 +00001143 // If we have an immediate that's not a constant, treat it as a label
1144 // reference needing a fixup. If it is a constant, it's something else
1145 // and we reject it.
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001146 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbach8648c102011-12-19 23:06:24 +00001147 return true;
Chad Rosier41099832012-09-11 23:02:35 +00001148 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbach7db8d692011-09-08 22:07:06 +00001149 return false;
1150 // Immediate offset a multiple of 4 in range [-1020, 1020].
Jim Grosbach871dff72011-10-11 15:59:20 +00001151 if (!Memory.OffsetImm) return true;
1152 int64_t Val = Memory.OffsetImm->getValue();
Jiangning Liu6a43bf72012-08-02 08:29:50 +00001153 // Special case, #-0 is INT32_MIN.
1154 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
Jim Grosbach7db8d692011-09-08 22:07:06 +00001155 }
Jim Grosbacha05627e2011-09-09 18:37:27 +00001156 bool isMemImm0_1020s4Offset() const {
Chad Rosier41099832012-09-11 23:02:35 +00001157 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbacha05627e2011-09-09 18:37:27 +00001158 return false;
1159 // Immediate offset a multiple of 4 in range [0, 1020].
Jim Grosbach871dff72011-10-11 15:59:20 +00001160 if (!Memory.OffsetImm) return true;
1161 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbacha05627e2011-09-09 18:37:27 +00001162 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1163 }
Jim Grosbachd3595712011-08-03 23:50:40 +00001164 bool isMemImm8Offset() const {
Chad Rosier41099832012-09-11 23:02:35 +00001165 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbachd3595712011-08-03 23:50:40 +00001166 return false;
Jim Grosbach94298a92012-01-18 22:46:46 +00001167 // Base reg of PC isn't allowed for these encodings.
1168 if (Memory.BaseRegNum == ARM::PC) return false;
Jim Grosbachd3595712011-08-03 23:50:40 +00001169 // Immediate offset in range [-255, 255].
Jim Grosbach871dff72011-10-11 15:59:20 +00001170 if (!Memory.OffsetImm) return true;
1171 int64_t Val = Memory.OffsetImm->getValue();
Owen Anderson49168402011-09-23 22:25:02 +00001172 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
Jim Grosbachd3595712011-08-03 23:50:40 +00001173 }
Jim Grosbach2392c532011-09-07 23:39:14 +00001174 bool isMemPosImm8Offset() const {
Chad Rosier41099832012-09-11 23:02:35 +00001175 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbach2392c532011-09-07 23:39:14 +00001176 return false;
1177 // Immediate offset in range [0, 255].
Jim Grosbach871dff72011-10-11 15:59:20 +00001178 if (!Memory.OffsetImm) return true;
1179 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach2392c532011-09-07 23:39:14 +00001180 return Val >= 0 && Val < 256;
1181 }
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001182 bool isMemNegImm8Offset() const {
Chad Rosier41099832012-09-11 23:02:35 +00001183 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001184 return false;
Jim Grosbach94298a92012-01-18 22:46:46 +00001185 // Base reg of PC isn't allowed for these encodings.
1186 if (Memory.BaseRegNum == ARM::PC) return false;
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001187 // Immediate offset in range [-255, -1].
Jim Grosbach175c7d02011-12-06 04:49:29 +00001188 if (!Memory.OffsetImm) return false;
Jim Grosbach871dff72011-10-11 15:59:20 +00001189 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach175c7d02011-12-06 04:49:29 +00001190 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001191 }
1192 bool isMemUImm12Offset() const {
Chad Rosier41099832012-09-11 23:02:35 +00001193 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001194 return false;
1195 // Immediate offset in range [0, 4095].
Jim Grosbach871dff72011-10-11 15:59:20 +00001196 if (!Memory.OffsetImm) return true;
1197 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001198 return (Val >= 0 && Val < 4096);
1199 }
Jim Grosbachd3595712011-08-03 23:50:40 +00001200 bool isMemImm12Offset() const {
Jim Grosbach95466ce2011-08-08 20:59:31 +00001201 // If we have an immediate that's not a constant, treat it as a label
1202 // reference needing a fixup. If it is a constant, it's something else
1203 // and we reject it.
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001204 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbach95466ce2011-08-08 20:59:31 +00001205 return true;
1206
Chad Rosier41099832012-09-11 23:02:35 +00001207 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbachd3595712011-08-03 23:50:40 +00001208 return false;
1209 // Immediate offset in range [-4095, 4095].
Jim Grosbach871dff72011-10-11 15:59:20 +00001210 if (!Memory.OffsetImm) return true;
1211 int64_t Val = Memory.OffsetImm->getValue();
Owen Anderson967674d2011-08-29 19:36:44 +00001212 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
Jim Grosbachd3595712011-08-03 23:50:40 +00001213 }
1214 bool isPostIdxImm8() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001215 if (!isImm()) return false;
Jim Grosbachd3595712011-08-03 23:50:40 +00001216 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1217 if (!CE) return false;
1218 int64_t Val = CE->getValue();
Owen Andersonf02d98d2011-08-29 17:17:09 +00001219 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
Jim Grosbachd3595712011-08-03 23:50:40 +00001220 }
Jim Grosbach93981412011-10-11 21:55:36 +00001221 bool isPostIdxImm8s4() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001222 if (!isImm()) return false;
Jim Grosbach93981412011-10-11 21:55:36 +00001223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224 if (!CE) return false;
1225 int64_t Val = CE->getValue();
1226 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1227 (Val == INT32_MIN);
1228 }
Jim Grosbachd3595712011-08-03 23:50:40 +00001229
Jim Grosbach6e5778f2011-10-07 23:24:09 +00001230 bool isMSRMask() const { return Kind == k_MSRMask; }
1231 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00001232
Jim Grosbach741cd732011-10-17 22:26:03 +00001233 // NEON operands.
Jim Grosbach2f50e922011-12-15 21:44:33 +00001234 bool isSingleSpacedVectorList() const {
1235 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1236 }
1237 bool isDoubleSpacedVectorList() const {
1238 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1239 }
Jim Grosbachad47cfc2011-10-18 23:02:30 +00001240 bool isVecListOneD() const {
Jim Grosbach2f50e922011-12-15 21:44:33 +00001241 if (!isSingleSpacedVectorList()) return false;
Jim Grosbachad47cfc2011-10-18 23:02:30 +00001242 return VectorList.Count == 1;
1243 }
1244
Jim Grosbachc988e0c2012-03-05 19:33:30 +00001245 bool isVecListDPair() const {
1246 if (!isSingleSpacedVectorList()) return false;
1247 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1248 .contains(VectorList.RegNum));
1249 }
1250
Jim Grosbachc4360fe2011-10-21 20:02:19 +00001251 bool isVecListThreeD() const {
Jim Grosbach2f50e922011-12-15 21:44:33 +00001252 if (!isSingleSpacedVectorList()) return false;
Jim Grosbachc4360fe2011-10-21 20:02:19 +00001253 return VectorList.Count == 3;
1254 }
1255
Jim Grosbach846bcff2011-10-21 20:35:01 +00001256 bool isVecListFourD() const {
Jim Grosbach2f50e922011-12-15 21:44:33 +00001257 if (!isSingleSpacedVectorList()) return false;
Jim Grosbach846bcff2011-10-21 20:35:01 +00001258 return VectorList.Count == 4;
1259 }
1260
Jim Grosbache5307f92012-03-05 21:43:40 +00001261 bool isVecListDPairSpaced() const {
Kevin Enderby816ca272012-03-20 17:41:51 +00001262 if (isSingleSpacedVectorList()) return false;
Jim Grosbache5307f92012-03-05 21:43:40 +00001263 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1264 .contains(VectorList.RegNum));
1265 }
1266
Jim Grosbachac2af3f2012-01-23 23:20:46 +00001267 bool isVecListThreeQ() const {
1268 if (!isDoubleSpacedVectorList()) return false;
1269 return VectorList.Count == 3;
1270 }
1271
Jim Grosbach1e946a42012-01-24 00:43:12 +00001272 bool isVecListFourQ() const {
1273 if (!isDoubleSpacedVectorList()) return false;
1274 return VectorList.Count == 4;
1275 }
1276
Jim Grosbachc5af54e2011-12-21 00:38:54 +00001277 bool isSingleSpacedVectorAllLanes() const {
1278 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1279 }
1280 bool isDoubleSpacedVectorAllLanes() const {
1281 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1282 }
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00001283 bool isVecListOneDAllLanes() const {
Jim Grosbachc5af54e2011-12-21 00:38:54 +00001284 if (!isSingleSpacedVectorAllLanes()) return false;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00001285 return VectorList.Count == 1;
1286 }
1287
Jim Grosbach13a292c2012-03-06 22:01:44 +00001288 bool isVecListDPairAllLanes() const {
Jim Grosbachc5af54e2011-12-21 00:38:54 +00001289 if (!isSingleSpacedVectorAllLanes()) return false;
Jim Grosbach13a292c2012-03-06 22:01:44 +00001290 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1291 .contains(VectorList.RegNum));
Jim Grosbachc5af54e2011-12-21 00:38:54 +00001292 }
1293
Jim Grosbached428bc2012-03-06 23:10:38 +00001294 bool isVecListDPairSpacedAllLanes() const {
Jim Grosbachc5af54e2011-12-21 00:38:54 +00001295 if (!isDoubleSpacedVectorAllLanes()) return false;
Jim Grosbach3ecf9762011-11-30 18:21:25 +00001296 return VectorList.Count == 2;
1297 }
1298
Jim Grosbachb78403c2012-01-24 23:47:04 +00001299 bool isVecListThreeDAllLanes() const {
1300 if (!isSingleSpacedVectorAllLanes()) return false;
1301 return VectorList.Count == 3;
1302 }
1303
1304 bool isVecListThreeQAllLanes() const {
1305 if (!isDoubleSpacedVectorAllLanes()) return false;
1306 return VectorList.Count == 3;
1307 }
1308
Jim Grosbach086cbfa2012-01-25 00:01:08 +00001309 bool isVecListFourDAllLanes() const {
1310 if (!isSingleSpacedVectorAllLanes()) return false;
1311 return VectorList.Count == 4;
1312 }
1313
1314 bool isVecListFourQAllLanes() const {
1315 if (!isDoubleSpacedVectorAllLanes()) return false;
1316 return VectorList.Count == 4;
1317 }
1318
Jim Grosbach75e2ab52011-12-20 19:21:26 +00001319 bool isSingleSpacedVectorIndexed() const {
1320 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1321 }
1322 bool isDoubleSpacedVectorIndexed() const {
1323 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1324 }
Jim Grosbach04945c42011-12-02 00:35:16 +00001325 bool isVecListOneDByteIndexed() const {
Jim Grosbach75e2ab52011-12-20 19:21:26 +00001326 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbach04945c42011-12-02 00:35:16 +00001327 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1328 }
1329
Jim Grosbachda511042011-12-14 23:35:06 +00001330 bool isVecListOneDHWordIndexed() const {
Jim Grosbach75e2ab52011-12-20 19:21:26 +00001331 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbachda511042011-12-14 23:35:06 +00001332 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1333 }
1334
1335 bool isVecListOneDWordIndexed() const {
Jim Grosbach75e2ab52011-12-20 19:21:26 +00001336 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbachda511042011-12-14 23:35:06 +00001337 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1338 }
1339
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00001340 bool isVecListTwoDByteIndexed() const {
Jim Grosbach75e2ab52011-12-20 19:21:26 +00001341 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00001342 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1343 }
1344
Jim Grosbachda511042011-12-14 23:35:06 +00001345 bool isVecListTwoDHWordIndexed() const {
Jim Grosbach75e2ab52011-12-20 19:21:26 +00001346 if (!isSingleSpacedVectorIndexed()) return false;
1347 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1348 }
1349
1350 bool isVecListTwoQWordIndexed() const {
1351 if (!isDoubleSpacedVectorIndexed()) return false;
1352 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1353 }
1354
1355 bool isVecListTwoQHWordIndexed() const {
1356 if (!isDoubleSpacedVectorIndexed()) return false;
Jim Grosbachda511042011-12-14 23:35:06 +00001357 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1358 }
1359
1360 bool isVecListTwoDWordIndexed() const {
Jim Grosbach75e2ab52011-12-20 19:21:26 +00001361 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbachda511042011-12-14 23:35:06 +00001362 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1363 }
1364
Jim Grosbacha8b444b2012-01-23 21:53:26 +00001365 bool isVecListThreeDByteIndexed() const {
1366 if (!isSingleSpacedVectorIndexed()) return false;
1367 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1368 }
1369
1370 bool isVecListThreeDHWordIndexed() const {
1371 if (!isSingleSpacedVectorIndexed()) return false;
1372 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1373 }
1374
1375 bool isVecListThreeQWordIndexed() const {
1376 if (!isDoubleSpacedVectorIndexed()) return false;
1377 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1378 }
1379
1380 bool isVecListThreeQHWordIndexed() const {
1381 if (!isDoubleSpacedVectorIndexed()) return false;
1382 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1383 }
1384
1385 bool isVecListThreeDWordIndexed() const {
1386 if (!isSingleSpacedVectorIndexed()) return false;
1387 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1388 }
1389
Jim Grosbach14952a02012-01-24 18:37:25 +00001390 bool isVecListFourDByteIndexed() const {
1391 if (!isSingleSpacedVectorIndexed()) return false;
1392 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1393 }
1394
1395 bool isVecListFourDHWordIndexed() const {
1396 if (!isSingleSpacedVectorIndexed()) return false;
1397 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1398 }
1399
1400 bool isVecListFourQWordIndexed() const {
1401 if (!isDoubleSpacedVectorIndexed()) return false;
1402 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1403 }
1404
1405 bool isVecListFourQHWordIndexed() const {
1406 if (!isDoubleSpacedVectorIndexed()) return false;
1407 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1408 }
1409
1410 bool isVecListFourDWordIndexed() const {
1411 if (!isSingleSpacedVectorIndexed()) return false;
1412 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1413 }
1414
Jim Grosbachd0637bf2011-10-07 23:56:00 +00001415 bool isVectorIndex8() const {
1416 if (Kind != k_VectorIndex) return false;
1417 return VectorIndex.Val < 8;
1418 }
1419 bool isVectorIndex16() const {
1420 if (Kind != k_VectorIndex) return false;
1421 return VectorIndex.Val < 4;
1422 }
1423 bool isVectorIndex32() const {
1424 if (Kind != k_VectorIndex) return false;
1425 return VectorIndex.Val < 2;
1426 }
1427
Jim Grosbach741cd732011-10-17 22:26:03 +00001428 bool isNEONi8splat() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001429 if (!isImm()) return false;
Jim Grosbach741cd732011-10-17 22:26:03 +00001430 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1431 // Must be a constant.
1432 if (!CE) return false;
1433 int64_t Value = CE->getValue();
1434 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1435 // value.
Jim Grosbach741cd732011-10-17 22:26:03 +00001436 return Value >= 0 && Value < 256;
1437 }
Jim Grosbachd0637bf2011-10-07 23:56:00 +00001438
Jim Grosbachcda32ae2011-10-17 23:09:09 +00001439 bool isNEONi16splat() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001440 if (!isImm()) return false;
Jim Grosbachcda32ae2011-10-17 23:09:09 +00001441 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1442 // Must be a constant.
1443 if (!CE) return false;
1444 int64_t Value = CE->getValue();
1445 // i16 value in the range [0,255] or [0x0100, 0xff00]
1446 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1447 }
1448
Jim Grosbach8211c052011-10-18 00:22:00 +00001449 bool isNEONi32splat() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001450 if (!isImm()) return false;
Jim Grosbach8211c052011-10-18 00:22:00 +00001451 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1452 // Must be a constant.
1453 if (!CE) return false;
1454 int64_t Value = CE->getValue();
1455 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1456 return (Value >= 0 && Value < 256) ||
1457 (Value >= 0x0100 && Value <= 0xff00) ||
1458 (Value >= 0x010000 && Value <= 0xff0000) ||
1459 (Value >= 0x01000000 && Value <= 0xff000000);
1460 }
1461
1462 bool isNEONi32vmov() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001463 if (!isImm()) return false;
Jim Grosbach8211c052011-10-18 00:22:00 +00001464 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1465 // Must be a constant.
1466 if (!CE) return false;
1467 int64_t Value = CE->getValue();
1468 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1469 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1470 return (Value >= 0 && Value < 256) ||
1471 (Value >= 0x0100 && Value <= 0xff00) ||
1472 (Value >= 0x010000 && Value <= 0xff0000) ||
1473 (Value >= 0x01000000 && Value <= 0xff000000) ||
1474 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1475 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1476 }
Jim Grosbach045b6c72011-12-19 23:51:07 +00001477 bool isNEONi32vmovNeg() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001478 if (!isImm()) return false;
Jim Grosbach045b6c72011-12-19 23:51:07 +00001479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1480 // Must be a constant.
1481 if (!CE) return false;
1482 int64_t Value = ~CE->getValue();
1483 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1484 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1485 return (Value >= 0 && Value < 256) ||
1486 (Value >= 0x0100 && Value <= 0xff00) ||
1487 (Value >= 0x010000 && Value <= 0xff0000) ||
1488 (Value >= 0x01000000 && Value <= 0xff000000) ||
1489 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1490 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1491 }
Jim Grosbach8211c052011-10-18 00:22:00 +00001492
Jim Grosbache4454e02011-10-18 16:18:11 +00001493 bool isNEONi64splat() const {
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001494 if (!isImm()) return false;
Jim Grosbache4454e02011-10-18 16:18:11 +00001495 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1496 // Must be a constant.
1497 if (!CE) return false;
1498 uint64_t Value = CE->getValue();
1499 // i64 value with each byte being either 0 or 0xff.
1500 for (unsigned i = 0; i < 8; ++i)
1501 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1502 return true;
1503 }
1504
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00001505 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
Chris Lattner5d6f6a02010-10-29 00:27:31 +00001506 // Add as immediates when possible. Null MCExpr = 0.
1507 if (Expr == 0)
1508 Inst.addOperand(MCOperand::CreateImm(0));
1509 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00001510 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1511 else
1512 Inst.addOperand(MCOperand::CreateExpr(Expr));
1513 }
1514
Daniel Dunbard8042b72010-08-11 06:36:53 +00001515 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
Daniel Dunbar188b47b2010-08-11 06:37:20 +00001516 assert(N == 2 && "Invalid number of operands!");
Daniel Dunbard8042b72010-08-11 06:36:53 +00001517 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
Jim Grosbach968c9272010-12-06 18:30:57 +00001518 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1519 Inst.addOperand(MCOperand::CreateReg(RegNum));
Daniel Dunbard8042b72010-08-11 06:36:53 +00001520 }
1521
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00001522 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1523 assert(N == 1 && "Invalid number of operands!");
1524 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1525 }
1526
Jim Grosbach48399582011-10-12 17:34:41 +00001527 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1528 assert(N == 1 && "Invalid number of operands!");
1529 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1530 }
1531
1532 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1533 assert(N == 1 && "Invalid number of operands!");
1534 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1535 }
1536
Jim Grosbach3d1eac82011-08-26 21:43:41 +00001537 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1538 assert(N == 1 && "Invalid number of operands!");
1539 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1540 }
1541
1542 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1543 assert(N == 1 && "Invalid number of operands!");
1544 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1545 }
1546
Jim Grosbach0bfb4d52010-12-06 18:21:12 +00001547 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1548 assert(N == 1 && "Invalid number of operands!");
1549 Inst.addOperand(MCOperand::CreateReg(getReg()));
1550 }
1551
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00001552 void addRegOperands(MCInst &Inst, unsigned N) const {
1553 assert(N == 1 && "Invalid number of operands!");
1554 Inst.addOperand(MCOperand::CreateReg(getReg()));
1555 }
1556
Jim Grosbachac798e12011-07-25 20:49:51 +00001557 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
Jim Grosbach7dcd1352011-07-13 17:50:29 +00001558 assert(N == 3 && "Invalid number of operands!");
Jim Grosbachee201fa2011-11-14 17:52:47 +00001559 assert(isRegShiftedReg() &&
1560 "addRegShiftedRegOperands() on non RegShiftedReg!");
Jim Grosbachac798e12011-07-25 20:49:51 +00001561 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1562 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
Jim Grosbach7dcd1352011-07-13 17:50:29 +00001563 Inst.addOperand(MCOperand::CreateImm(
Jim Grosbachac798e12011-07-25 20:49:51 +00001564 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
Jim Grosbach7dcd1352011-07-13 17:50:29 +00001565 }
1566
Jim Grosbachac798e12011-07-25 20:49:51 +00001567 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
Owen Anderson04912702011-07-21 23:38:37 +00001568 assert(N == 2 && "Invalid number of operands!");
Jim Grosbachee201fa2011-11-14 17:52:47 +00001569 assert(isRegShiftedImm() &&
1570 "addRegShiftedImmOperands() on non RegShiftedImm!");
Jim Grosbachac798e12011-07-25 20:49:51 +00001571 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
Richard Bartonba5b0cc2012-04-25 18:00:18 +00001572 // Shift of #32 is encoded as 0 where permitted
1573 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
Owen Andersonb595ed02011-07-21 18:54:16 +00001574 Inst.addOperand(MCOperand::CreateImm(
Richard Bartonba5b0cc2012-04-25 18:00:18 +00001575 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
Owen Andersonb595ed02011-07-21 18:54:16 +00001576 }
1577
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00001578 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00001579 assert(N == 1 && "Invalid number of operands!");
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00001580 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1581 ShifterImm.Imm));
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00001582 }
1583
Bill Wendling8d2aa032010-11-08 23:49:57 +00001584 void addRegListOperands(MCInst &Inst, unsigned N) const {
Bill Wendling2cae3272010-11-09 22:44:22 +00001585 assert(N == 1 && "Invalid number of operands!");
Bill Wendlingbed94652010-11-09 23:28:44 +00001586 const SmallVectorImpl<unsigned> &RegList = getRegList();
1587 for (SmallVectorImpl<unsigned>::const_iterator
Bill Wendling2cae3272010-11-09 22:44:22 +00001588 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1589 Inst.addOperand(MCOperand::CreateReg(*I));
Bill Wendling8d2aa032010-11-08 23:49:57 +00001590 }
1591
Bill Wendling9898ac92010-11-17 04:32:08 +00001592 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1593 addRegListOperands(Inst, N);
1594 }
1595
1596 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1597 addRegListOperands(Inst, N);
1598 }
1599
Jim Grosbach833b9d32011-07-27 20:15:40 +00001600 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1601 assert(N == 1 && "Invalid number of operands!");
1602 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1603 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1604 }
1605
Jim Grosbach864b6092011-07-28 21:34:26 +00001606 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1607 assert(N == 1 && "Invalid number of operands!");
1608 // Munge the lsb/width into a bitfield mask.
1609 unsigned lsb = Bitfield.LSB;
1610 unsigned width = Bitfield.Width;
1611 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1612 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1613 (32 - (lsb + width)));
1614 Inst.addOperand(MCOperand::CreateImm(Mask));
1615 }
1616
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00001617 void addImmOperands(MCInst &Inst, unsigned N) const {
1618 assert(N == 1 && "Invalid number of operands!");
1619 addExpr(Inst, getImm());
1620 }
Jim Grosbach624bcc72010-10-29 14:46:02 +00001621
Jim Grosbachea231912011-12-22 22:19:05 +00001622 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1623 assert(N == 1 && "Invalid number of operands!");
1624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1626 }
1627
1628 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1629 assert(N == 1 && "Invalid number of operands!");
1630 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1631 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1632 }
1633
Jim Grosbache7fbce72011-10-03 23:38:36 +00001634 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1635 assert(N == 1 && "Invalid number of operands!");
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00001636 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1637 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1638 Inst.addOperand(MCOperand::CreateImm(Val));
Jim Grosbache7fbce72011-10-03 23:38:36 +00001639 }
1640
Jim Grosbach7db8d692011-09-08 22:07:06 +00001641 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1642 assert(N == 1 && "Invalid number of operands!");
1643 // FIXME: We really want to scale the value here, but the LDRD/STRD
1644 // instruction don't encode operands that way yet.
1645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1646 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1647 }
1648
Jim Grosbach0a0b3072011-08-24 21:22:15 +00001649 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1650 assert(N == 1 && "Invalid number of operands!");
1651 // The immediate is scaled by four in the encoding and is stored
1652 // in the MCInst as such. Lop off the low two bits here.
1653 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1654 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1655 }
1656
Jim Grosbach930f2f62012-04-05 20:57:13 +00001657 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1658 assert(N == 1 && "Invalid number of operands!");
1659 // The immediate is scaled by four in the encoding and is stored
1660 // in the MCInst as such. Lop off the low two bits here.
1661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1662 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1663 }
1664
Jim Grosbach0a0b3072011-08-24 21:22:15 +00001665 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1666 assert(N == 1 && "Invalid number of operands!");
1667 // The immediate is scaled by four in the encoding and is stored
1668 // in the MCInst as such. Lop off the low two bits here.
1669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1670 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1671 }
1672
Jim Grosbach475c6db2011-07-25 23:09:14 +00001673 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1674 assert(N == 1 && "Invalid number of operands!");
1675 // The constant encodes as the immediate-1, and we store in the instruction
1676 // the bits as encoded, so subtract off one here.
1677 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1678 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1679 }
1680
Jim Grosbach801e0a32011-07-22 23:16:18 +00001681 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1682 assert(N == 1 && "Invalid number of operands!");
1683 // The constant encodes as the immediate-1, and we store in the instruction
1684 // the bits as encoded, so subtract off one here.
1685 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1686 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1687 }
1688
Jim Grosbach46dd4132011-08-17 21:51:27 +00001689 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1690 assert(N == 1 && "Invalid number of operands!");
1691 // The constant encodes as the immediate, except for 32, which encodes as
1692 // zero.
1693 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1694 unsigned Imm = CE->getValue();
1695 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1696 }
1697
Jim Grosbach27c1e252011-07-21 17:23:04 +00001698 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1699 assert(N == 1 && "Invalid number of operands!");
1700 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1701 // the instruction as well.
1702 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1703 int Val = CE->getValue();
1704 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1705 }
1706
Jim Grosbachb009a872011-10-28 22:36:30 +00001707 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1708 assert(N == 1 && "Invalid number of operands!");
1709 // The operand is actually a t2_so_imm, but we have its bitwise
1710 // negation in the assembly source, so twiddle it here.
1711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1712 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1713 }
1714
Jim Grosbach30506252011-12-08 00:31:07 +00001715 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1716 assert(N == 1 && "Invalid number of operands!");
1717 // The operand is actually a t2_so_imm, but we have its
1718 // negation in the assembly source, so twiddle it here.
1719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1720 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1721 }
1722
Jim Grosbach930f2f62012-04-05 20:57:13 +00001723 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1724 assert(N == 1 && "Invalid number of operands!");
1725 // The operand is actually an imm0_4095, but we have its
1726 // negation in the assembly source, so twiddle it here.
1727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1728 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1729 }
1730
Mihai Popad36cbaa2013-07-03 09:21:44 +00001731 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1732 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1733 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1734 return;
1735 }
1736
1737 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1738 assert(SR && "Unknown value type!");
1739 Inst.addOperand(MCOperand::CreateExpr(SR));
1740 }
1741
Mihai Popa8a9da5b2013-07-22 15:49:36 +00001742 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1743 assert(N == 1 && "Invalid number of operands!");
1744 if (isImm()) {
1745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1746 if (CE) {
1747 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1748 return;
1749 }
1750
1751 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1752 assert(SR && "Unknown value type!");
1753 Inst.addOperand(MCOperand::CreateExpr(SR));
1754 return;
1755 }
1756
1757 assert(isMem() && "Unknown value type!");
1758 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1759 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1760 }
1761
Jim Grosbach3d785ed2011-10-28 22:50:54 +00001762 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1763 assert(N == 1 && "Invalid number of operands!");
1764 // The operand is actually a so_imm, but we have its bitwise
1765 // negation in the assembly source, so twiddle it here.
1766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1767 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1768 }
1769
Jim Grosbach30506252011-12-08 00:31:07 +00001770 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1771 assert(N == 1 && "Invalid number of operands!");
1772 // The operand is actually a so_imm, but we have its
1773 // negation in the assembly source, so twiddle it here.
1774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1775 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1776 }
1777
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00001778 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1779 assert(N == 1 && "Invalid number of operands!");
1780 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1781 }
1782
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00001783 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1784 assert(N == 1 && "Invalid number of operands!");
1785 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1786 }
1787
Jim Grosbachd3595712011-08-03 23:50:40 +00001788 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1789 assert(N == 1 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00001790 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Bruno Cardoso Lopesf170f8b2011-03-24 21:04:58 +00001791 }
1792
Jim Grosbach94298a92012-01-18 22:46:46 +00001793 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1794 assert(N == 1 && "Invalid number of operands!");
1795 int32_t Imm = Memory.OffsetImm->getValue();
1796 // FIXME: Handle #-0
1797 if (Imm == INT32_MIN) Imm = 0;
1798 Inst.addOperand(MCOperand::CreateImm(Imm));
1799 }
1800
Jiangning Liu10dd40e2012-08-02 08:13:13 +00001801 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1802 assert(N == 1 && "Invalid number of operands!");
1803 assert(isImm() && "Not an immediate!");
1804
1805 // If we have an immediate that's not a constant, treat it as a label
1806 // reference needing a fixup.
1807 if (!isa<MCConstantExpr>(getImm())) {
1808 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1809 return;
1810 }
1811
1812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1813 int Val = CE->getValue();
1814 Inst.addOperand(MCOperand::CreateImm(Val));
1815 }
1816
Jim Grosbacha95ec992011-10-11 17:29:55 +00001817 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1818 assert(N == 2 && "Invalid number of operands!");
1819 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1820 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1821 }
1822
Jim Grosbachd3595712011-08-03 23:50:40 +00001823 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1824 assert(N == 3 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00001825 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1826 if (!Memory.OffsetRegNum) {
Jim Grosbachd3595712011-08-03 23:50:40 +00001827 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1828 // Special case for #-0
1829 if (Val == INT32_MIN) Val = 0;
1830 if (Val < 0) Val = -Val;
1831 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1832 } else {
1833 // For register offset, we encode the shift type and negation flag
1834 // here.
Jim Grosbach871dff72011-10-11 15:59:20 +00001835 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1836 Memory.ShiftImm, Memory.ShiftType);
Bruno Cardoso Lopesab830502011-03-31 23:26:08 +00001837 }
Jim Grosbach871dff72011-10-11 15:59:20 +00001838 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1839 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbachd3595712011-08-03 23:50:40 +00001840 Inst.addOperand(MCOperand::CreateImm(Val));
Bruno Cardoso Lopesab830502011-03-31 23:26:08 +00001841 }
1842
Jim Grosbachcd17c122011-08-04 23:01:30 +00001843 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1844 assert(N == 2 && "Invalid number of operands!");
1845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1846 assert(CE && "non-constant AM2OffsetImm operand!");
1847 int32_t Val = CE->getValue();
1848 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1849 // Special case for #-0
1850 if (Val == INT32_MIN) Val = 0;
1851 if (Val < 0) Val = -Val;
1852 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1853 Inst.addOperand(MCOperand::CreateReg(0));
1854 Inst.addOperand(MCOperand::CreateImm(Val));
1855 }
1856
Jim Grosbach5b96b802011-08-10 20:29:19 +00001857 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1858 assert(N == 3 && "Invalid number of operands!");
Jim Grosbach8648c102011-12-19 23:06:24 +00001859 // If we have an immediate that's not a constant, treat it as a label
1860 // reference needing a fixup. If it is a constant, it's something else
1861 // and we reject it.
1862 if (isImm()) {
1863 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1864 Inst.addOperand(MCOperand::CreateReg(0));
1865 Inst.addOperand(MCOperand::CreateImm(0));
1866 return;
1867 }
1868
Jim Grosbach871dff72011-10-11 15:59:20 +00001869 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1870 if (!Memory.OffsetRegNum) {
Jim Grosbach5b96b802011-08-10 20:29:19 +00001871 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1872 // Special case for #-0
1873 if (Val == INT32_MIN) Val = 0;
1874 if (Val < 0) Val = -Val;
1875 Val = ARM_AM::getAM3Opc(AddSub, Val);
1876 } else {
1877 // For register offset, we encode the shift type and negation flag
1878 // here.
Jim Grosbach871dff72011-10-11 15:59:20 +00001879 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
Jim Grosbach5b96b802011-08-10 20:29:19 +00001880 }
Jim Grosbach871dff72011-10-11 15:59:20 +00001881 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1882 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach5b96b802011-08-10 20:29:19 +00001883 Inst.addOperand(MCOperand::CreateImm(Val));
1884 }
1885
1886 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1887 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach6e5778f2011-10-07 23:24:09 +00001888 if (Kind == k_PostIndexRegister) {
Jim Grosbach5b96b802011-08-10 20:29:19 +00001889 int32_t Val =
1890 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1891 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1892 Inst.addOperand(MCOperand::CreateImm(Val));
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00001893 return;
Jim Grosbach5b96b802011-08-10 20:29:19 +00001894 }
1895
1896 // Constant offset.
1897 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1898 int32_t Val = CE->getValue();
1899 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1900 // Special case for #-0
1901 if (Val == INT32_MIN) Val = 0;
1902 if (Val < 0) Val = -Val;
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00001903 Val = ARM_AM::getAM3Opc(AddSub, Val);
Jim Grosbach5b96b802011-08-10 20:29:19 +00001904 Inst.addOperand(MCOperand::CreateReg(0));
1905 Inst.addOperand(MCOperand::CreateImm(Val));
1906 }
1907
Jim Grosbachd3595712011-08-03 23:50:40 +00001908 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1909 assert(N == 2 && "Invalid number of operands!");
Jim Grosbachfb2f1d62011-11-01 01:24:45 +00001910 // If we have an immediate that's not a constant, treat it as a label
1911 // reference needing a fixup. If it is a constant, it's something else
1912 // and we reject it.
1913 if (isImm()) {
1914 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1915 Inst.addOperand(MCOperand::CreateImm(0));
1916 return;
1917 }
1918
Jim Grosbachd3595712011-08-03 23:50:40 +00001919 // The lower two bits are always zero and as such are not encoded.
Jim Grosbach871dff72011-10-11 15:59:20 +00001920 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
Jim Grosbachd3595712011-08-03 23:50:40 +00001921 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1922 // Special case for #-0
1923 if (Val == INT32_MIN) Val = 0;
1924 if (Val < 0) Val = -Val;
1925 Val = ARM_AM::getAM5Opc(AddSub, Val);
Jim Grosbach871dff72011-10-11 15:59:20 +00001926 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbachd3595712011-08-03 23:50:40 +00001927 Inst.addOperand(MCOperand::CreateImm(Val));
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +00001928 }
1929
Jim Grosbach7db8d692011-09-08 22:07:06 +00001930 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1931 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach8648c102011-12-19 23:06:24 +00001932 // If we have an immediate that's not a constant, treat it as a label
1933 // reference needing a fixup. If it is a constant, it's something else
1934 // and we reject it.
1935 if (isImm()) {
1936 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1937 Inst.addOperand(MCOperand::CreateImm(0));
1938 return;
1939 }
1940
Jim Grosbach871dff72011-10-11 15:59:20 +00001941 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1942 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach7db8d692011-09-08 22:07:06 +00001943 Inst.addOperand(MCOperand::CreateImm(Val));
1944 }
1945
Jim Grosbacha05627e2011-09-09 18:37:27 +00001946 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1947 assert(N == 2 && "Invalid number of operands!");
1948 // The lower two bits are always zero and as such are not encoded.
Jim Grosbach871dff72011-10-11 15:59:20 +00001949 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1950 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbacha05627e2011-09-09 18:37:27 +00001951 Inst.addOperand(MCOperand::CreateImm(Val));
1952 }
1953
Jim Grosbachd3595712011-08-03 23:50:40 +00001954 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1955 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00001956 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1957 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbachd3595712011-08-03 23:50:40 +00001958 Inst.addOperand(MCOperand::CreateImm(Val));
Chris Lattner5d6f6a02010-10-29 00:27:31 +00001959 }
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00001960
Jim Grosbach2392c532011-09-07 23:39:14 +00001961 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1962 addMemImm8OffsetOperands(Inst, N);
1963 }
1964
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001965 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
Jim Grosbach2392c532011-09-07 23:39:14 +00001966 addMemImm8OffsetOperands(Inst, N);
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001967 }
1968
1969 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1970 assert(N == 2 && "Invalid number of operands!");
1971 // If this is an immediate, it's a label reference.
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001972 if (isImm()) {
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001973 addExpr(Inst, getImm());
1974 Inst.addOperand(MCOperand::CreateImm(0));
1975 return;
1976 }
1977
1978 // Otherwise, it's a normal memory reg+offset.
Jim Grosbach871dff72011-10-11 15:59:20 +00001979 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1980 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach5bfa8ba2011-09-07 20:58:57 +00001981 Inst.addOperand(MCOperand::CreateImm(Val));
1982 }
1983
Jim Grosbachd3595712011-08-03 23:50:40 +00001984 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1985 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach95466ce2011-08-08 20:59:31 +00001986 // If this is an immediate, it's a label reference.
Jim Grosbachc4d8d2f2011-12-22 22:02:35 +00001987 if (isImm()) {
Jim Grosbach95466ce2011-08-08 20:59:31 +00001988 addExpr(Inst, getImm());
1989 Inst.addOperand(MCOperand::CreateImm(0));
1990 return;
1991 }
1992
1993 // Otherwise, it's a normal memory reg+offset.
Jim Grosbach871dff72011-10-11 15:59:20 +00001994 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1995 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbachd3595712011-08-03 23:50:40 +00001996 Inst.addOperand(MCOperand::CreateImm(Val));
Bill Wendling092a7bd2010-12-14 03:36:38 +00001997 }
Bill Wendling811c9362010-11-30 07:44:32 +00001998
Jim Grosbach05541f42011-09-19 22:21:13 +00001999 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2000 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002001 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2002 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach05541f42011-09-19 22:21:13 +00002003 }
2004
2005 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2006 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002007 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2008 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach05541f42011-09-19 22:21:13 +00002009 }
2010
Jim Grosbachd3595712011-08-03 23:50:40 +00002011 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2012 assert(N == 3 && "Invalid number of operands!");
Jim Grosbachee201fa2011-11-14 17:52:47 +00002013 unsigned Val =
2014 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2015 Memory.ShiftImm, Memory.ShiftType);
Jim Grosbach871dff72011-10-11 15:59:20 +00002016 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2017 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbachd3595712011-08-03 23:50:40 +00002018 Inst.addOperand(MCOperand::CreateImm(Val));
2019 }
2020
Jim Grosbache0ebc1c2011-09-07 23:10:15 +00002021 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2022 assert(N == 3 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002023 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2024 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2025 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
Jim Grosbache0ebc1c2011-09-07 23:10:15 +00002026 }
2027
Jim Grosbachd3595712011-08-03 23:50:40 +00002028 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2029 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002030 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2031 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbachd3595712011-08-03 23:50:40 +00002032 }
2033
Jim Grosbach3fe94e32011-08-19 17:55:24 +00002034 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2035 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002036 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2037 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach3fe94e32011-08-19 17:55:24 +00002038 Inst.addOperand(MCOperand::CreateImm(Val));
2039 }
2040
Jim Grosbach26d35872011-08-19 18:55:51 +00002041 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2042 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002043 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2044 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach26d35872011-08-19 18:55:51 +00002045 Inst.addOperand(MCOperand::CreateImm(Val));
2046 }
2047
Jim Grosbacha32c7532011-08-19 18:49:59 +00002048 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2049 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002050 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2051 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbacha32c7532011-08-19 18:49:59 +00002052 Inst.addOperand(MCOperand::CreateImm(Val));
2053 }
2054
Jim Grosbach23983d62011-08-19 18:13:48 +00002055 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2056 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach871dff72011-10-11 15:59:20 +00002057 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2058 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach23983d62011-08-19 18:13:48 +00002059 Inst.addOperand(MCOperand::CreateImm(Val));
2060 }
2061
Jim Grosbachd3595712011-08-03 23:50:40 +00002062 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2063 assert(N == 1 && "Invalid number of operands!");
2064 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2065 assert(CE && "non-constant post-idx-imm8 operand!");
2066 int Imm = CE->getValue();
2067 bool isAdd = Imm >= 0;
Owen Andersonf02d98d2011-08-29 17:17:09 +00002068 if (Imm == INT32_MIN) Imm = 0;
Jim Grosbachd3595712011-08-03 23:50:40 +00002069 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2070 Inst.addOperand(MCOperand::CreateImm(Imm));
2071 }
2072
Jim Grosbach93981412011-10-11 21:55:36 +00002073 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2074 assert(N == 1 && "Invalid number of operands!");
2075 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2076 assert(CE && "non-constant post-idx-imm8s4 operand!");
2077 int Imm = CE->getValue();
2078 bool isAdd = Imm >= 0;
2079 if (Imm == INT32_MIN) Imm = 0;
2080 // Immediate is scaled by 4.
2081 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2082 Inst.addOperand(MCOperand::CreateImm(Imm));
2083 }
2084
Jim Grosbachd3595712011-08-03 23:50:40 +00002085 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2086 assert(N == 2 && "Invalid number of operands!");
2087 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
Jim Grosbachc320c852011-08-05 21:28:30 +00002088 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2089 }
2090
2091 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2092 assert(N == 2 && "Invalid number of operands!");
2093 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2094 // The sign, shift type, and shift amount are encoded in a single operand
2095 // using the AM2 encoding helpers.
2096 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2097 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2098 PostIdxReg.ShiftTy);
2099 Inst.addOperand(MCOperand::CreateImm(Imm));
Bill Wendling811c9362010-11-30 07:44:32 +00002100 }
2101
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00002102 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2103 assert(N == 1 && "Invalid number of operands!");
2104 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2105 }
2106
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00002107 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2108 assert(N == 1 && "Invalid number of operands!");
2109 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2110 }
2111
Jim Grosbach182b6a02011-11-29 23:51:09 +00002112 void addVecListOperands(MCInst &Inst, unsigned N) const {
Jim Grosbachad47cfc2011-10-18 23:02:30 +00002113 assert(N == 1 && "Invalid number of operands!");
2114 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2115 }
2116
Jim Grosbach04945c42011-12-02 00:35:16 +00002117 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2118 assert(N == 2 && "Invalid number of operands!");
2119 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2120 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2121 }
2122
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002123 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2124 assert(N == 1 && "Invalid number of operands!");
2125 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2126 }
2127
2128 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2129 assert(N == 1 && "Invalid number of operands!");
2130 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2131 }
2132
2133 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2134 assert(N == 1 && "Invalid number of operands!");
2135 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2136 }
2137
Jim Grosbach741cd732011-10-17 22:26:03 +00002138 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2139 assert(N == 1 && "Invalid number of operands!");
2140 // The immediate encodes the type of constant as well as the value.
2141 // Mask in that this is an i8 splat.
2142 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2143 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2144 }
2145
Jim Grosbachcda32ae2011-10-17 23:09:09 +00002146 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2147 assert(N == 1 && "Invalid number of operands!");
2148 // The immediate encodes the type of constant as well as the value.
2149 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2150 unsigned Value = CE->getValue();
2151 if (Value >= 256)
2152 Value = (Value >> 8) | 0xa00;
2153 else
2154 Value |= 0x800;
2155 Inst.addOperand(MCOperand::CreateImm(Value));
2156 }
2157
Jim Grosbach8211c052011-10-18 00:22:00 +00002158 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2159 assert(N == 1 && "Invalid number of operands!");
2160 // The immediate encodes the type of constant as well as the value.
2161 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2162 unsigned Value = CE->getValue();
2163 if (Value >= 256 && Value <= 0xff00)
2164 Value = (Value >> 8) | 0x200;
2165 else if (Value > 0xffff && Value <= 0xff0000)
2166 Value = (Value >> 16) | 0x400;
2167 else if (Value > 0xffffff)
2168 Value = (Value >> 24) | 0x600;
2169 Inst.addOperand(MCOperand::CreateImm(Value));
2170 }
2171
2172 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2173 assert(N == 1 && "Invalid number of operands!");
2174 // The immediate encodes the type of constant as well as the value.
2175 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2176 unsigned Value = CE->getValue();
2177 if (Value >= 256 && Value <= 0xffff)
2178 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2179 else if (Value > 0xffff && Value <= 0xffffff)
2180 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2181 else if (Value > 0xffffff)
2182 Value = (Value >> 24) | 0x600;
2183 Inst.addOperand(MCOperand::CreateImm(Value));
2184 }
2185
Jim Grosbach045b6c72011-12-19 23:51:07 +00002186 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2187 assert(N == 1 && "Invalid number of operands!");
2188 // The immediate encodes the type of constant as well as the value.
2189 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2190 unsigned Value = ~CE->getValue();
2191 if (Value >= 256 && Value <= 0xffff)
2192 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2193 else if (Value > 0xffff && Value <= 0xffffff)
2194 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2195 else if (Value > 0xffffff)
2196 Value = (Value >> 24) | 0x600;
2197 Inst.addOperand(MCOperand::CreateImm(Value));
2198 }
2199
Jim Grosbache4454e02011-10-18 16:18:11 +00002200 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2201 assert(N == 1 && "Invalid number of operands!");
2202 // The immediate encodes the type of constant as well as the value.
2203 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2204 uint64_t Value = CE->getValue();
2205 unsigned Imm = 0;
2206 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2207 Imm |= (Value & 1) << i;
2208 }
2209 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2210 }
2211
Jim Grosbach602aa902011-07-13 15:34:57 +00002212 virtual void print(raw_ostream &OS) const;
Daniel Dunbarebace222010-08-11 06:37:04 +00002213
Jim Grosbach3d1eac82011-08-26 21:43:41 +00002214 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002215 ARMOperand *Op = new ARMOperand(k_ITCondMask);
Jim Grosbach3d1eac82011-08-26 21:43:41 +00002216 Op->ITMask.Mask = Mask;
2217 Op->StartLoc = S;
2218 Op->EndLoc = S;
2219 return Op;
2220 }
2221
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002222 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002223 ARMOperand *Op = new ARMOperand(k_CondCode);
Daniel Dunbar188b47b2010-08-11 06:37:20 +00002224 Op->CC.Val = CC;
2225 Op->StartLoc = S;
2226 Op->EndLoc = S;
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002227 return Op;
Daniel Dunbar188b47b2010-08-11 06:37:20 +00002228 }
2229
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002230 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002231 ARMOperand *Op = new ARMOperand(k_CoprocNum);
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002232 Op->Cop.Val = CopVal;
2233 Op->StartLoc = S;
2234 Op->EndLoc = S;
2235 return Op;
2236 }
2237
2238 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002239 ARMOperand *Op = new ARMOperand(k_CoprocReg);
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002240 Op->Cop.Val = CopVal;
2241 Op->StartLoc = S;
2242 Op->EndLoc = S;
2243 return Op;
2244 }
2245
Jim Grosbach48399582011-10-12 17:34:41 +00002246 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2247 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2248 Op->Cop.Val = Val;
2249 Op->StartLoc = S;
2250 Op->EndLoc = E;
2251 return Op;
2252 }
2253
Jim Grosbach0bfb4d52010-12-06 18:21:12 +00002254 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002255 ARMOperand *Op = new ARMOperand(k_CCOut);
Jim Grosbach0bfb4d52010-12-06 18:21:12 +00002256 Op->Reg.RegNum = RegNum;
2257 Op->StartLoc = S;
2258 Op->EndLoc = S;
2259 return Op;
2260 }
2261
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002262 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002263 ARMOperand *Op = new ARMOperand(k_Token);
Sean Callanan7ad0ad02010-04-02 22:27:05 +00002264 Op->Tok.Data = Str.data();
2265 Op->Tok.Length = Str.size();
2266 Op->StartLoc = S;
2267 Op->EndLoc = S;
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002268 return Op;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00002269 }
2270
Bill Wendling2063b842010-11-18 23:43:05 +00002271 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002272 ARMOperand *Op = new ARMOperand(k_Register);
Sean Callanan7ad0ad02010-04-02 22:27:05 +00002273 Op->Reg.RegNum = RegNum;
Sean Callanan7ad0ad02010-04-02 22:27:05 +00002274 Op->StartLoc = S;
2275 Op->EndLoc = E;
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002276 return Op;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00002277 }
2278
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002279 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2280 unsigned SrcReg,
2281 unsigned ShiftReg,
2282 unsigned ShiftImm,
2283 SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002284 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
Jim Grosbachac798e12011-07-25 20:49:51 +00002285 Op->RegShiftedReg.ShiftTy = ShTy;
2286 Op->RegShiftedReg.SrcReg = SrcReg;
2287 Op->RegShiftedReg.ShiftReg = ShiftReg;
2288 Op->RegShiftedReg.ShiftImm = ShiftImm;
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002289 Op->StartLoc = S;
2290 Op->EndLoc = E;
2291 return Op;
2292 }
2293
Owen Andersonb595ed02011-07-21 18:54:16 +00002294 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2295 unsigned SrcReg,
2296 unsigned ShiftImm,
2297 SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002298 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
Jim Grosbachac798e12011-07-25 20:49:51 +00002299 Op->RegShiftedImm.ShiftTy = ShTy;
2300 Op->RegShiftedImm.SrcReg = SrcReg;
2301 Op->RegShiftedImm.ShiftImm = ShiftImm;
Owen Andersonb595ed02011-07-21 18:54:16 +00002302 Op->StartLoc = S;
2303 Op->EndLoc = E;
2304 return Op;
2305 }
2306
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00002307 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002308 SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002309 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00002310 Op->ShifterImm.isASR = isASR;
2311 Op->ShifterImm.Imm = Imm;
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002312 Op->StartLoc = S;
2313 Op->EndLoc = E;
2314 return Op;
2315 }
2316
Jim Grosbach833b9d32011-07-27 20:15:40 +00002317 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002318 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
Jim Grosbach833b9d32011-07-27 20:15:40 +00002319 Op->RotImm.Imm = Imm;
2320 Op->StartLoc = S;
2321 Op->EndLoc = E;
2322 return Op;
2323 }
2324
Jim Grosbach864b6092011-07-28 21:34:26 +00002325 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2326 SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002327 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
Jim Grosbach864b6092011-07-28 21:34:26 +00002328 Op->Bitfield.LSB = LSB;
2329 Op->Bitfield.Width = Width;
2330 Op->StartLoc = S;
2331 Op->EndLoc = E;
2332 return Op;
2333 }
2334
Bill Wendling2cae3272010-11-09 22:44:22 +00002335 static ARMOperand *
Chad Rosierfa705ee2013-07-01 20:49:23 +00002336 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
Matt Beaumont-Gay55c4cc72010-11-10 00:08:58 +00002337 SMLoc StartLoc, SMLoc EndLoc) {
Chad Rosierfa705ee2013-07-01 20:49:23 +00002338 assert (Regs.size() > 0 && "RegList contains no registers?");
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002339 KindTy Kind = k_RegisterList;
Bill Wendling9898ac92010-11-17 04:32:08 +00002340
Chad Rosierfa705ee2013-07-01 20:49:23 +00002341 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002342 Kind = k_DPRRegisterList;
Jim Grosbach75461af2011-09-13 22:56:44 +00002343 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
Chad Rosierfa705ee2013-07-01 20:49:23 +00002344 contains(Regs.front().second))
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002345 Kind = k_SPRRegisterList;
Bill Wendling9898ac92010-11-17 04:32:08 +00002346
Chad Rosierfa705ee2013-07-01 20:49:23 +00002347 // Sort based on the register encoding values.
2348 array_pod_sort(Regs.begin(), Regs.end());
2349
Bill Wendling9898ac92010-11-17 04:32:08 +00002350 ARMOperand *Op = new ARMOperand(Kind);
Chad Rosierfa705ee2013-07-01 20:49:23 +00002351 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
Bill Wendling2cae3272010-11-09 22:44:22 +00002352 I = Regs.begin(), E = Regs.end(); I != E; ++I)
Chad Rosierfa705ee2013-07-01 20:49:23 +00002353 Op->Registers.push_back(I->second);
Matt Beaumont-Gay55c4cc72010-11-10 00:08:58 +00002354 Op->StartLoc = StartLoc;
2355 Op->EndLoc = EndLoc;
Bill Wendling7cef4472010-11-06 19:56:04 +00002356 return Op;
2357 }
2358
Jim Grosbachad47cfc2011-10-18 23:02:30 +00002359 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
Jim Grosbach2f50e922011-12-15 21:44:33 +00002360 bool isDoubleSpaced, SMLoc S, SMLoc E) {
Jim Grosbachad47cfc2011-10-18 23:02:30 +00002361 ARMOperand *Op = new ARMOperand(k_VectorList);
2362 Op->VectorList.RegNum = RegNum;
2363 Op->VectorList.Count = Count;
Jim Grosbach2f50e922011-12-15 21:44:33 +00002364 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Jim Grosbachad47cfc2011-10-18 23:02:30 +00002365 Op->StartLoc = S;
2366 Op->EndLoc = E;
2367 return Op;
2368 }
2369
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00002370 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
Jim Grosbachc5af54e2011-12-21 00:38:54 +00002371 bool isDoubleSpaced,
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00002372 SMLoc S, SMLoc E) {
2373 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2374 Op->VectorList.RegNum = RegNum;
2375 Op->VectorList.Count = Count;
Jim Grosbachc5af54e2011-12-21 00:38:54 +00002376 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00002377 Op->StartLoc = S;
2378 Op->EndLoc = E;
2379 return Op;
2380 }
2381
Jim Grosbach04945c42011-12-02 00:35:16 +00002382 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
Jim Grosbach75e2ab52011-12-20 19:21:26 +00002383 unsigned Index,
2384 bool isDoubleSpaced,
2385 SMLoc S, SMLoc E) {
Jim Grosbach04945c42011-12-02 00:35:16 +00002386 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2387 Op->VectorList.RegNum = RegNum;
2388 Op->VectorList.Count = Count;
2389 Op->VectorList.LaneIndex = Index;
Jim Grosbach75e2ab52011-12-20 19:21:26 +00002390 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Jim Grosbach04945c42011-12-02 00:35:16 +00002391 Op->StartLoc = S;
2392 Op->EndLoc = E;
2393 return Op;
2394 }
2395
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002396 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2397 MCContext &Ctx) {
2398 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2399 Op->VectorIndex.Val = Idx;
2400 Op->StartLoc = S;
2401 Op->EndLoc = E;
2402 return Op;
2403 }
2404
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002405 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002406 ARMOperand *Op = new ARMOperand(k_Immediate);
Sean Callanan7ad0ad02010-04-02 22:27:05 +00002407 Op->Imm.Val = Val;
Sean Callanan7ad0ad02010-04-02 22:27:05 +00002408 Op->StartLoc = S;
2409 Op->EndLoc = E;
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002410 return Op;
Kevin Enderbyf5079942009-10-13 22:19:02 +00002411 }
2412
Jim Grosbachd3595712011-08-03 23:50:40 +00002413 static ARMOperand *CreateMem(unsigned BaseRegNum,
2414 const MCConstantExpr *OffsetImm,
2415 unsigned OffsetRegNum,
2416 ARM_AM::ShiftOpc ShiftType,
Jim Grosbach3d0b3a32011-08-05 22:03:36 +00002417 unsigned ShiftImm,
Jim Grosbacha95ec992011-10-11 17:29:55 +00002418 unsigned Alignment,
Jim Grosbachd3595712011-08-03 23:50:40 +00002419 bool isNegative,
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002420 SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002421 ARMOperand *Op = new ARMOperand(k_Memory);
Jim Grosbach871dff72011-10-11 15:59:20 +00002422 Op->Memory.BaseRegNum = BaseRegNum;
2423 Op->Memory.OffsetImm = OffsetImm;
2424 Op->Memory.OffsetRegNum = OffsetRegNum;
2425 Op->Memory.ShiftType = ShiftType;
2426 Op->Memory.ShiftImm = ShiftImm;
Jim Grosbacha95ec992011-10-11 17:29:55 +00002427 Op->Memory.Alignment = Alignment;
Jim Grosbach871dff72011-10-11 15:59:20 +00002428 Op->Memory.isNegative = isNegative;
Jim Grosbachd3595712011-08-03 23:50:40 +00002429 Op->StartLoc = S;
2430 Op->EndLoc = E;
2431 return Op;
2432 }
Jim Grosbach624bcc72010-10-29 14:46:02 +00002433
Jim Grosbachc320c852011-08-05 21:28:30 +00002434 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2435 ARM_AM::ShiftOpc ShiftTy,
2436 unsigned ShiftImm,
Jim Grosbachd3595712011-08-03 23:50:40 +00002437 SMLoc S, SMLoc E) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002438 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
Jim Grosbachd3595712011-08-03 23:50:40 +00002439 Op->PostIdxReg.RegNum = RegNum;
Jim Grosbachc320c852011-08-05 21:28:30 +00002440 Op->PostIdxReg.isAdd = isAdd;
2441 Op->PostIdxReg.ShiftTy = ShiftTy;
2442 Op->PostIdxReg.ShiftImm = ShiftImm;
Sean Callanan7ad0ad02010-04-02 22:27:05 +00002443 Op->StartLoc = S;
2444 Op->EndLoc = E;
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002445 return Op;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00002446 }
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00002447
2448 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002449 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00002450 Op->MBOpt.Val = Opt;
2451 Op->StartLoc = S;
2452 Op->EndLoc = S;
2453 return Op;
2454 }
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00002455
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00002456 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2457 SMLoc S) {
2458 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2459 Op->ISBOpt.Val = Opt;
2460 Op->StartLoc = S;
2461 Op->EndLoc = S;
2462 return Op;
2463 }
2464
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00002465 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002466 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00002467 Op->IFlags.Val = IFlags;
2468 Op->StartLoc = S;
2469 Op->EndLoc = S;
2470 return Op;
2471 }
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00002472
2473 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002474 ARMOperand *Op = new ARMOperand(k_MSRMask);
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00002475 Op->MMask.Val = MMask;
2476 Op->StartLoc = S;
2477 Op->EndLoc = S;
2478 return Op;
2479 }
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00002480};
2481
2482} // end anonymous namespace.
2483
Jim Grosbach602aa902011-07-13 15:34:57 +00002484void ARMOperand::print(raw_ostream &OS) const {
Daniel Dunbar4a863e62010-08-11 06:37:12 +00002485 switch (Kind) {
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002486 case k_CondCode:
Daniel Dunbar2be732a2011-01-10 15:26:21 +00002487 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
Daniel Dunbar4a863e62010-08-11 06:37:12 +00002488 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002489 case k_CCOut:
Jim Grosbach0bfb4d52010-12-06 18:21:12 +00002490 OS << "<ccout " << getReg() << ">";
2491 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002492 case k_ITCondMask: {
Craig Topper42b96d12012-05-24 04:11:15 +00002493 static const char *const MaskStr[] = {
Benjamin Kramer0d6d0982011-10-22 16:50:00 +00002494 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2495 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2496 };
Jim Grosbach3d1eac82011-08-26 21:43:41 +00002497 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2498 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2499 break;
2500 }
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002501 case k_CoprocNum:
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002502 OS << "<coprocessor number: " << getCoproc() << ">";
2503 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002504 case k_CoprocReg:
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002505 OS << "<coprocessor register: " << getCoproc() << ">";
2506 break;
Jim Grosbach48399582011-10-12 17:34:41 +00002507 case k_CoprocOption:
2508 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2509 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002510 case k_MSRMask:
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00002511 OS << "<mask: " << getMSRMask() << ">";
2512 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002513 case k_Immediate:
Daniel Dunbar4a863e62010-08-11 06:37:12 +00002514 getImm()->print(OS);
2515 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002516 case k_MemBarrierOpt:
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00002517 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2518 break;
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00002519 case k_InstSyncBarrierOpt:
2520 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2521 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002522 case k_Memory:
Daniel Dunbarbcd8eb02011-01-18 05:55:21 +00002523 OS << "<memory "
Jim Grosbach871dff72011-10-11 15:59:20 +00002524 << " base:" << Memory.BaseRegNum;
Daniel Dunbarbcd8eb02011-01-18 05:55:21 +00002525 OS << ">";
Daniel Dunbar4a863e62010-08-11 06:37:12 +00002526 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002527 case k_PostIndexRegister:
Jim Grosbachc320c852011-08-05 21:28:30 +00002528 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2529 << PostIdxReg.RegNum;
2530 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2531 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2532 << PostIdxReg.ShiftImm;
2533 OS << ">";
Jim Grosbachd3595712011-08-03 23:50:40 +00002534 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002535 case k_ProcIFlags: {
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00002536 OS << "<ARM_PROC::";
2537 unsigned IFlags = getProcIFlags();
2538 for (int i=2; i >= 0; --i)
2539 if (IFlags & (1 << i))
2540 OS << ARM_PROC::IFlagsToString(1 << i);
2541 OS << ">";
2542 break;
2543 }
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002544 case k_Register:
Bill Wendling2063b842010-11-18 23:43:05 +00002545 OS << "<register " << getReg() << ">";
Daniel Dunbar4a863e62010-08-11 06:37:12 +00002546 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002547 case k_ShifterImmediate:
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00002548 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2549 << " #" << ShifterImm.Imm << ">";
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002550 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002551 case k_ShiftedRegister:
Owen Andersonb595ed02011-07-21 18:54:16 +00002552 OS << "<so_reg_reg "
Jim Grosbach01e04392011-11-16 21:46:50 +00002553 << RegShiftedReg.SrcReg << " "
2554 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2555 << " " << RegShiftedReg.ShiftReg << ">";
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002556 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002557 case k_ShiftedImmediate:
Owen Andersonb595ed02011-07-21 18:54:16 +00002558 OS << "<so_reg_imm "
Jim Grosbach01e04392011-11-16 21:46:50 +00002559 << RegShiftedImm.SrcReg << " "
2560 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2561 << " #" << RegShiftedImm.ShiftImm << ">";
Owen Andersonb595ed02011-07-21 18:54:16 +00002562 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002563 case k_RotateImmediate:
Jim Grosbach833b9d32011-07-27 20:15:40 +00002564 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2565 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002566 case k_BitfieldDescriptor:
Jim Grosbach864b6092011-07-28 21:34:26 +00002567 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2568 << ", width: " << Bitfield.Width << ">";
2569 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002570 case k_RegisterList:
2571 case k_DPRRegisterList:
2572 case k_SPRRegisterList: {
Bill Wendling7cef4472010-11-06 19:56:04 +00002573 OS << "<register_list ";
Bill Wendling7cef4472010-11-06 19:56:04 +00002574
Bill Wendlingbed94652010-11-09 23:28:44 +00002575 const SmallVectorImpl<unsigned> &RegList = getRegList();
2576 for (SmallVectorImpl<unsigned>::const_iterator
Bill Wendling2cae3272010-11-09 22:44:22 +00002577 I = RegList.begin(), E = RegList.end(); I != E; ) {
2578 OS << *I;
2579 if (++I < E) OS << ", ";
Bill Wendling7cef4472010-11-06 19:56:04 +00002580 }
2581
2582 OS << ">";
2583 break;
2584 }
Jim Grosbachad47cfc2011-10-18 23:02:30 +00002585 case k_VectorList:
2586 OS << "<vector_list " << VectorList.Count << " * "
2587 << VectorList.RegNum << ">";
2588 break;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00002589 case k_VectorListAllLanes:
2590 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2591 << VectorList.RegNum << ">";
2592 break;
Jim Grosbach04945c42011-12-02 00:35:16 +00002593 case k_VectorListIndexed:
2594 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2595 << VectorList.Count << " * " << VectorList.RegNum << ">";
2596 break;
Jim Grosbach6e5778f2011-10-07 23:24:09 +00002597 case k_Token:
Daniel Dunbar4a863e62010-08-11 06:37:12 +00002598 OS << "'" << getToken() << "'";
2599 break;
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002600 case k_VectorIndex:
2601 OS << "<vectorindex " << getVectorIndex() << ">";
2602 break;
Daniel Dunbar4a863e62010-08-11 06:37:12 +00002603 }
2604}
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00002605
2606/// @name Auto-generated Match Functions
2607/// {
2608
2609static unsigned MatchRegisterName(StringRef Name);
2610
2611/// }
2612
Bob Wilsonfb0bd042011-02-03 21:46:10 +00002613bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2614 SMLoc &StartLoc, SMLoc &EndLoc) {
Jim Grosbachab5830e2011-12-14 02:16:11 +00002615 StartLoc = Parser.getTok().getLoc();
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002616 EndLoc = Parser.getTok().getEndLoc();
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00002617 RegNo = tryParseRegister();
Roman Divacky36b1b472011-01-27 17:14:22 +00002618
2619 return (RegNo == (unsigned)-1);
2620}
2621
Kevin Enderby8be42bd2009-10-30 22:55:57 +00002622/// Try to parse a register name. The token must be an Identifier when called,
Chris Lattner44e5981c2010-10-30 04:09:10 +00002623/// and if it is a register name the token is eaten and the register number is
2624/// returned. Otherwise return -1.
2625///
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00002626int ARMAsmParser::tryParseRegister() {
Chris Lattner44e5981c2010-10-30 04:09:10 +00002627 const AsmToken &Tok = Parser.getTok();
Jim Grosbachd3595712011-08-03 23:50:40 +00002628 if (Tok.isNot(AsmToken::Identifier)) return -1;
Jim Grosbach99710a82010-11-01 16:44:21 +00002629
Benjamin Kramer20baffb2011-11-06 20:37:06 +00002630 std::string lowerCase = Tok.getString().lower();
Owen Andersona098d152011-01-13 22:50:36 +00002631 unsigned RegNum = MatchRegisterName(lowerCase);
2632 if (!RegNum) {
2633 RegNum = StringSwitch<unsigned>(lowerCase)
2634 .Case("r13", ARM::SP)
2635 .Case("r14", ARM::LR)
2636 .Case("r15", ARM::PC)
2637 .Case("ip", ARM::R12)
Jim Grosbach4edc7362011-12-08 19:27:38 +00002638 // Additional register name aliases for 'gas' compatibility.
2639 .Case("a1", ARM::R0)
2640 .Case("a2", ARM::R1)
2641 .Case("a3", ARM::R2)
2642 .Case("a4", ARM::R3)
2643 .Case("v1", ARM::R4)
2644 .Case("v2", ARM::R5)
2645 .Case("v3", ARM::R6)
2646 .Case("v4", ARM::R7)
2647 .Case("v5", ARM::R8)
2648 .Case("v6", ARM::R9)
2649 .Case("v7", ARM::R10)
2650 .Case("v8", ARM::R11)
2651 .Case("sb", ARM::R9)
2652 .Case("sl", ARM::R10)
2653 .Case("fp", ARM::R11)
Owen Andersona098d152011-01-13 22:50:36 +00002654 .Default(0);
2655 }
Jim Grosbachab5830e2011-12-14 02:16:11 +00002656 if (!RegNum) {
Jim Grosbachcd22e4a2011-12-20 23:11:00 +00002657 // Check for aliases registered via .req. Canonicalize to lower case.
2658 // That's more consistent since register names are case insensitive, and
2659 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2660 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
Jim Grosbachab5830e2011-12-14 02:16:11 +00002661 // If no match, return failure.
2662 if (Entry == RegisterReqs.end())
2663 return -1;
2664 Parser.Lex(); // Eat identifier token.
2665 return Entry->getValue();
2666 }
Bob Wilsonfb0bd042011-02-03 21:46:10 +00002667
Chris Lattner44e5981c2010-10-30 04:09:10 +00002668 Parser.Lex(); // Eat identifier token.
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002669
Chris Lattner44e5981c2010-10-30 04:09:10 +00002670 return RegNum;
2671}
Jim Grosbach99710a82010-11-01 16:44:21 +00002672
Jim Grosbachbb24c592011-07-13 18:49:30 +00002673// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2674// If a recoverable error occurs, return 1. If an irrecoverable error
2675// occurs, return -1. An irrecoverable error is one where tokens have been
2676// consumed in the process of trying to parse the shifter (i.e., when it is
2677// indeed a shifter operand, but malformed).
Jim Grosbach0d6022d2011-07-26 20:41:24 +00002678int ARMAsmParser::tryParseShiftRegister(
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002679 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2680 SMLoc S = Parser.getTok().getLoc();
2681 const AsmToken &Tok = Parser.getTok();
2682 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2683
Benjamin Kramer20baffb2011-11-06 20:37:06 +00002684 std::string lowerCase = Tok.getString().lower();
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002685 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
Jim Grosbach3b559ff2011-12-07 23:40:58 +00002686 .Case("asl", ARM_AM::lsl)
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002687 .Case("lsl", ARM_AM::lsl)
2688 .Case("lsr", ARM_AM::lsr)
2689 .Case("asr", ARM_AM::asr)
2690 .Case("ror", ARM_AM::ror)
2691 .Case("rrx", ARM_AM::rrx)
2692 .Default(ARM_AM::no_shift);
2693
2694 if (ShiftTy == ARM_AM::no_shift)
Jim Grosbachbb24c592011-07-13 18:49:30 +00002695 return 1;
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002696
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002697 Parser.Lex(); // Eat the operator.
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002698
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002699 // The source register for the shift has already been added to the
2700 // operand list, so we need to pop it off and combine it into the shifted
2701 // register operand instead.
Benjamin Kramer1757e7a2011-07-14 18:41:22 +00002702 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002703 if (!PrevOp->isReg())
2704 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2705 int SrcReg = PrevOp->getReg();
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002706
2707 SMLoc EndLoc;
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002708 int64_t Imm = 0;
2709 int ShiftReg = 0;
2710 if (ShiftTy == ARM_AM::rrx) {
2711 // RRX Doesn't have an explicit shift amount. The encoder expects
2712 // the shift register to be the same as the source register. Seems odd,
2713 // but OK.
2714 ShiftReg = SrcReg;
2715 } else {
2716 // Figure out if this is shifted by a constant or a register (for non-RRX).
Jim Grosbachef70e9b2011-12-09 22:25:03 +00002717 if (Parser.getTok().is(AsmToken::Hash) ||
2718 Parser.getTok().is(AsmToken::Dollar)) {
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002719 Parser.Lex(); // Eat hash.
2720 SMLoc ImmLoc = Parser.getTok().getLoc();
2721 const MCExpr *ShiftExpr = 0;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002722 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
Jim Grosbachbb24c592011-07-13 18:49:30 +00002723 Error(ImmLoc, "invalid immediate shift value");
2724 return -1;
2725 }
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002726 // The expression must be evaluatable as an immediate.
2727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
Jim Grosbachbb24c592011-07-13 18:49:30 +00002728 if (!CE) {
2729 Error(ImmLoc, "invalid immediate shift value");
2730 return -1;
2731 }
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002732 // Range check the immediate.
2733 // lsl, ror: 0 <= imm <= 31
2734 // lsr, asr: 0 <= imm <= 32
2735 Imm = CE->getValue();
2736 if (Imm < 0 ||
2737 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2738 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
Jim Grosbachbb24c592011-07-13 18:49:30 +00002739 Error(ImmLoc, "immediate shift value out of range");
2740 return -1;
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002741 }
Jim Grosbach21488b82011-12-22 17:37:00 +00002742 // shift by zero is a nop. Always send it through as lsl.
2743 // ('as' compatibility)
2744 if (Imm == 0)
2745 ShiftTy = ARM_AM::lsl;
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002746 } else if (Parser.getTok().is(AsmToken::Identifier)) {
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002747 SMLoc L = Parser.getTok().getLoc();
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002748 EndLoc = Parser.getTok().getEndLoc();
2749 ShiftReg = tryParseRegister();
Jim Grosbachbb24c592011-07-13 18:49:30 +00002750 if (ShiftReg == -1) {
2751 Error (L, "expected immediate or register in shift operand");
2752 return -1;
2753 }
2754 } else {
2755 Error (Parser.getTok().getLoc(),
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002756 "expected immediate or register in shift operand");
Jim Grosbachbb24c592011-07-13 18:49:30 +00002757 return -1;
2758 }
Jim Grosbach7dcd1352011-07-13 17:50:29 +00002759 }
2760
Owen Andersonb595ed02011-07-21 18:54:16 +00002761 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2762 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
Jim Grosbachac798e12011-07-25 20:49:51 +00002763 ShiftReg, Imm,
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002764 S, EndLoc));
Owen Andersonb595ed02011-07-21 18:54:16 +00002765 else
2766 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002767 S, EndLoc));
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002768
Jim Grosbachbb24c592011-07-13 18:49:30 +00002769 return 0;
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00002770}
2771
2772
Bill Wendling2063b842010-11-18 23:43:05 +00002773/// Try to parse a register name. The token must be an Identifier when called.
2774/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2775/// if there is a "writeback". 'true' if it's not a register.
Chris Lattnerbd7c9fa2010-10-28 17:20:03 +00002776///
Kevin Enderby8be42bd2009-10-30 22:55:57 +00002777/// TODO this is likely to change to allow different register types and or to
2778/// parse for a specific register type.
Bill Wendling2063b842010-11-18 23:43:05 +00002779bool ARMAsmParser::
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00002780tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002781 const AsmToken &RegTok = Parser.getTok();
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00002782 int RegNo = tryParseRegister();
Bill Wendlinge18980a2010-11-06 22:36:58 +00002783 if (RegNo == -1)
Bill Wendling2063b842010-11-18 23:43:05 +00002784 return true;
Jim Grosbach99710a82010-11-01 16:44:21 +00002785
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002786 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2787 RegTok.getEndLoc()));
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00002788
Chris Lattner44e5981c2010-10-30 04:09:10 +00002789 const AsmToken &ExclaimTok = Parser.getTok();
2790 if (ExclaimTok.is(AsmToken::Exclaim)) {
Bill Wendling2063b842010-11-18 23:43:05 +00002791 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2792 ExclaimTok.getLoc()));
Chris Lattner44e5981c2010-10-30 04:09:10 +00002793 Parser.Lex(); // Eat exclaim token
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002794 return false;
2795 }
2796
2797 // Also check for an index operand. This is only legal for vector registers,
2798 // but that'll get caught OK in operand matching, so we don't need to
2799 // explicitly filter everything else out here.
2800 if (Parser.getTok().is(AsmToken::LBrac)) {
2801 SMLoc SIdx = Parser.getTok().getLoc();
2802 Parser.Lex(); // Eat left bracket token.
2803
2804 const MCExpr *ImmVal;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002805 if (getParser().parseExpression(ImmVal))
Jim Grosbacha2147ce2012-01-31 23:51:09 +00002806 return true;
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002807 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
Jim Grosbachc8f2b782012-01-26 15:56:45 +00002808 if (!MCE)
2809 return TokError("immediate value expected for vector index");
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002810
Jim Grosbachc8f2b782012-01-26 15:56:45 +00002811 if (Parser.getTok().isNot(AsmToken::RBrac))
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002812 return Error(Parser.getTok().getLoc(), "']' expected");
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002813
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002814 SMLoc E = Parser.getTok().getEndLoc();
Jim Grosbachd0637bf2011-10-07 23:56:00 +00002815 Parser.Lex(); // Eat right bracket token.
2816
2817 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2818 SIdx, E,
2819 getContext()));
Kevin Enderby2207e5f2009-10-07 18:01:35 +00002820 }
2821
Bill Wendling2063b842010-11-18 23:43:05 +00002822 return false;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00002823}
2824
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002825/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2826/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2827/// "c5", ...
2828static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002829 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2830 // but efficient.
2831 switch (Name.size()) {
David Blaikie46a9f012012-01-20 21:51:11 +00002832 default: return -1;
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002833 case 2:
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002834 if (Name[0] != CoprocOp)
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002835 return -1;
2836 switch (Name[1]) {
2837 default: return -1;
2838 case '0': return 0;
2839 case '1': return 1;
2840 case '2': return 2;
2841 case '3': return 3;
2842 case '4': return 4;
2843 case '5': return 5;
2844 case '6': return 6;
2845 case '7': return 7;
2846 case '8': return 8;
2847 case '9': return 9;
2848 }
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002849 case 3:
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002850 if (Name[0] != CoprocOp || Name[1] != '1')
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002851 return -1;
2852 switch (Name[2]) {
2853 default: return -1;
2854 case '0': return 10;
2855 case '1': return 11;
2856 case '2': return 12;
2857 case '3': return 13;
2858 case '4': return 14;
2859 case '5': return 15;
2860 }
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002861 }
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002862}
2863
Jim Grosbach3d1eac82011-08-26 21:43:41 +00002864/// parseITCondCode - Try to parse a condition code for an IT instruction.
2865ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2866parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2867 SMLoc S = Parser.getTok().getLoc();
2868 const AsmToken &Tok = Parser.getTok();
2869 if (!Tok.is(AsmToken::Identifier))
2870 return MatchOperand_NoMatch;
Richard Barton82f95ea2012-04-27 17:34:01 +00002871 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
Jim Grosbach3d1eac82011-08-26 21:43:41 +00002872 .Case("eq", ARMCC::EQ)
2873 .Case("ne", ARMCC::NE)
2874 .Case("hs", ARMCC::HS)
2875 .Case("cs", ARMCC::HS)
2876 .Case("lo", ARMCC::LO)
2877 .Case("cc", ARMCC::LO)
2878 .Case("mi", ARMCC::MI)
2879 .Case("pl", ARMCC::PL)
2880 .Case("vs", ARMCC::VS)
2881 .Case("vc", ARMCC::VC)
2882 .Case("hi", ARMCC::HI)
2883 .Case("ls", ARMCC::LS)
2884 .Case("ge", ARMCC::GE)
2885 .Case("lt", ARMCC::LT)
2886 .Case("gt", ARMCC::GT)
2887 .Case("le", ARMCC::LE)
2888 .Case("al", ARMCC::AL)
2889 .Default(~0U);
2890 if (CC == ~0U)
2891 return MatchOperand_NoMatch;
2892 Parser.Lex(); // Eat the token.
2893
2894 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2895
2896 return MatchOperand_Success;
2897}
2898
Jim Grosbach2d6ef442011-07-25 20:14:50 +00002899/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002900/// token must be an Identifier when called, and if it is a coprocessor
2901/// number, the token is eaten and the operand is added to the operand list.
Jim Grosbach861e49c2011-02-12 01:34:40 +00002902ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach2d6ef442011-07-25 20:14:50 +00002903parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002904 SMLoc S = Parser.getTok().getLoc();
2905 const AsmToken &Tok = Parser.getTok();
Jim Grosbach54a20ed2011-10-12 20:54:17 +00002906 if (Tok.isNot(AsmToken::Identifier))
2907 return MatchOperand_NoMatch;
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002908
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002909 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002910 if (Num == -1)
Jim Grosbach861e49c2011-02-12 01:34:40 +00002911 return MatchOperand_NoMatch;
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002912
2913 Parser.Lex(); // Eat identifier token.
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002914 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
Jim Grosbach861e49c2011-02-12 01:34:40 +00002915 return MatchOperand_Success;
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002916}
2917
Jim Grosbach2d6ef442011-07-25 20:14:50 +00002918/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002919/// token must be an Identifier when called, and if it is a coprocessor
2920/// number, the token is eaten and the operand is added to the operand list.
Jim Grosbach861e49c2011-02-12 01:34:40 +00002921ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach2d6ef442011-07-25 20:14:50 +00002922parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002923 SMLoc S = Parser.getTok().getLoc();
2924 const AsmToken &Tok = Parser.getTok();
Jim Grosbach54a20ed2011-10-12 20:54:17 +00002925 if (Tok.isNot(AsmToken::Identifier))
2926 return MatchOperand_NoMatch;
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002927
2928 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2929 if (Reg == -1)
Jim Grosbach861e49c2011-02-12 01:34:40 +00002930 return MatchOperand_NoMatch;
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00002931
2932 Parser.Lex(); // Eat identifier token.
2933 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
Jim Grosbach861e49c2011-02-12 01:34:40 +00002934 return MatchOperand_Success;
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00002935}
2936
Jim Grosbach48399582011-10-12 17:34:41 +00002937/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2938/// coproc_option : '{' imm0_255 '}'
2939ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2940parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2941 SMLoc S = Parser.getTok().getLoc();
2942
2943 // If this isn't a '{', this isn't a coprocessor immediate operand.
2944 if (Parser.getTok().isNot(AsmToken::LCurly))
2945 return MatchOperand_NoMatch;
2946 Parser.Lex(); // Eat the '{'
2947
2948 const MCExpr *Expr;
2949 SMLoc Loc = Parser.getTok().getLoc();
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002950 if (getParser().parseExpression(Expr)) {
Jim Grosbach48399582011-10-12 17:34:41 +00002951 Error(Loc, "illegal expression");
2952 return MatchOperand_ParseFail;
2953 }
2954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2955 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2956 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2957 return MatchOperand_ParseFail;
2958 }
2959 int Val = CE->getValue();
2960
2961 // Check for and consume the closing '}'
2962 if (Parser.getTok().isNot(AsmToken::RCurly))
2963 return MatchOperand_ParseFail;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002964 SMLoc E = Parser.getTok().getEndLoc();
Jim Grosbach48399582011-10-12 17:34:41 +00002965 Parser.Lex(); // Eat the '}'
2966
2967 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2968 return MatchOperand_Success;
2969}
2970
Jim Grosbach3ac26b12011-09-14 18:08:35 +00002971// For register list parsing, we need to map from raw GPR register numbering
2972// to the enumeration values. The enumeration values aren't sorted by
2973// register number due to our using "sp", "lr" and "pc" as canonical names.
2974static unsigned getNextRegister(unsigned Reg) {
2975 // If this is a GPR, we need to do it manually, otherwise we can rely
2976 // on the sort ordering of the enumeration since the other reg-classes
2977 // are sane.
2978 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2979 return Reg + 1;
2980 switch(Reg) {
Craig Toppere55c5562012-02-07 02:50:20 +00002981 default: llvm_unreachable("Invalid GPR number!");
Jim Grosbach3ac26b12011-09-14 18:08:35 +00002982 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2983 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2984 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2985 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2986 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2987 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2988 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2989 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2990 }
2991}
2992
Jim Grosbach85a23432011-11-11 21:27:40 +00002993// Return the low-subreg of a given Q register.
2994static unsigned getDRegFromQReg(unsigned QReg) {
2995 switch (QReg) {
2996 default: llvm_unreachable("expected a Q register!");
2997 case ARM::Q0: return ARM::D0;
2998 case ARM::Q1: return ARM::D2;
2999 case ARM::Q2: return ARM::D4;
3000 case ARM::Q3: return ARM::D6;
3001 case ARM::Q4: return ARM::D8;
3002 case ARM::Q5: return ARM::D10;
3003 case ARM::Q6: return ARM::D12;
3004 case ARM::Q7: return ARM::D14;
3005 case ARM::Q8: return ARM::D16;
Jim Grosbacha92a5d82011-11-15 21:01:30 +00003006 case ARM::Q9: return ARM::D18;
Jim Grosbach85a23432011-11-11 21:27:40 +00003007 case ARM::Q10: return ARM::D20;
3008 case ARM::Q11: return ARM::D22;
3009 case ARM::Q12: return ARM::D24;
3010 case ARM::Q13: return ARM::D26;
3011 case ARM::Q14: return ARM::D28;
3012 case ARM::Q15: return ARM::D30;
3013 }
3014}
3015
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003016/// Parse a register list.
Bill Wendling2063b842010-11-18 23:43:05 +00003017bool ARMAsmParser::
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00003018parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Sean Callanan936b0d32010-01-19 21:44:56 +00003019 assert(Parser.getTok().is(AsmToken::LCurly) &&
Bill Wendling4f4bce02010-11-06 10:48:18 +00003020 "Token is not a Left Curly Brace");
Bill Wendlinge18980a2010-11-06 22:36:58 +00003021 SMLoc S = Parser.getTok().getLoc();
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003022 Parser.Lex(); // Eat '{' token.
3023 SMLoc RegLoc = Parser.getTok().getLoc();
Kevin Enderbya2b99102009-10-09 21:12:28 +00003024
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003025 // Check the first register in the list to see what register class
3026 // this is a list of.
3027 int Reg = tryParseRegister();
3028 if (Reg == -1)
3029 return Error(RegLoc, "register expected");
3030
Jim Grosbach85a23432011-11-11 21:27:40 +00003031 // The reglist instructions have at most 16 registers, so reserve
3032 // space for that many.
Chad Rosierfa705ee2013-07-01 20:49:23 +00003033 int EReg = 0;
3034 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
Jim Grosbach85a23432011-11-11 21:27:40 +00003035
3036 // Allow Q regs and just interpret them as the two D sub-registers.
3037 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3038 Reg = getDRegFromQReg(Reg);
Chad Rosierfa705ee2013-07-01 20:49:23 +00003039 EReg = MRI->getEncodingValue(Reg);
3040 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
Jim Grosbach85a23432011-11-11 21:27:40 +00003041 ++Reg;
3042 }
Benjamin Kramer0d6d0982011-10-22 16:50:00 +00003043 const MCRegisterClass *RC;
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003044 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3045 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3046 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3047 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3048 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3049 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3050 else
3051 return Error(RegLoc, "invalid register in register list");
3052
Jim Grosbach85a23432011-11-11 21:27:40 +00003053 // Store the register.
Chad Rosierfa705ee2013-07-01 20:49:23 +00003054 EReg = MRI->getEncodingValue(Reg);
3055 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
Kevin Enderbya2b99102009-10-09 21:12:28 +00003056
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003057 // This starts immediately after the first register token in the list,
3058 // so we can see either a comma or a minus (range separator) as a legal
3059 // next token.
3060 while (Parser.getTok().is(AsmToken::Comma) ||
3061 Parser.getTok().is(AsmToken::Minus)) {
3062 if (Parser.getTok().is(AsmToken::Minus)) {
Jim Grosbache891fe82011-11-15 23:19:15 +00003063 Parser.Lex(); // Eat the minus.
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003064 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003065 int EndReg = tryParseRegister();
3066 if (EndReg == -1)
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003067 return Error(AfterMinusLoc, "register expected");
Jim Grosbach85a23432011-11-11 21:27:40 +00003068 // Allow Q regs and just interpret them as the two D sub-registers.
3069 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3070 EndReg = getDRegFromQReg(EndReg) + 1;
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003071 // If the register is the same as the start reg, there's nothing
3072 // more to do.
3073 if (Reg == EndReg)
3074 continue;
3075 // The register must be in the same register class as the first.
3076 if (!RC->contains(EndReg))
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003077 return Error(AfterMinusLoc, "invalid register in register list");
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003078 // Ranges must go from low to high.
Eric Christopher6ac277c2012-08-09 22:10:21 +00003079 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003080 return Error(AfterMinusLoc, "bad range in register list");
Kevin Enderbya2b99102009-10-09 21:12:28 +00003081
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003082 // Add all the registers in the range to the register list.
3083 while (Reg != EndReg) {
3084 Reg = getNextRegister(Reg);
Chad Rosierfa705ee2013-07-01 20:49:23 +00003085 EReg = MRI->getEncodingValue(Reg);
3086 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003087 }
3088 continue;
3089 }
3090 Parser.Lex(); // Eat the comma.
3091 RegLoc = Parser.getTok().getLoc();
3092 int OldReg = Reg;
Jim Grosbach98bc7972011-12-08 21:34:20 +00003093 const AsmToken RegTok = Parser.getTok();
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003094 Reg = tryParseRegister();
3095 if (Reg == -1)
Jim Grosbach3337e392011-09-12 23:36:42 +00003096 return Error(RegLoc, "register expected");
Jim Grosbach85a23432011-11-11 21:27:40 +00003097 // Allow Q regs and just interpret them as the two D sub-registers.
3098 bool isQReg = false;
3099 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3100 Reg = getDRegFromQReg(Reg);
3101 isQReg = true;
3102 }
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003103 // The register must be in the same register class as the first.
3104 if (!RC->contains(Reg))
3105 return Error(RegLoc, "invalid register in register list");
3106 // List must be monotonically increasing.
Eric Christopher6ac277c2012-08-09 22:10:21 +00003107 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
Jim Grosbach905686a2012-03-16 20:48:38 +00003108 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3109 Warning(RegLoc, "register list not in ascending order");
3110 else
3111 return Error(RegLoc, "register list not in ascending order");
3112 }
Eric Christopher6ac277c2012-08-09 22:10:21 +00003113 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
Jim Grosbach98bc7972011-12-08 21:34:20 +00003114 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3115 ") in register list");
3116 continue;
3117 }
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003118 // VFP register lists must also be contiguous.
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003119 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3120 Reg != OldReg + 1)
3121 return Error(RegLoc, "non-contiguous register range");
Chad Rosierfa705ee2013-07-01 20:49:23 +00003122 EReg = MRI->getEncodingValue(Reg);
3123 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3124 if (isQReg) {
3125 EReg = MRI->getEncodingValue(++Reg);
3126 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3127 }
Bill Wendlinge18980a2010-11-06 22:36:58 +00003128 }
3129
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003130 if (Parser.getTok().isNot(AsmToken::RCurly))
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003131 return Error(Parser.getTok().getLoc(), "'}' expected");
3132 SMLoc E = Parser.getTok().getEndLoc();
Jim Grosbach3ac26b12011-09-14 18:08:35 +00003133 Parser.Lex(); // Eat '}' token.
3134
Jim Grosbach18bf3632011-12-13 21:48:29 +00003135 // Push the register list operand.
Bill Wendling2063b842010-11-18 23:43:05 +00003136 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
Jim Grosbach18bf3632011-12-13 21:48:29 +00003137
3138 // The ARM system instruction variants for LDM/STM have a '^' token here.
3139 if (Parser.getTok().is(AsmToken::Caret)) {
3140 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3141 Parser.Lex(); // Eat '^' token.
3142 }
3143
Bill Wendling2063b842010-11-18 23:43:05 +00003144 return false;
Kevin Enderbya2b99102009-10-09 21:12:28 +00003145}
3146
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003147// Helper function to parse the lane index for vector lists.
3148ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003149parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
Jim Grosbach04945c42011-12-02 00:35:16 +00003150 Index = 0; // Always return a defined index value.
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003151 if (Parser.getTok().is(AsmToken::LBrac)) {
3152 Parser.Lex(); // Eat the '['.
3153 if (Parser.getTok().is(AsmToken::RBrac)) {
3154 // "Dn[]" is the 'all lanes' syntax.
3155 LaneKind = AllLanes;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003156 EndLoc = Parser.getTok().getEndLoc();
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003157 Parser.Lex(); // Eat the ']'.
3158 return MatchOperand_Success;
3159 }
Jim Grosbach67e76ba2012-03-19 20:39:53 +00003160
3161 // There's an optional '#' token here. Normally there wouldn't be, but
3162 // inline assemble puts one in, and it's friendly to accept that.
3163 if (Parser.getTok().is(AsmToken::Hash))
Amaury de la Vieuvillebac917f2013-06-10 14:17:15 +00003164 Parser.Lex(); // Eat '#' or '$'.
Jim Grosbach67e76ba2012-03-19 20:39:53 +00003165
Jim Grosbach7de7ab82011-12-21 01:19:23 +00003166 const MCExpr *LaneIndex;
3167 SMLoc Loc = Parser.getTok().getLoc();
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003168 if (getParser().parseExpression(LaneIndex)) {
Jim Grosbach7de7ab82011-12-21 01:19:23 +00003169 Error(Loc, "illegal expression");
3170 return MatchOperand_ParseFail;
Jim Grosbach04945c42011-12-02 00:35:16 +00003171 }
Jim Grosbach7de7ab82011-12-21 01:19:23 +00003172 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3173 if (!CE) {
3174 Error(Loc, "lane index must be empty or an integer");
3175 return MatchOperand_ParseFail;
3176 }
3177 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3178 Error(Parser.getTok().getLoc(), "']' expected");
3179 return MatchOperand_ParseFail;
3180 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003181 EndLoc = Parser.getTok().getEndLoc();
Jim Grosbach7de7ab82011-12-21 01:19:23 +00003182 Parser.Lex(); // Eat the ']'.
3183 int64_t Val = CE->getValue();
3184
3185 // FIXME: Make this range check context sensitive for .8, .16, .32.
3186 if (Val < 0 || Val > 7) {
3187 Error(Parser.getTok().getLoc(), "lane index out of range");
3188 return MatchOperand_ParseFail;
3189 }
3190 Index = Val;
3191 LaneKind = IndexedLane;
3192 return MatchOperand_Success;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003193 }
3194 LaneKind = NoLanes;
3195 return MatchOperand_Success;
3196}
3197
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003198// parse a vector register list
3199ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3200parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003201 VectorLaneTy LaneKind;
Jim Grosbach04945c42011-12-02 00:35:16 +00003202 unsigned LaneIndex;
Jim Grosbach8d579232011-11-15 21:45:55 +00003203 SMLoc S = Parser.getTok().getLoc();
3204 // As an extension (to match gas), support a plain D register or Q register
3205 // (without encosing curly braces) as a single or double entry list,
3206 // respectively.
3207 if (Parser.getTok().is(AsmToken::Identifier)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003208 SMLoc E = Parser.getTok().getEndLoc();
Jim Grosbach8d579232011-11-15 21:45:55 +00003209 int Reg = tryParseRegister();
3210 if (Reg == -1)
3211 return MatchOperand_NoMatch;
Jim Grosbach8d579232011-11-15 21:45:55 +00003212 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003213 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003214 if (Res != MatchOperand_Success)
3215 return Res;
3216 switch (LaneKind) {
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003217 case NoLanes:
Jim Grosbach2f50e922011-12-15 21:44:33 +00003218 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003219 break;
3220 case AllLanes:
Jim Grosbachc5af54e2011-12-21 00:38:54 +00003221 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3222 S, E));
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003223 break;
Jim Grosbach04945c42011-12-02 00:35:16 +00003224 case IndexedLane:
3225 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
Jim Grosbach75e2ab52011-12-20 19:21:26 +00003226 LaneIndex,
3227 false, S, E));
Jim Grosbach04945c42011-12-02 00:35:16 +00003228 break;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003229 }
Jim Grosbach8d579232011-11-15 21:45:55 +00003230 return MatchOperand_Success;
3231 }
3232 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3233 Reg = getDRegFromQReg(Reg);
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003234 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003235 if (Res != MatchOperand_Success)
3236 return Res;
3237 switch (LaneKind) {
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003238 case NoLanes:
Jim Grosbachc988e0c2012-03-05 19:33:30 +00003239 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
Jim Grosbach13a292c2012-03-06 22:01:44 +00003240 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
Jim Grosbach2f50e922011-12-15 21:44:33 +00003241 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003242 break;
3243 case AllLanes:
Jim Grosbach13a292c2012-03-06 22:01:44 +00003244 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3245 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
Jim Grosbachc5af54e2011-12-21 00:38:54 +00003246 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3247 S, E));
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003248 break;
Jim Grosbach04945c42011-12-02 00:35:16 +00003249 case IndexedLane:
3250 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
Jim Grosbach75e2ab52011-12-20 19:21:26 +00003251 LaneIndex,
3252 false, S, E));
Jim Grosbach04945c42011-12-02 00:35:16 +00003253 break;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003254 }
Jim Grosbach8d579232011-11-15 21:45:55 +00003255 return MatchOperand_Success;
3256 }
3257 Error(S, "vector register expected");
3258 return MatchOperand_ParseFail;
3259 }
3260
3261 if (Parser.getTok().isNot(AsmToken::LCurly))
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003262 return MatchOperand_NoMatch;
3263
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003264 Parser.Lex(); // Eat '{' token.
3265 SMLoc RegLoc = Parser.getTok().getLoc();
3266
3267 int Reg = tryParseRegister();
3268 if (Reg == -1) {
3269 Error(RegLoc, "register expected");
3270 return MatchOperand_ParseFail;
3271 }
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003272 unsigned Count = 1;
Jim Grosbachc2f16a32011-12-15 21:54:55 +00003273 int Spacing = 0;
Jim Grosbach080a4992011-10-28 00:06:50 +00003274 unsigned FirstReg = Reg;
3275 // The list is of D registers, but we also allow Q regs and just interpret
3276 // them as the two D sub-registers.
3277 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3278 FirstReg = Reg = getDRegFromQReg(Reg);
Jim Grosbach2f50e922011-12-15 21:44:33 +00003279 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3280 // it's ambiguous with four-register single spaced.
Jim Grosbach080a4992011-10-28 00:06:50 +00003281 ++Reg;
3282 ++Count;
3283 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003284
3285 SMLoc E;
3286 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003287 return MatchOperand_ParseFail;
Jim Grosbach080a4992011-10-28 00:06:50 +00003288
Jim Grosbache891fe82011-11-15 23:19:15 +00003289 while (Parser.getTok().is(AsmToken::Comma) ||
3290 Parser.getTok().is(AsmToken::Minus)) {
3291 if (Parser.getTok().is(AsmToken::Minus)) {
Jim Grosbach2f50e922011-12-15 21:44:33 +00003292 if (!Spacing)
3293 Spacing = 1; // Register range implies a single spaced list.
3294 else if (Spacing == 2) {
3295 Error(Parser.getTok().getLoc(),
3296 "sequential registers in double spaced list");
3297 return MatchOperand_ParseFail;
3298 }
Jim Grosbache891fe82011-11-15 23:19:15 +00003299 Parser.Lex(); // Eat the minus.
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003300 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
Jim Grosbache891fe82011-11-15 23:19:15 +00003301 int EndReg = tryParseRegister();
3302 if (EndReg == -1) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003303 Error(AfterMinusLoc, "register expected");
Jim Grosbache891fe82011-11-15 23:19:15 +00003304 return MatchOperand_ParseFail;
3305 }
3306 // Allow Q regs and just interpret them as the two D sub-registers.
3307 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3308 EndReg = getDRegFromQReg(EndReg) + 1;
3309 // If the register is the same as the start reg, there's nothing
3310 // more to do.
3311 if (Reg == EndReg)
3312 continue;
3313 // The register must be in the same register class as the first.
3314 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003315 Error(AfterMinusLoc, "invalid register in register list");
Jim Grosbache891fe82011-11-15 23:19:15 +00003316 return MatchOperand_ParseFail;
3317 }
3318 // Ranges must go from low to high.
3319 if (Reg > EndReg) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003320 Error(AfterMinusLoc, "bad range in register list");
Jim Grosbache891fe82011-11-15 23:19:15 +00003321 return MatchOperand_ParseFail;
3322 }
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003323 // Parse the lane specifier if present.
3324 VectorLaneTy NextLaneKind;
Jim Grosbach04945c42011-12-02 00:35:16 +00003325 unsigned NextLaneIndex;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003326 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3327 MatchOperand_Success)
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003328 return MatchOperand_ParseFail;
Jim Grosbach04945c42011-12-02 00:35:16 +00003329 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003330 Error(AfterMinusLoc, "mismatched lane index in register list");
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003331 return MatchOperand_ParseFail;
3332 }
Jim Grosbache891fe82011-11-15 23:19:15 +00003333
3334 // Add all the registers in the range to the register list.
3335 Count += EndReg - Reg;
3336 Reg = EndReg;
3337 continue;
3338 }
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003339 Parser.Lex(); // Eat the comma.
3340 RegLoc = Parser.getTok().getLoc();
3341 int OldReg = Reg;
3342 Reg = tryParseRegister();
3343 if (Reg == -1) {
3344 Error(RegLoc, "register expected");
3345 return MatchOperand_ParseFail;
3346 }
Jim Grosbach080a4992011-10-28 00:06:50 +00003347 // vector register lists must be contiguous.
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003348 // It's OK to use the enumeration values directly here rather, as the
3349 // VFP register classes have the enum sorted properly.
Jim Grosbach080a4992011-10-28 00:06:50 +00003350 //
3351 // The list is of D registers, but we also allow Q regs and just interpret
3352 // them as the two D sub-registers.
3353 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Jim Grosbach2f50e922011-12-15 21:44:33 +00003354 if (!Spacing)
3355 Spacing = 1; // Register range implies a single spaced list.
3356 else if (Spacing == 2) {
3357 Error(RegLoc,
3358 "invalid register in double-spaced list (must be 'D' register')");
3359 return MatchOperand_ParseFail;
3360 }
Jim Grosbach080a4992011-10-28 00:06:50 +00003361 Reg = getDRegFromQReg(Reg);
3362 if (Reg != OldReg + 1) {
3363 Error(RegLoc, "non-contiguous register range");
3364 return MatchOperand_ParseFail;
3365 }
3366 ++Reg;
3367 Count += 2;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003368 // Parse the lane specifier if present.
3369 VectorLaneTy NextLaneKind;
Jim Grosbach04945c42011-12-02 00:35:16 +00003370 unsigned NextLaneIndex;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003371 SMLoc LaneLoc = Parser.getTok().getLoc();
3372 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3373 MatchOperand_Success)
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003374 return MatchOperand_ParseFail;
Jim Grosbach04945c42011-12-02 00:35:16 +00003375 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003376 Error(LaneLoc, "mismatched lane index in register list");
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003377 return MatchOperand_ParseFail;
3378 }
Jim Grosbach080a4992011-10-28 00:06:50 +00003379 continue;
3380 }
Jim Grosbach2f50e922011-12-15 21:44:33 +00003381 // Normal D register.
3382 // Figure out the register spacing (single or double) of the list if
3383 // we don't know it already.
3384 if (!Spacing)
3385 Spacing = 1 + (Reg == OldReg + 2);
3386
3387 // Just check that it's contiguous and keep going.
3388 if (Reg != OldReg + Spacing) {
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003389 Error(RegLoc, "non-contiguous register range");
3390 return MatchOperand_ParseFail;
3391 }
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003392 ++Count;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003393 // Parse the lane specifier if present.
3394 VectorLaneTy NextLaneKind;
Jim Grosbach04945c42011-12-02 00:35:16 +00003395 unsigned NextLaneIndex;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003396 SMLoc EndLoc = Parser.getTok().getLoc();
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003397 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003398 return MatchOperand_ParseFail;
Jim Grosbach04945c42011-12-02 00:35:16 +00003399 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003400 Error(EndLoc, "mismatched lane index in register list");
3401 return MatchOperand_ParseFail;
3402 }
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003403 }
3404
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003405 if (Parser.getTok().isNot(AsmToken::RCurly)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003406 Error(Parser.getTok().getLoc(), "'}' expected");
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003407 return MatchOperand_ParseFail;
3408 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003409 E = Parser.getTok().getEndLoc();
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003410 Parser.Lex(); // Eat '}' token.
3411
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003412 switch (LaneKind) {
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003413 case NoLanes:
Jim Grosbach13a292c2012-03-06 22:01:44 +00003414 // Two-register operands have been converted to the
Jim Grosbache5307f92012-03-05 21:43:40 +00003415 // composite register classes.
3416 if (Count == 2) {
3417 const MCRegisterClass *RC = (Spacing == 1) ?
3418 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3419 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3420 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3421 }
Jim Grosbachc988e0c2012-03-05 19:33:30 +00003422
Jim Grosbach2f50e922011-12-15 21:44:33 +00003423 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3424 (Spacing == 2), S, E));
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003425 break;
3426 case AllLanes:
Jim Grosbach13a292c2012-03-06 22:01:44 +00003427 // Two-register operands have been converted to the
3428 // composite register classes.
Jim Grosbached428bc2012-03-06 23:10:38 +00003429 if (Count == 2) {
3430 const MCRegisterClass *RC = (Spacing == 1) ?
3431 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3432 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
Jim Grosbach13a292c2012-03-06 22:01:44 +00003433 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3434 }
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003435 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
Jim Grosbachc5af54e2011-12-21 00:38:54 +00003436 (Spacing == 2),
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003437 S, E));
3438 break;
Jim Grosbach04945c42011-12-02 00:35:16 +00003439 case IndexedLane:
3440 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
Jim Grosbach75e2ab52011-12-20 19:21:26 +00003441 LaneIndex,
3442 (Spacing == 2),
3443 S, E));
Jim Grosbach04945c42011-12-02 00:35:16 +00003444 break;
Jim Grosbachcd6f5e72011-11-30 01:09:44 +00003445 }
Jim Grosbachad47cfc2011-10-18 23:02:30 +00003446 return MatchOperand_Success;
3447}
3448
Jim Grosbach2d6ef442011-07-25 20:14:50 +00003449/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
Jim Grosbach861e49c2011-02-12 01:34:40 +00003450ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach2d6ef442011-07-25 20:14:50 +00003451parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00003452 SMLoc S = Parser.getTok().getLoc();
3453 const AsmToken &Tok = Parser.getTok();
Jiangning Liu288e1af2012-08-02 08:21:27 +00003454 unsigned Opt;
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00003455
Jiangning Liu288e1af2012-08-02 08:21:27 +00003456 if (Tok.is(AsmToken::Identifier)) {
3457 StringRef OptStr = Tok.getString();
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00003458
Jiangning Liu288e1af2012-08-02 08:21:27 +00003459 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3460 .Case("sy", ARM_MB::SY)
3461 .Case("st", ARM_MB::ST)
3462 .Case("sh", ARM_MB::ISH)
3463 .Case("ish", ARM_MB::ISH)
3464 .Case("shst", ARM_MB::ISHST)
3465 .Case("ishst", ARM_MB::ISHST)
3466 .Case("nsh", ARM_MB::NSH)
3467 .Case("un", ARM_MB::NSH)
3468 .Case("nshst", ARM_MB::NSHST)
3469 .Case("unst", ARM_MB::NSHST)
3470 .Case("osh", ARM_MB::OSH)
3471 .Case("oshst", ARM_MB::OSHST)
3472 .Default(~0U);
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00003473
Jiangning Liu288e1af2012-08-02 08:21:27 +00003474 if (Opt == ~0U)
3475 return MatchOperand_NoMatch;
3476
3477 Parser.Lex(); // Eat identifier token.
3478 } else if (Tok.is(AsmToken::Hash) ||
3479 Tok.is(AsmToken::Dollar) ||
3480 Tok.is(AsmToken::Integer)) {
3481 if (Parser.getTok().isNot(AsmToken::Integer))
Amaury de la Vieuvillebac917f2013-06-10 14:17:15 +00003482 Parser.Lex(); // Eat '#' or '$'.
Jiangning Liu288e1af2012-08-02 08:21:27 +00003483 SMLoc Loc = Parser.getTok().getLoc();
3484
3485 const MCExpr *MemBarrierID;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003486 if (getParser().parseExpression(MemBarrierID)) {
Jiangning Liu288e1af2012-08-02 08:21:27 +00003487 Error(Loc, "illegal expression");
3488 return MatchOperand_ParseFail;
3489 }
3490
3491 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3492 if (!CE) {
3493 Error(Loc, "constant expression expected");
3494 return MatchOperand_ParseFail;
3495 }
3496
3497 int Val = CE->getValue();
3498 if (Val & ~0xf) {
3499 Error(Loc, "immediate value out of range");
3500 return MatchOperand_ParseFail;
3501 }
3502
3503 Opt = ARM_MB::RESERVED_0 + Val;
3504 } else
3505 return MatchOperand_ParseFail;
3506
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00003507 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
Jim Grosbach861e49c2011-02-12 01:34:40 +00003508 return MatchOperand_Success;
Bruno Cardoso Lopes36dd43f2011-02-07 22:09:15 +00003509}
3510
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00003511/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3512ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3513parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3514 SMLoc S = Parser.getTok().getLoc();
3515 const AsmToken &Tok = Parser.getTok();
3516 unsigned Opt;
3517
3518 if (Tok.is(AsmToken::Identifier)) {
3519 StringRef OptStr = Tok.getString();
3520
3521 if (OptStr.lower() == "sy")
3522 Opt = ARM_ISB::SY;
3523 else
3524 return MatchOperand_NoMatch;
3525
3526 Parser.Lex(); // Eat identifier token.
3527 } else if (Tok.is(AsmToken::Hash) ||
3528 Tok.is(AsmToken::Dollar) ||
3529 Tok.is(AsmToken::Integer)) {
3530 if (Parser.getTok().isNot(AsmToken::Integer))
Amaury de la Vieuvillebac917f2013-06-10 14:17:15 +00003531 Parser.Lex(); // Eat '#' or '$'.
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00003532 SMLoc Loc = Parser.getTok().getLoc();
3533
3534 const MCExpr *ISBarrierID;
3535 if (getParser().parseExpression(ISBarrierID)) {
3536 Error(Loc, "illegal expression");
3537 return MatchOperand_ParseFail;
3538 }
3539
3540 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3541 if (!CE) {
3542 Error(Loc, "constant expression expected");
3543 return MatchOperand_ParseFail;
3544 }
3545
3546 int Val = CE->getValue();
3547 if (Val & ~0xf) {
3548 Error(Loc, "immediate value out of range");
3549 return MatchOperand_ParseFail;
3550 }
3551
3552 Opt = ARM_ISB::RESERVED_0 + Val;
3553 } else
3554 return MatchOperand_ParseFail;
3555
3556 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3557 (ARM_ISB::InstSyncBOpt)Opt, S));
3558 return MatchOperand_Success;
3559}
3560
3561
Jim Grosbach2d6ef442011-07-25 20:14:50 +00003562/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00003563ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach2d6ef442011-07-25 20:14:50 +00003564parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00003565 SMLoc S = Parser.getTok().getLoc();
3566 const AsmToken &Tok = Parser.getTok();
Richard Bartonb0ec3752012-06-14 10:48:04 +00003567 if (!Tok.is(AsmToken::Identifier))
3568 return MatchOperand_NoMatch;
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00003569 StringRef IFlagsStr = Tok.getString();
3570
Owen Anderson10c5b122011-10-05 17:16:40 +00003571 // An iflags string of "none" is interpreted to mean that none of the AIF
3572 // bits are set. Not a terribly useful instruction, but a valid encoding.
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00003573 unsigned IFlags = 0;
Owen Anderson10c5b122011-10-05 17:16:40 +00003574 if (IFlagsStr != "none") {
3575 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3576 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3577 .Case("a", ARM_PROC::A)
3578 .Case("i", ARM_PROC::I)
3579 .Case("f", ARM_PROC::F)
3580 .Default(~0U);
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00003581
Owen Anderson10c5b122011-10-05 17:16:40 +00003582 // If some specific iflag is already set, it means that some letter is
3583 // present more than once, this is not acceptable.
3584 if (Flag == ~0U || (IFlags & Flag))
3585 return MatchOperand_NoMatch;
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00003586
Owen Anderson10c5b122011-10-05 17:16:40 +00003587 IFlags |= Flag;
3588 }
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00003589 }
3590
3591 Parser.Lex(); // Eat identifier token.
3592 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3593 return MatchOperand_Success;
3594}
3595
Jim Grosbach2d6ef442011-07-25 20:14:50 +00003596/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003597ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach2d6ef442011-07-25 20:14:50 +00003598parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003599 SMLoc S = Parser.getTok().getLoc();
3600 const AsmToken &Tok = Parser.getTok();
Craig Toppera004b0d2012-10-09 04:55:28 +00003601 if (!Tok.is(AsmToken::Identifier))
3602 return MatchOperand_NoMatch;
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003603 StringRef Mask = Tok.getString();
3604
James Molloy21efa7d2011-09-28 14:21:38 +00003605 if (isMClass()) {
3606 // See ARMv6-M 10.1.1
Jim Grosbachd28888d2012-03-15 21:34:14 +00003607 std::string Name = Mask.lower();
3608 unsigned FlagsVal = StringSwitch<unsigned>(Name)
Kevin Enderbyf1b225d2012-05-17 22:18:01 +00003609 // Note: in the documentation:
3610 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3611 // for MSR APSR_nzcvq.
3612 // but we do make it an alias here. This is so to get the "mask encoding"
3613 // bits correct on MSR APSR writes.
3614 //
3615 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3616 // should really only be allowed when writing a special register. Note
3617 // they get dropped in the MRS instruction reading a special register as
3618 // the SYSm field is only 8 bits.
3619 //
3620 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3621 // includes the DSP extension but that is not checked.
3622 .Case("apsr", 0x800)
3623 .Case("apsr_nzcvq", 0x800)
3624 .Case("apsr_g", 0x400)
3625 .Case("apsr_nzcvqg", 0xc00)
3626 .Case("iapsr", 0x801)
3627 .Case("iapsr_nzcvq", 0x801)
3628 .Case("iapsr_g", 0x401)
3629 .Case("iapsr_nzcvqg", 0xc01)
3630 .Case("eapsr", 0x802)
3631 .Case("eapsr_nzcvq", 0x802)
3632 .Case("eapsr_g", 0x402)
3633 .Case("eapsr_nzcvqg", 0xc02)
3634 .Case("xpsr", 0x803)
3635 .Case("xpsr_nzcvq", 0x803)
3636 .Case("xpsr_g", 0x403)
3637 .Case("xpsr_nzcvqg", 0xc03)
Kevin Enderby6c7279e2012-06-15 22:14:44 +00003638 .Case("ipsr", 0x805)
3639 .Case("epsr", 0x806)
3640 .Case("iepsr", 0x807)
3641 .Case("msp", 0x808)
3642 .Case("psp", 0x809)
3643 .Case("primask", 0x810)
3644 .Case("basepri", 0x811)
3645 .Case("basepri_max", 0x812)
3646 .Case("faultmask", 0x813)
3647 .Case("control", 0x814)
James Molloy21efa7d2011-09-28 14:21:38 +00003648 .Default(~0U);
Jim Grosbach3794d822011-12-22 17:17:10 +00003649
James Molloy21efa7d2011-09-28 14:21:38 +00003650 if (FlagsVal == ~0U)
3651 return MatchOperand_NoMatch;
3652
Kevin Enderby6c7279e2012-06-15 22:14:44 +00003653 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
James Molloy21efa7d2011-09-28 14:21:38 +00003654 // basepri, basepri_max and faultmask only valid for V7m.
3655 return MatchOperand_NoMatch;
Jim Grosbach3794d822011-12-22 17:17:10 +00003656
James Molloy21efa7d2011-09-28 14:21:38 +00003657 Parser.Lex(); // Eat identifier token.
3658 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3659 return MatchOperand_Success;
3660 }
3661
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003662 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3663 size_t Start = 0, Next = Mask.find('_');
3664 StringRef Flags = "";
Benjamin Kramer20baffb2011-11-06 20:37:06 +00003665 std::string SpecReg = Mask.slice(Start, Next).lower();
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003666 if (Next != StringRef::npos)
3667 Flags = Mask.slice(Next+1, Mask.size());
3668
3669 // FlagsVal contains the complete mask:
3670 // 3-0: Mask
3671 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3672 unsigned FlagsVal = 0;
3673
3674 if (SpecReg == "apsr") {
3675 FlagsVal = StringSwitch<unsigned>(Flags)
Jim Grosbachd25c2cd2011-07-19 22:45:10 +00003676 .Case("nzcvq", 0x8) // same as CPSR_f
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003677 .Case("g", 0x4) // same as CPSR_s
3678 .Case("nzcvqg", 0xc) // same as CPSR_fs
3679 .Default(~0U);
3680
Joerg Sonnenberger740467a2011-02-19 00:43:45 +00003681 if (FlagsVal == ~0U) {
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003682 if (!Flags.empty())
3683 return MatchOperand_NoMatch;
3684 else
Jim Grosbach0ecd3952011-09-14 20:03:46 +00003685 FlagsVal = 8; // No flag
Joerg Sonnenberger740467a2011-02-19 00:43:45 +00003686 }
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003687 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
Jim Grosbach3d00eec2012-04-05 03:17:53 +00003688 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3689 if (Flags == "all" || Flags == "")
Bruno Cardoso Lopes54452132011-05-25 00:35:03 +00003690 Flags = "fc";
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003691 for (int i = 0, e = Flags.size(); i != e; ++i) {
3692 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3693 .Case("c", 1)
3694 .Case("x", 2)
3695 .Case("s", 4)
3696 .Case("f", 8)
3697 .Default(~0U);
3698
3699 // If some specific flag is already set, it means that some letter is
3700 // present more than once, this is not acceptable.
3701 if (FlagsVal == ~0U || (FlagsVal & Flag))
3702 return MatchOperand_NoMatch;
3703 FlagsVal |= Flag;
3704 }
3705 } else // No match for special register.
3706 return MatchOperand_NoMatch;
3707
Owen Anderson03a173e2011-10-21 18:43:28 +00003708 // Special register without flags is NOT equivalent to "fc" flags.
3709 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3710 // two lines would enable gas compatibility at the expense of breaking
3711 // round-tripping.
3712 //
3713 // if (!FlagsVal)
3714 // FlagsVal = 0x9;
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +00003715
3716 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3717 if (SpecReg == "spsr")
3718 FlagsVal |= 16;
3719
3720 Parser.Lex(); // Eat identifier token.
3721 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3722 return MatchOperand_Success;
3723}
3724
Jim Grosbach27c1e252011-07-21 17:23:04 +00003725ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3726parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3727 int Low, int High) {
3728 const AsmToken &Tok = Parser.getTok();
3729 if (Tok.isNot(AsmToken::Identifier)) {
3730 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3731 return MatchOperand_ParseFail;
3732 }
3733 StringRef ShiftName = Tok.getString();
Benjamin Kramer20baffb2011-11-06 20:37:06 +00003734 std::string LowerOp = Op.lower();
3735 std::string UpperOp = Op.upper();
Jim Grosbach27c1e252011-07-21 17:23:04 +00003736 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3737 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3738 return MatchOperand_ParseFail;
3739 }
3740 Parser.Lex(); // Eat shift type token.
3741
3742 // There must be a '#' and a shift amount.
Jim Grosbachef70e9b2011-12-09 22:25:03 +00003743 if (Parser.getTok().isNot(AsmToken::Hash) &&
3744 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach27c1e252011-07-21 17:23:04 +00003745 Error(Parser.getTok().getLoc(), "'#' expected");
3746 return MatchOperand_ParseFail;
3747 }
3748 Parser.Lex(); // Eat hash token.
3749
3750 const MCExpr *ShiftAmount;
3751 SMLoc Loc = Parser.getTok().getLoc();
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003752 SMLoc EndLoc;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003753 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
Jim Grosbach27c1e252011-07-21 17:23:04 +00003754 Error(Loc, "illegal expression");
3755 return MatchOperand_ParseFail;
3756 }
3757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3758 if (!CE) {
3759 Error(Loc, "constant expression expected");
3760 return MatchOperand_ParseFail;
3761 }
3762 int Val = CE->getValue();
3763 if (Val < Low || Val > High) {
3764 Error(Loc, "immediate value out of range");
3765 return MatchOperand_ParseFail;
3766 }
3767
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003768 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
Jim Grosbach27c1e252011-07-21 17:23:04 +00003769
3770 return MatchOperand_Success;
3771}
3772
Jim Grosbach0a547702011-07-22 17:44:50 +00003773ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3774parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3775 const AsmToken &Tok = Parser.getTok();
3776 SMLoc S = Tok.getLoc();
3777 if (Tok.isNot(AsmToken::Identifier)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003778 Error(S, "'be' or 'le' operand expected");
Jim Grosbach0a547702011-07-22 17:44:50 +00003779 return MatchOperand_ParseFail;
3780 }
Tim Northover4d141442013-05-31 15:58:45 +00003781 int Val = StringSwitch<int>(Tok.getString().lower())
Jim Grosbach0a547702011-07-22 17:44:50 +00003782 .Case("be", 1)
3783 .Case("le", 0)
3784 .Default(-1);
3785 Parser.Lex(); // Eat the token.
3786
3787 if (Val == -1) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003788 Error(S, "'be' or 'le' operand expected");
Jim Grosbach0a547702011-07-22 17:44:50 +00003789 return MatchOperand_ParseFail;
3790 }
3791 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3792 getContext()),
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003793 S, Tok.getEndLoc()));
Jim Grosbach0a547702011-07-22 17:44:50 +00003794 return MatchOperand_Success;
3795}
3796
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003797/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3798/// instructions. Legal values are:
3799/// lsl #n 'n' in [0,31]
3800/// asr #n 'n' in [1,32]
3801/// n == 32 encoded as n == 0.
3802ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3803parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3804 const AsmToken &Tok = Parser.getTok();
3805 SMLoc S = Tok.getLoc();
3806 if (Tok.isNot(AsmToken::Identifier)) {
3807 Error(S, "shift operator 'asr' or 'lsl' expected");
3808 return MatchOperand_ParseFail;
3809 }
3810 StringRef ShiftName = Tok.getString();
3811 bool isASR;
3812 if (ShiftName == "lsl" || ShiftName == "LSL")
3813 isASR = false;
3814 else if (ShiftName == "asr" || ShiftName == "ASR")
3815 isASR = true;
3816 else {
3817 Error(S, "shift operator 'asr' or 'lsl' expected");
3818 return MatchOperand_ParseFail;
3819 }
3820 Parser.Lex(); // Eat the operator.
3821
3822 // A '#' and a shift amount.
Jim Grosbachef70e9b2011-12-09 22:25:03 +00003823 if (Parser.getTok().isNot(AsmToken::Hash) &&
3824 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003825 Error(Parser.getTok().getLoc(), "'#' expected");
3826 return MatchOperand_ParseFail;
3827 }
3828 Parser.Lex(); // Eat hash token.
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003829 SMLoc ExLoc = Parser.getTok().getLoc();
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003830
3831 const MCExpr *ShiftAmount;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003832 SMLoc EndLoc;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003833 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003834 Error(ExLoc, "malformed shift expression");
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003835 return MatchOperand_ParseFail;
3836 }
3837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3838 if (!CE) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003839 Error(ExLoc, "shift amount must be an immediate");
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003840 return MatchOperand_ParseFail;
3841 }
3842
3843 int64_t Val = CE->getValue();
3844 if (isASR) {
3845 // Shift amount must be in [1,32]
3846 if (Val < 1 || Val > 32) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003847 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003848 return MatchOperand_ParseFail;
3849 }
Owen Andersonf01e2de2011-09-26 21:06:22 +00003850 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3851 if (isThumb() && Val == 32) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003852 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
Owen Andersonf01e2de2011-09-26 21:06:22 +00003853 return MatchOperand_ParseFail;
3854 }
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003855 if (Val == 32) Val = 0;
3856 } else {
3857 // Shift amount must be in [1,32]
3858 if (Val < 0 || Val > 31) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003859 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003860 return MatchOperand_ParseFail;
3861 }
3862 }
3863
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003864 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
Jim Grosbach3a9cbee2011-07-25 22:20:28 +00003865
3866 return MatchOperand_Success;
3867}
3868
Jim Grosbach833b9d32011-07-27 20:15:40 +00003869/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3870/// of instructions. Legal values are:
3871/// ror #n 'n' in {0, 8, 16, 24}
3872ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3873parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3874 const AsmToken &Tok = Parser.getTok();
3875 SMLoc S = Tok.getLoc();
Jim Grosbach82213192011-09-19 20:29:33 +00003876 if (Tok.isNot(AsmToken::Identifier))
3877 return MatchOperand_NoMatch;
Jim Grosbach833b9d32011-07-27 20:15:40 +00003878 StringRef ShiftName = Tok.getString();
Jim Grosbach82213192011-09-19 20:29:33 +00003879 if (ShiftName != "ror" && ShiftName != "ROR")
3880 return MatchOperand_NoMatch;
Jim Grosbach833b9d32011-07-27 20:15:40 +00003881 Parser.Lex(); // Eat the operator.
3882
3883 // A '#' and a rotate amount.
Jim Grosbachef70e9b2011-12-09 22:25:03 +00003884 if (Parser.getTok().isNot(AsmToken::Hash) &&
3885 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach833b9d32011-07-27 20:15:40 +00003886 Error(Parser.getTok().getLoc(), "'#' expected");
3887 return MatchOperand_ParseFail;
3888 }
3889 Parser.Lex(); // Eat hash token.
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003890 SMLoc ExLoc = Parser.getTok().getLoc();
Jim Grosbach833b9d32011-07-27 20:15:40 +00003891
3892 const MCExpr *ShiftAmount;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003893 SMLoc EndLoc;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003894 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003895 Error(ExLoc, "malformed rotate expression");
Jim Grosbach833b9d32011-07-27 20:15:40 +00003896 return MatchOperand_ParseFail;
3897 }
3898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3899 if (!CE) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003900 Error(ExLoc, "rotate amount must be an immediate");
Jim Grosbach833b9d32011-07-27 20:15:40 +00003901 return MatchOperand_ParseFail;
3902 }
3903
3904 int64_t Val = CE->getValue();
3905 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3906 // normally, zero is represented in asm by omitting the rotate operand
3907 // entirely.
3908 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003909 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
Jim Grosbach833b9d32011-07-27 20:15:40 +00003910 return MatchOperand_ParseFail;
3911 }
3912
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003913 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
Jim Grosbach833b9d32011-07-27 20:15:40 +00003914
3915 return MatchOperand_Success;
3916}
3917
Jim Grosbach864b6092011-07-28 21:34:26 +00003918ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3919parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3920 SMLoc S = Parser.getTok().getLoc();
3921 // The bitfield descriptor is really two operands, the LSB and the width.
Jim Grosbachef70e9b2011-12-09 22:25:03 +00003922 if (Parser.getTok().isNot(AsmToken::Hash) &&
3923 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach864b6092011-07-28 21:34:26 +00003924 Error(Parser.getTok().getLoc(), "'#' expected");
3925 return MatchOperand_ParseFail;
3926 }
3927 Parser.Lex(); // Eat hash token.
3928
3929 const MCExpr *LSBExpr;
3930 SMLoc E = Parser.getTok().getLoc();
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003931 if (getParser().parseExpression(LSBExpr)) {
Jim Grosbach864b6092011-07-28 21:34:26 +00003932 Error(E, "malformed immediate expression");
3933 return MatchOperand_ParseFail;
3934 }
3935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3936 if (!CE) {
3937 Error(E, "'lsb' operand must be an immediate");
3938 return MatchOperand_ParseFail;
3939 }
3940
3941 int64_t LSB = CE->getValue();
3942 // The LSB must be in the range [0,31]
3943 if (LSB < 0 || LSB > 31) {
3944 Error(E, "'lsb' operand must be in the range [0,31]");
3945 return MatchOperand_ParseFail;
3946 }
3947 E = Parser.getTok().getLoc();
3948
3949 // Expect another immediate operand.
3950 if (Parser.getTok().isNot(AsmToken::Comma)) {
3951 Error(Parser.getTok().getLoc(), "too few operands");
3952 return MatchOperand_ParseFail;
3953 }
3954 Parser.Lex(); // Eat hash token.
Jim Grosbachef70e9b2011-12-09 22:25:03 +00003955 if (Parser.getTok().isNot(AsmToken::Hash) &&
3956 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach864b6092011-07-28 21:34:26 +00003957 Error(Parser.getTok().getLoc(), "'#' expected");
3958 return MatchOperand_ParseFail;
3959 }
3960 Parser.Lex(); // Eat hash token.
3961
3962 const MCExpr *WidthExpr;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003963 SMLoc EndLoc;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003964 if (getParser().parseExpression(WidthExpr, EndLoc)) {
Jim Grosbach864b6092011-07-28 21:34:26 +00003965 Error(E, "malformed immediate expression");
3966 return MatchOperand_ParseFail;
3967 }
3968 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3969 if (!CE) {
3970 Error(E, "'width' operand must be an immediate");
3971 return MatchOperand_ParseFail;
3972 }
3973
3974 int64_t Width = CE->getValue();
3975 // The LSB must be in the range [1,32-lsb]
3976 if (Width < 1 || Width > 32 - LSB) {
3977 Error(E, "'width' operand must be in the range [1,32-lsb]");
3978 return MatchOperand_ParseFail;
3979 }
Jim Grosbach864b6092011-07-28 21:34:26 +00003980
Jordan Rosee8f1eae2013-01-07 19:00:49 +00003981 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
Jim Grosbach864b6092011-07-28 21:34:26 +00003982
3983 return MatchOperand_Success;
3984}
3985
Jim Grosbachd3595712011-08-03 23:50:40 +00003986ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3987parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3988 // Check for a post-index addressing register operand. Specifically:
Jim Grosbachc320c852011-08-05 21:28:30 +00003989 // postidx_reg := '+' register {, shift}
3990 // | '-' register {, shift}
3991 // | register {, shift}
Jim Grosbachd3595712011-08-03 23:50:40 +00003992
3993 // This method must return MatchOperand_NoMatch without consuming any tokens
3994 // in the case where there is no match, as other alternatives take other
3995 // parse methods.
3996 AsmToken Tok = Parser.getTok();
3997 SMLoc S = Tok.getLoc();
3998 bool haveEaten = false;
Jim Grosbacha70fbfd52011-08-05 16:11:38 +00003999 bool isAdd = true;
Jim Grosbachd3595712011-08-03 23:50:40 +00004000 if (Tok.is(AsmToken::Plus)) {
4001 Parser.Lex(); // Eat the '+' token.
4002 haveEaten = true;
4003 } else if (Tok.is(AsmToken::Minus)) {
4004 Parser.Lex(); // Eat the '-' token.
Jim Grosbacha70fbfd52011-08-05 16:11:38 +00004005 isAdd = false;
Jim Grosbachd3595712011-08-03 23:50:40 +00004006 haveEaten = true;
4007 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004008
4009 SMLoc E = Parser.getTok().getEndLoc();
4010 int Reg = tryParseRegister();
Jim Grosbachd3595712011-08-03 23:50:40 +00004011 if (Reg == -1) {
4012 if (!haveEaten)
4013 return MatchOperand_NoMatch;
4014 Error(Parser.getTok().getLoc(), "register expected");
4015 return MatchOperand_ParseFail;
4016 }
Jim Grosbachd3595712011-08-03 23:50:40 +00004017
Jim Grosbachc320c852011-08-05 21:28:30 +00004018 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4019 unsigned ShiftImm = 0;
Jim Grosbach3d0b3a32011-08-05 22:03:36 +00004020 if (Parser.getTok().is(AsmToken::Comma)) {
4021 Parser.Lex(); // Eat the ','.
4022 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4023 return MatchOperand_ParseFail;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004024
4025 // FIXME: Only approximates end...may include intervening whitespace.
4026 E = Parser.getTok().getLoc();
Jim Grosbach3d0b3a32011-08-05 22:03:36 +00004027 }
Jim Grosbachc320c852011-08-05 21:28:30 +00004028
4029 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4030 ShiftImm, S, E));
Jim Grosbachd3595712011-08-03 23:50:40 +00004031
4032 return MatchOperand_Success;
4033}
4034
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004035ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4036parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4037 // Check for a post-index addressing register operand. Specifically:
4038 // am3offset := '+' register
4039 // | '-' register
4040 // | register
4041 // | # imm
4042 // | # + imm
4043 // | # - imm
4044
4045 // This method must return MatchOperand_NoMatch without consuming any tokens
4046 // in the case where there is no match, as other alternatives take other
4047 // parse methods.
4048 AsmToken Tok = Parser.getTok();
4049 SMLoc S = Tok.getLoc();
4050
4051 // Do immediates first, as we always parse those if we have a '#'.
Jim Grosbachef70e9b2011-12-09 22:25:03 +00004052 if (Parser.getTok().is(AsmToken::Hash) ||
4053 Parser.getTok().is(AsmToken::Dollar)) {
Amaury de la Vieuvillebac917f2013-06-10 14:17:15 +00004054 Parser.Lex(); // Eat '#' or '$'.
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004055 // Explicitly look for a '-', as we need to encode negative zero
4056 // differently.
4057 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4058 const MCExpr *Offset;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004059 SMLoc E;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004060 if (getParser().parseExpression(Offset, E))
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004061 return MatchOperand_ParseFail;
4062 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4063 if (!CE) {
4064 Error(S, "constant expression expected");
4065 return MatchOperand_ParseFail;
4066 }
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004067 // Negative zero is encoded as the flag value INT32_MIN.
4068 int32_t Val = CE->getValue();
4069 if (isNegative && Val == 0)
4070 Val = INT32_MIN;
4071
4072 Operands.push_back(
4073 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4074
4075 return MatchOperand_Success;
4076 }
4077
4078
4079 bool haveEaten = false;
4080 bool isAdd = true;
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004081 if (Tok.is(AsmToken::Plus)) {
4082 Parser.Lex(); // Eat the '+' token.
4083 haveEaten = true;
4084 } else if (Tok.is(AsmToken::Minus)) {
4085 Parser.Lex(); // Eat the '-' token.
4086 isAdd = false;
4087 haveEaten = true;
4088 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004089
4090 Tok = Parser.getTok();
4091 int Reg = tryParseRegister();
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004092 if (Reg == -1) {
4093 if (!haveEaten)
4094 return MatchOperand_NoMatch;
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004095 Error(Tok.getLoc(), "register expected");
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004096 return MatchOperand_ParseFail;
4097 }
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004098
4099 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004100 0, S, Tok.getEndLoc()));
Jim Grosbach1d9d5e92011-08-10 21:56:18 +00004101
4102 return MatchOperand_Success;
4103}
4104
Tim Northovereb5e4d52013-07-22 09:06:12 +00004105/// Convert parsed operands to MCInst. Needed here because this instruction
4106/// only has two register operands, but multiplication is commutative so
4107/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
Chad Rosier98cfa102012-08-31 00:03:31 +00004108void ARMAsmParser::
Chad Rosier451ef132012-08-31 22:12:31 +00004109cvtThumbMultiply(MCInst &Inst,
Jim Grosbach8e048492011-08-19 22:07:46 +00004110 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbach8e048492011-08-19 22:07:46 +00004111 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4112 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
Jim Grosbach5a5ce632011-11-10 22:10:12 +00004113 // If we have a three-operand form, make sure to set Rn to be the operand
4114 // that isn't the same as Rd.
4115 unsigned RegOp = 4;
4116 if (Operands.size() == 6 &&
4117 ((ARMOperand*)Operands[4])->getReg() ==
4118 ((ARMOperand*)Operands[3])->getReg())
4119 RegOp = 5;
4120 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4121 Inst.addOperand(Inst.getOperand(0));
Jim Grosbach8e048492011-08-19 22:07:46 +00004122 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
Jim Grosbach8e048492011-08-19 22:07:46 +00004123}
Jim Grosbachcd4dd252011-08-10 22:42:16 +00004124
Mihai Popaad18d3c2013-08-09 10:38:32 +00004125void ARMAsmParser::
4126cvtThumbBranches(MCInst &Inst,
4127 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4128 int CondOp = -1, ImmOp = -1;
4129 switch(Inst.getOpcode()) {
4130 case ARM::tB:
4131 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4132
4133 case ARM::t2B:
4134 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4135
4136 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4137 }
4138 // first decide whether or not the branch should be conditional
4139 // by looking at it's location relative to an IT block
4140 if(inITBlock()) {
4141 // inside an IT block we cannot have any conditional branches. any
4142 // such instructions needs to be converted to unconditional form
4143 switch(Inst.getOpcode()) {
4144 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4145 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4146 }
4147 } else {
4148 // outside IT blocks we can only have unconditional branches with AL
4149 // condition code or conditional branches with non-AL condition code
4150 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4151 switch(Inst.getOpcode()) {
4152 case ARM::tB:
4153 case ARM::tBcc:
4154 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4155 break;
4156 case ARM::t2B:
4157 case ARM::t2Bcc:
4158 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4159 break;
4160 }
4161 }
4162
4163 // now decide on encoding size based on branch target range
4164 switch(Inst.getOpcode()) {
4165 // classify tB as either t2B or t1B based on range of immediate operand
4166 case ARM::tB: {
4167 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4168 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4169 Inst.setOpcode(ARM::t2B);
4170 break;
4171 }
4172 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4173 case ARM::tBcc: {
4174 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4175 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4176 Inst.setOpcode(ARM::t2Bcc);
4177 break;
4178 }
4179 }
4180 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4181 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4182}
4183
Bill Wendlinge18980a2010-11-06 22:36:58 +00004184/// Parse an ARM memory expression, return false if successful else return true
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004185/// or an error. The first token must be a '[' when called.
Bill Wendling2063b842010-11-18 23:43:05 +00004186bool ARMAsmParser::
Jim Grosbachd3595712011-08-03 23:50:40 +00004187parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Sean Callanan7ad0ad02010-04-02 22:27:05 +00004188 SMLoc S, E;
Sean Callanan936b0d32010-01-19 21:44:56 +00004189 assert(Parser.getTok().is(AsmToken::LBrac) &&
Bill Wendling4f4bce02010-11-06 10:48:18 +00004190 "Token is not a Left Bracket");
Sean Callanan7ad0ad02010-04-02 22:27:05 +00004191 S = Parser.getTok().getLoc();
Sean Callanana83fd7d2010-01-19 20:27:46 +00004192 Parser.Lex(); // Eat left bracket token.
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004193
Sean Callanan936b0d32010-01-19 21:44:56 +00004194 const AsmToken &BaseRegTok = Parser.getTok();
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004195 int BaseRegNum = tryParseRegister();
Jim Grosbachd3595712011-08-03 23:50:40 +00004196 if (BaseRegNum == -1)
4197 return Error(BaseRegTok.getLoc(), "register expected");
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004198
Kristof Beyls2efb59a2013-02-14 14:46:12 +00004199 // The next token must either be a comma, a colon or a closing bracket.
Daniel Dunbar1d5e9542011-01-18 05:34:17 +00004200 const AsmToken &Tok = Parser.getTok();
Kristof Beyls2efb59a2013-02-14 14:46:12 +00004201 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4202 !Tok.is(AsmToken::RBrac))
Jim Grosbachd3595712011-08-03 23:50:40 +00004203 return Error(Tok.getLoc(), "malformed memory operand");
Daniel Dunbar1d5e9542011-01-18 05:34:17 +00004204
Jim Grosbachd3595712011-08-03 23:50:40 +00004205 if (Tok.is(AsmToken::RBrac)) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004206 E = Tok.getEndLoc();
Sean Callanana83fd7d2010-01-19 20:27:46 +00004207 Parser.Lex(); // Eat right bracket token.
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004208
Jim Grosbachd3595712011-08-03 23:50:40 +00004209 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
Jim Grosbacha95ec992011-10-11 17:29:55 +00004210 0, 0, false, S, E));
Jim Grosbach32ff5582010-11-29 23:18:01 +00004211
Jim Grosbach40700e02011-09-19 18:42:21 +00004212 // If there's a pre-indexing writeback marker, '!', just add it as a token
4213 // operand. It's rather odd, but syntactically valid.
4214 if (Parser.getTok().is(AsmToken::Exclaim)) {
4215 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4216 Parser.Lex(); // Eat the '!'.
4217 }
4218
Jim Grosbachd3595712011-08-03 23:50:40 +00004219 return false;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004220 }
Daniel Dunbarf5164f42011-01-18 05:34:24 +00004221
Kristof Beyls2efb59a2013-02-14 14:46:12 +00004222 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4223 "Lost colon or comma in memory operand?!");
4224 if (Tok.is(AsmToken::Comma)) {
4225 Parser.Lex(); // Eat the comma.
4226 }
Daniel Dunbarf5164f42011-01-18 05:34:24 +00004227
Jim Grosbacha95ec992011-10-11 17:29:55 +00004228 // If we have a ':', it's an alignment specifier.
4229 if (Parser.getTok().is(AsmToken::Colon)) {
4230 Parser.Lex(); // Eat the ':'.
4231 E = Parser.getTok().getLoc();
4232
4233 const MCExpr *Expr;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004234 if (getParser().parseExpression(Expr))
Jim Grosbacha95ec992011-10-11 17:29:55 +00004235 return true;
4236
4237 // The expression has to be a constant. Memory references with relocations
4238 // don't come through here, as they use the <label> forms of the relevant
4239 // instructions.
4240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4241 if (!CE)
4242 return Error (E, "constant expression expected");
4243
4244 unsigned Align = 0;
4245 switch (CE->getValue()) {
4246 default:
Jim Grosbachcef98cd2011-12-19 18:31:43 +00004247 return Error(E,
4248 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4249 case 16: Align = 2; break;
4250 case 32: Align = 4; break;
Jim Grosbacha95ec992011-10-11 17:29:55 +00004251 case 64: Align = 8; break;
4252 case 128: Align = 16; break;
4253 case 256: Align = 32; break;
4254 }
4255
4256 // Now we should have the closing ']'
Jim Grosbacha95ec992011-10-11 17:29:55 +00004257 if (Parser.getTok().isNot(AsmToken::RBrac))
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004258 return Error(Parser.getTok().getLoc(), "']' expected");
4259 E = Parser.getTok().getEndLoc();
Jim Grosbacha95ec992011-10-11 17:29:55 +00004260 Parser.Lex(); // Eat right bracket token.
4261
4262 // Don't worry about range checking the value here. That's handled by
4263 // the is*() predicates.
4264 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4265 ARM_AM::no_shift, 0, Align,
4266 false, S, E));
4267
4268 // If there's a pre-indexing writeback marker, '!', just add it as a token
4269 // operand.
4270 if (Parser.getTok().is(AsmToken::Exclaim)) {
4271 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4272 Parser.Lex(); // Eat the '!'.
4273 }
4274
4275 return false;
4276 }
4277
4278 // If we have a '#', it's an immediate offset, else assume it's a register
Jim Grosbach8279c182011-11-15 22:14:41 +00004279 // offset. Be friendly and also accept a plain integer (without a leading
4280 // hash) for gas compatibility.
4281 if (Parser.getTok().is(AsmToken::Hash) ||
Jim Grosbachef70e9b2011-12-09 22:25:03 +00004282 Parser.getTok().is(AsmToken::Dollar) ||
Jim Grosbach8279c182011-11-15 22:14:41 +00004283 Parser.getTok().is(AsmToken::Integer)) {
Jim Grosbachef70e9b2011-12-09 22:25:03 +00004284 if (Parser.getTok().isNot(AsmToken::Integer))
Amaury de la Vieuvillebac917f2013-06-10 14:17:15 +00004285 Parser.Lex(); // Eat '#' or '$'.
Jim Grosbachd3595712011-08-03 23:50:40 +00004286 E = Parser.getTok().getLoc();
Daniel Dunbarf5164f42011-01-18 05:34:24 +00004287
Owen Anderson967674d2011-08-29 19:36:44 +00004288 bool isNegative = getParser().getTok().is(AsmToken::Minus);
Jim Grosbachd3595712011-08-03 23:50:40 +00004289 const MCExpr *Offset;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004290 if (getParser().parseExpression(Offset))
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004291 return true;
Jim Grosbachd3595712011-08-03 23:50:40 +00004292
4293 // The expression has to be a constant. Memory references with relocations
4294 // don't come through here, as they use the <label> forms of the relevant
4295 // instructions.
4296 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4297 if (!CE)
4298 return Error (E, "constant expression expected");
4299
Owen Anderson967674d2011-08-29 19:36:44 +00004300 // If the constant was #-0, represent it as INT32_MIN.
4301 int32_t Val = CE->getValue();
4302 if (isNegative && Val == 0)
4303 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4304
Jim Grosbachd3595712011-08-03 23:50:40 +00004305 // Now we should have the closing ']'
Jim Grosbachd3595712011-08-03 23:50:40 +00004306 if (Parser.getTok().isNot(AsmToken::RBrac))
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004307 return Error(Parser.getTok().getLoc(), "']' expected");
4308 E = Parser.getTok().getEndLoc();
Jim Grosbachd3595712011-08-03 23:50:40 +00004309 Parser.Lex(); // Eat right bracket token.
4310
4311 // Don't worry about range checking the value here. That's handled by
4312 // the is*() predicates.
4313 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
Jim Grosbacha95ec992011-10-11 17:29:55 +00004314 ARM_AM::no_shift, 0, 0,
4315 false, S, E));
Jim Grosbachd3595712011-08-03 23:50:40 +00004316
4317 // If there's a pre-indexing writeback marker, '!', just add it as a token
4318 // operand.
4319 if (Parser.getTok().is(AsmToken::Exclaim)) {
4320 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4321 Parser.Lex(); // Eat the '!'.
4322 }
4323
4324 return false;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004325 }
Jim Grosbachd3595712011-08-03 23:50:40 +00004326
4327 // The register offset is optionally preceded by a '+' or '-'
4328 bool isNegative = false;
4329 if (Parser.getTok().is(AsmToken::Minus)) {
4330 isNegative = true;
4331 Parser.Lex(); // Eat the '-'.
4332 } else if (Parser.getTok().is(AsmToken::Plus)) {
4333 // Nothing to do.
4334 Parser.Lex(); // Eat the '+'.
4335 }
4336
4337 E = Parser.getTok().getLoc();
4338 int OffsetRegNum = tryParseRegister();
4339 if (OffsetRegNum == -1)
4340 return Error(E, "register expected");
4341
4342 // If there's a shift operator, handle it.
4343 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
Jim Grosbach3d0b3a32011-08-05 22:03:36 +00004344 unsigned ShiftImm = 0;
Jim Grosbachd3595712011-08-03 23:50:40 +00004345 if (Parser.getTok().is(AsmToken::Comma)) {
4346 Parser.Lex(); // Eat the ','.
Jim Grosbach3d0b3a32011-08-05 22:03:36 +00004347 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
Jim Grosbachd3595712011-08-03 23:50:40 +00004348 return true;
4349 }
4350
4351 // Now we should have the closing ']'
Jim Grosbachd3595712011-08-03 23:50:40 +00004352 if (Parser.getTok().isNot(AsmToken::RBrac))
Jordan Rosee8f1eae2013-01-07 19:00:49 +00004353 return Error(Parser.getTok().getLoc(), "']' expected");
4354 E = Parser.getTok().getEndLoc();
Jim Grosbachd3595712011-08-03 23:50:40 +00004355 Parser.Lex(); // Eat right bracket token.
4356
4357 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
Jim Grosbacha95ec992011-10-11 17:29:55 +00004358 ShiftType, ShiftImm, 0, isNegative,
Jim Grosbachd3595712011-08-03 23:50:40 +00004359 S, E));
4360
Jim Grosbachc320c852011-08-05 21:28:30 +00004361 // If there's a pre-indexing writeback marker, '!', just add it as a token
4362 // operand.
4363 if (Parser.getTok().is(AsmToken::Exclaim)) {
4364 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4365 Parser.Lex(); // Eat the '!'.
4366 }
Jim Grosbachd3595712011-08-03 23:50:40 +00004367
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004368 return false;
4369}
4370
Jim Grosbachd3595712011-08-03 23:50:40 +00004371/// parseMemRegOffsetShift - one of these two:
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004372/// ( lsl | lsr | asr | ror ) , # shift_amount
4373/// rrx
Jim Grosbachd3595712011-08-03 23:50:40 +00004374/// return true if it parses a shift otherwise it returns false.
4375bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4376 unsigned &Amount) {
4377 SMLoc Loc = Parser.getTok().getLoc();
Sean Callanan936b0d32010-01-19 21:44:56 +00004378 const AsmToken &Tok = Parser.getTok();
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004379 if (Tok.isNot(AsmToken::Identifier))
4380 return true;
Benjamin Kramer92d89982010-07-14 22:38:02 +00004381 StringRef ShiftName = Tok.getString();
Jim Grosbach3b559ff2011-12-07 23:40:58 +00004382 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4383 ShiftName == "asl" || ShiftName == "ASL")
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00004384 St = ARM_AM::lsl;
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004385 else if (ShiftName == "lsr" || ShiftName == "LSR")
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00004386 St = ARM_AM::lsr;
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004387 else if (ShiftName == "asr" || ShiftName == "ASR")
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00004388 St = ARM_AM::asr;
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004389 else if (ShiftName == "ror" || ShiftName == "ROR")
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00004390 St = ARM_AM::ror;
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004391 else if (ShiftName == "rrx" || ShiftName == "RRX")
Owen Anderson1d2f5ce2011-03-18 22:50:18 +00004392 St = ARM_AM::rrx;
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004393 else
Jim Grosbachd3595712011-08-03 23:50:40 +00004394 return Error(Loc, "illegal shift operator");
Sean Callanana83fd7d2010-01-19 20:27:46 +00004395 Parser.Lex(); // Eat shift type token.
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004396
Jim Grosbachd3595712011-08-03 23:50:40 +00004397 // rrx stands alone.
4398 Amount = 0;
4399 if (St != ARM_AM::rrx) {
4400 Loc = Parser.getTok().getLoc();
4401 // A '#' and a shift amount.
4402 const AsmToken &HashTok = Parser.getTok();
Jim Grosbachef70e9b2011-12-09 22:25:03 +00004403 if (HashTok.isNot(AsmToken::Hash) &&
4404 HashTok.isNot(AsmToken::Dollar))
Jim Grosbachd3595712011-08-03 23:50:40 +00004405 return Error(HashTok.getLoc(), "'#' expected");
4406 Parser.Lex(); // Eat hash token.
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004407
Jim Grosbachd3595712011-08-03 23:50:40 +00004408 const MCExpr *Expr;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004409 if (getParser().parseExpression(Expr))
Jim Grosbachd3595712011-08-03 23:50:40 +00004410 return true;
4411 // Range check the immediate.
4412 // lsl, ror: 0 <= imm <= 31
4413 // lsr, asr: 0 <= imm <= 32
4414 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4415 if (!CE)
4416 return Error(Loc, "shift amount must be an immediate");
4417 int64_t Imm = CE->getValue();
4418 if (Imm < 0 ||
4419 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4420 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4421 return Error(Loc, "immediate shift value out of range");
Tim Northover0c97e762012-09-22 11:18:12 +00004422 // If <ShiftTy> #0, turn it into a no_shift.
4423 if (Imm == 0)
4424 St = ARM_AM::lsl;
4425 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4426 if (Imm == 32)
4427 Imm = 0;
Jim Grosbachd3595712011-08-03 23:50:40 +00004428 Amount = Imm;
4429 }
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004430
4431 return false;
4432}
4433
Jim Grosbache7fbce72011-10-03 23:38:36 +00004434/// parseFPImm - A floating point immediate expression operand.
4435ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4436parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004437 // Anything that can accept a floating point constant as an operand
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004438 // needs to go through here, as the regular parseExpression is
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004439 // integer only.
4440 //
4441 // This routine still creates a generic Immediate operand, containing
4442 // a bitcast of the 64-bit floating point value. The various operands
4443 // that accept floats can check whether the value is valid for them
4444 // via the standard is*() predicates.
4445
Jim Grosbache7fbce72011-10-03 23:38:36 +00004446 SMLoc S = Parser.getTok().getLoc();
4447
Jim Grosbachef70e9b2011-12-09 22:25:03 +00004448 if (Parser.getTok().isNot(AsmToken::Hash) &&
4449 Parser.getTok().isNot(AsmToken::Dollar))
Jim Grosbache7fbce72011-10-03 23:38:36 +00004450 return MatchOperand_NoMatch;
Jim Grosbach741cd732011-10-17 22:26:03 +00004451
4452 // Disambiguate the VMOV forms that can accept an FP immediate.
4453 // vmov.f32 <sreg>, #imm
4454 // vmov.f64 <dreg>, #imm
4455 // vmov.f32 <dreg>, #imm @ vector f32x2
4456 // vmov.f32 <qreg>, #imm @ vector f32x4
4457 //
4458 // There are also the NEON VMOV instructions which expect an
4459 // integer constant. Make sure we don't try to parse an FPImm
4460 // for these:
4461 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4462 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4463 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4464 TyOp->getToken() != ".f64"))
4465 return MatchOperand_NoMatch;
4466
Amaury de la Vieuvillebac917f2013-06-10 14:17:15 +00004467 Parser.Lex(); // Eat '#' or '$'.
Jim Grosbache7fbce72011-10-03 23:38:36 +00004468
4469 // Handle negation, as that still comes through as a separate token.
4470 bool isNegative = false;
4471 if (Parser.getTok().is(AsmToken::Minus)) {
4472 isNegative = true;
4473 Parser.Lex();
4474 }
4475 const AsmToken &Tok = Parser.getTok();
Jim Grosbach235c8d22012-01-19 02:47:30 +00004476 SMLoc Loc = Tok.getLoc();
Jim Grosbache7fbce72011-10-03 23:38:36 +00004477 if (Tok.is(AsmToken::Real)) {
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004478 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
Jim Grosbache7fbce72011-10-03 23:38:36 +00004479 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4480 // If we had a '-' in front, toggle the sign bit.
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004481 IntVal ^= (uint64_t)isNegative << 31;
Jim Grosbache7fbce72011-10-03 23:38:36 +00004482 Parser.Lex(); // Eat the token.
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004483 Operands.push_back(ARMOperand::CreateImm(
4484 MCConstantExpr::Create(IntVal, getContext()),
4485 S, Parser.getTok().getLoc()));
Jim Grosbache7fbce72011-10-03 23:38:36 +00004486 return MatchOperand_Success;
4487 }
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004488 // Also handle plain integers. Instructions which allow floating point
4489 // immediates also allow a raw encoded 8-bit value.
Jim Grosbache7fbce72011-10-03 23:38:36 +00004490 if (Tok.is(AsmToken::Integer)) {
4491 int64_t Val = Tok.getIntVal();
4492 Parser.Lex(); // Eat the token.
4493 if (Val > 255 || Val < 0) {
Jim Grosbach235c8d22012-01-19 02:47:30 +00004494 Error(Loc, "encoded floating point value out of range");
Jim Grosbache7fbce72011-10-03 23:38:36 +00004495 return MatchOperand_ParseFail;
4496 }
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004497 double RealVal = ARM_AM::getFPImmFloat(Val);
4498 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4499 Operands.push_back(ARMOperand::CreateImm(
4500 MCConstantExpr::Create(Val, getContext()), S,
4501 Parser.getTok().getLoc()));
Jim Grosbache7fbce72011-10-03 23:38:36 +00004502 return MatchOperand_Success;
4503 }
4504
Jim Grosbach235c8d22012-01-19 02:47:30 +00004505 Error(Loc, "invalid floating point immediate");
Jim Grosbache7fbce72011-10-03 23:38:36 +00004506 return MatchOperand_ParseFail;
4507}
Jim Grosbacha9d36fb2012-01-20 18:09:51 +00004508
Kevin Enderby8be42bd2009-10-30 22:55:57 +00004509/// Parse a arm instruction operand. For now this parses the operand regardless
4510/// of the mnemonic.
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004511bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00004512 StringRef Mnemonic) {
Sean Callanan7ad0ad02010-04-02 22:27:05 +00004513 SMLoc S, E;
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00004514
4515 // Check if the current operand has a custom associated parser, if so, try to
4516 // custom parse the operand, or fallback to the general approach.
Jim Grosbach861e49c2011-02-12 01:34:40 +00004517 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4518 if (ResTy == MatchOperand_Success)
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00004519 return false;
Jim Grosbach861e49c2011-02-12 01:34:40 +00004520 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4521 // there was a match, but an error occurred, in which case, just return that
4522 // the operand parsing failed.
4523 if (ResTy == MatchOperand_ParseFail)
4524 return true;
Bruno Cardoso Lopesc9253b42011-02-07 21:41:25 +00004525
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004526 switch (getLexer().getKind()) {
Bill Wendlingee7f1f92010-11-06 21:42:12 +00004527 default:
4528 Error(Parser.getTok().getLoc(), "unexpected token in operand");
Bill Wendling2063b842010-11-18 23:43:05 +00004529 return true;
Jim Grosbachbb24c592011-07-13 18:49:30 +00004530 case AsmToken::Identifier: {
Chad Rosierb162a5c2013-03-19 23:44:03 +00004531 // If we've seen a branch mnemonic, the next operand must be a label. This
4532 // is true even if the label is a register name. So "br r1" means branch to
4533 // label "r1".
4534 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4535 if (!ExpectLabel) {
4536 if (!tryParseRegisterWithWriteBack(Operands))
4537 return false;
4538 int Res = tryParseShiftRegister(Operands);
4539 if (Res == 0) // success
4540 return false;
4541 else if (Res == -1) // irrecoverable error
4542 return true;
4543 // If this is VMRS, check for the apsr_nzcv operand.
4544 if (Mnemonic == "vmrs" &&
4545 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4546 S = Parser.getTok().getLoc();
4547 Parser.Lex();
4548 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4549 return false;
4550 }
Jim Grosbach4ab23b52011-10-03 21:12:43 +00004551 }
Owen Andersonc3c7f5d2011-01-13 21:46:02 +00004552
4553 // Fall though for the Identifier case that is not a register or a
4554 // special name.
Jim Grosbachbb24c592011-07-13 18:49:30 +00004555 }
Jim Grosbach4e380352011-10-26 21:14:08 +00004556 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
Kevin Enderbyb084be92011-01-13 20:32:36 +00004557 case AsmToken::Integer: // things like 1f and 2b as a branch targets
Jim Grosbach5c6b6342011-11-01 22:38:31 +00004558 case AsmToken::String: // quoted label names.
Kevin Enderbyb084be92011-01-13 20:32:36 +00004559 case AsmToken::Dot: { // . as a branch target
Kevin Enderby146dcf22009-10-15 20:48:48 +00004560 // This was not a register so parse other operands that start with an
4561 // identifier (like labels) as expressions and create them as immediates.
4562 const MCExpr *IdVal;
Sean Callanan7ad0ad02010-04-02 22:27:05 +00004563 S = Parser.getTok().getLoc();
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004564 if (getParser().parseExpression(IdVal))
Bill Wendling2063b842010-11-18 23:43:05 +00004565 return true;
Sean Callanan7ad0ad02010-04-02 22:27:05 +00004566 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Bill Wendling2063b842010-11-18 23:43:05 +00004567 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4568 return false;
4569 }
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004570 case AsmToken::LBrac:
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004571 return parseMemory(Operands);
Kevin Enderbya2b99102009-10-09 21:12:28 +00004572 case AsmToken::LCurly:
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004573 return parseRegisterList(Operands);
Jim Grosbachef70e9b2011-12-09 22:25:03 +00004574 case AsmToken::Dollar:
Owen Andersonf02d98d2011-08-29 17:17:09 +00004575 case AsmToken::Hash: {
Kevin Enderby3a80dac2009-10-13 23:33:38 +00004576 // #42 -> immediate.
Sean Callanan7ad0ad02010-04-02 22:27:05 +00004577 S = Parser.getTok().getLoc();
Sean Callanana83fd7d2010-01-19 20:27:46 +00004578 Parser.Lex();
Jim Grosbach003607f2012-04-16 21:18:46 +00004579
4580 if (Parser.getTok().isNot(AsmToken::Colon)) {
4581 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4582 const MCExpr *ImmVal;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004583 if (getParser().parseExpression(ImmVal))
Jim Grosbach003607f2012-04-16 21:18:46 +00004584 return true;
4585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4586 if (CE) {
4587 int32_t Val = CE->getValue();
4588 if (isNegative && Val == 0)
4589 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4590 }
4591 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4592 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
Jim Grosbach9be2d712013-02-23 00:52:09 +00004593
4594 // There can be a trailing '!' on operands that we want as a separate
4595 // '!' Token operand. Handle that here. For example, the compatibilty
4596 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4597 if (Parser.getTok().is(AsmToken::Exclaim)) {
4598 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4599 Parser.getTok().getLoc()));
4600 Parser.Lex(); // Eat exclaim token
4601 }
Jim Grosbach003607f2012-04-16 21:18:46 +00004602 return false;
Owen Andersonf02d98d2011-08-29 17:17:09 +00004603 }
Jim Grosbach003607f2012-04-16 21:18:46 +00004604 // w/ a ':' after the '#', it's just like a plain ':'.
4605 // FALLTHROUGH
Owen Andersonf02d98d2011-08-29 17:17:09 +00004606 }
Jason W Kim1f7bc072011-01-11 23:53:41 +00004607 case AsmToken::Colon: {
4608 // ":lower16:" and ":upper16:" expression prefixes
Evan Cheng965b3c72011-01-13 07:58:56 +00004609 // FIXME: Check it's an expression prefix,
4610 // e.g. (FOO - :lower16:BAR) isn't legal.
4611 ARMMCExpr::VariantKind RefKind;
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004612 if (parsePrefix(RefKind))
Jason W Kim1f7bc072011-01-11 23:53:41 +00004613 return true;
4614
Evan Cheng965b3c72011-01-13 07:58:56 +00004615 const MCExpr *SubExprVal;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00004616 if (getParser().parseExpression(SubExprVal))
Jason W Kim1f7bc072011-01-11 23:53:41 +00004617 return true;
4618
Evan Cheng965b3c72011-01-13 07:58:56 +00004619 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
Jim Grosbach9659ed92012-09-21 00:26:53 +00004620 getContext());
Jason W Kim1f7bc072011-01-11 23:53:41 +00004621 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Evan Cheng965b3c72011-01-13 07:58:56 +00004622 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
Jason W Kim1f7bc072011-01-11 23:53:41 +00004623 return false;
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00004624 }
Jason W Kim1f7bc072011-01-11 23:53:41 +00004625 }
4626}
4627
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004628// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
Evan Cheng965b3c72011-01-13 07:58:56 +00004629// :lower16: and :upper16:.
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004630bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
Evan Cheng965b3c72011-01-13 07:58:56 +00004631 RefKind = ARMMCExpr::VK_ARM_None;
Jason W Kim1f7bc072011-01-11 23:53:41 +00004632
4633 // :lower16: and :upper16: modifiers
Jason W Kim93229972011-01-13 00:27:00 +00004634 assert(getLexer().is(AsmToken::Colon) && "expected a :");
Jason W Kim1f7bc072011-01-11 23:53:41 +00004635 Parser.Lex(); // Eat ':'
4636
4637 if (getLexer().isNot(AsmToken::Identifier)) {
4638 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4639 return true;
4640 }
4641
4642 StringRef IDVal = Parser.getTok().getIdentifier();
4643 if (IDVal == "lower16") {
Evan Cheng965b3c72011-01-13 07:58:56 +00004644 RefKind = ARMMCExpr::VK_ARM_LO16;
Jason W Kim1f7bc072011-01-11 23:53:41 +00004645 } else if (IDVal == "upper16") {
Evan Cheng965b3c72011-01-13 07:58:56 +00004646 RefKind = ARMMCExpr::VK_ARM_HI16;
Jason W Kim1f7bc072011-01-11 23:53:41 +00004647 } else {
4648 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4649 return true;
4650 }
4651 Parser.Lex();
4652
4653 if (getLexer().isNot(AsmToken::Colon)) {
4654 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4655 return true;
4656 }
4657 Parser.Lex(); // Eat the last ':'
4658 return false;
4659}
4660
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004661/// \brief Given a mnemonic, split out possible predication code and carry
4662/// setting letters to form a canonical mnemonic and flags.
4663//
Daniel Dunbar876bb0182011-01-10 12:24:52 +00004664// FIXME: Would be nice to autogen this.
Jim Grosbach3d1eac82011-08-26 21:43:41 +00004665// FIXME: This is a bit of a maze of special cases.
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004666StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
Jim Grosbach5cc3b4c2011-07-19 20:10:31 +00004667 unsigned &PredicationCode,
4668 bool &CarrySetting,
Jim Grosbach3d1eac82011-08-26 21:43:41 +00004669 unsigned &ProcessorIMod,
4670 StringRef &ITMask) {
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004671 PredicationCode = ARMCC::AL;
4672 CarrySetting = false;
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00004673 ProcessorIMod = 0;
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004674
Daniel Dunbar876bb0182011-01-10 12:24:52 +00004675 // Ignore some mnemonics we know aren't predicated forms.
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004676 //
4677 // FIXME: Would be nice to autogen this.
Jim Grosbach5cc3b4c2011-07-19 20:10:31 +00004678 if ((Mnemonic == "movs" && isThumb()) ||
4679 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4680 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4681 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4682 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
Jim Grosbach9b81a4f2013-04-15 22:42:50 +00004683 Mnemonic == "vaclt" || Mnemonic == "vacle" ||
Jim Grosbach5cc3b4c2011-07-19 20:10:31 +00004684 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4685 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
Jim Grosbache16acac2011-12-19 19:43:50 +00004686 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
Joey Gouly2efaa732013-07-06 20:50:18 +00004687 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
Joey Gouly0f12aa22013-07-09 11:26:18 +00004688 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4689 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4690 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004691 return Mnemonic;
Daniel Dunbar75d26be2010-08-11 06:37:16 +00004692
Jim Grosbacha9a3f0a2011-07-11 17:09:57 +00004693 // First, split out any predication code. Ignore mnemonics we know aren't
4694 // predicated but do have a carry-set and so weren't caught above.
Jim Grosbach8d114902011-07-20 18:20:31 +00004695 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
Jim Grosbach0c398b92011-07-27 21:58:11 +00004696 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
Jim Grosbach3636be32011-08-22 23:55:58 +00004697 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
Jim Grosbachf6d5d602011-09-01 18:22:13 +00004698 Mnemonic != "sbcs" && Mnemonic != "rscs") {
Jim Grosbacha9a3f0a2011-07-11 17:09:57 +00004699 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4700 .Case("eq", ARMCC::EQ)
4701 .Case("ne", ARMCC::NE)
4702 .Case("hs", ARMCC::HS)
4703 .Case("cs", ARMCC::HS)
4704 .Case("lo", ARMCC::LO)
4705 .Case("cc", ARMCC::LO)
4706 .Case("mi", ARMCC::MI)
4707 .Case("pl", ARMCC::PL)
4708 .Case("vs", ARMCC::VS)
4709 .Case("vc", ARMCC::VC)
4710 .Case("hi", ARMCC::HI)
4711 .Case("ls", ARMCC::LS)
4712 .Case("ge", ARMCC::GE)
4713 .Case("lt", ARMCC::LT)
4714 .Case("gt", ARMCC::GT)
4715 .Case("le", ARMCC::LE)
4716 .Case("al", ARMCC::AL)
4717 .Default(~0U);
4718 if (CC != ~0U) {
4719 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4720 PredicationCode = CC;
4721 }
Bill Wendling193961b2010-10-29 23:50:21 +00004722 }
Daniel Dunbar188b47b2010-08-11 06:37:20 +00004723
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004724 // Next, determine if we have a carry setting bit. We explicitly ignore all
4725 // the instructions we know end in 's'.
4726 if (Mnemonic.endswith("s") &&
Jim Grosbachd3e8e292011-08-17 22:49:09 +00004727 !(Mnemonic == "cps" || Mnemonic == "mls" ||
Jim Grosbach5cc3b4c2011-07-19 20:10:31 +00004728 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4729 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4730 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
Jim Grosbach086d0132011-12-08 00:49:29 +00004731 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
Jim Grosbach54337b82011-12-10 00:01:02 +00004732 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
Jim Grosbach92a939a2011-12-19 19:02:41 +00004733 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
Jim Grosbachd74560b2012-03-15 20:48:18 +00004734 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
Evan Chengaca6c822012-04-11 00:13:00 +00004735 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
Jim Grosbach51726e22011-07-29 20:26:09 +00004736 (Mnemonic == "movs" && isThumb()))) {
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004737 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4738 CarrySetting = true;
4739 }
4740
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00004741 // The "cps" instruction can have a interrupt mode operand which is glued into
4742 // the mnemonic. Check if this is the case, split it and parse the imod op
4743 if (Mnemonic.startswith("cps")) {
4744 // Split out any imod code.
4745 unsigned IMod =
4746 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4747 .Case("ie", ARM_PROC::IE)
4748 .Case("id", ARM_PROC::ID)
4749 .Default(~0U);
4750 if (IMod != ~0U) {
4751 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4752 ProcessorIMod = IMod;
4753 }
4754 }
4755
Jim Grosbach3d1eac82011-08-26 21:43:41 +00004756 // The "it" instruction has the condition mask on the end of the mnemonic.
4757 if (Mnemonic.startswith("it")) {
4758 ITMask = Mnemonic.slice(2, Mnemonic.size());
4759 Mnemonic = Mnemonic.slice(0, 2);
4760 }
4761
Daniel Dunbar9d944b32011-01-11 15:59:50 +00004762 return Mnemonic;
4763}
Daniel Dunbar5a384c82011-01-11 15:59:53 +00004764
4765/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4766/// inclusion of carry set or predication code operands.
4767//
4768// FIXME: It would be nice to autogen this.
Bruno Cardoso Lopese6290cc2011-01-18 20:55:11 +00004769void ARMAsmParser::
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00004770getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
Bruno Cardoso Lopese6290cc2011-01-18 20:55:11 +00004771 bool &CanAcceptPredicationCode) {
Daniel Dunbar09264122011-01-11 19:06:29 +00004772 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4773 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
Jim Grosbachd73c6452011-09-16 18:05:48 +00004774 Mnemonic == "add" || Mnemonic == "adc" ||
Daniel Dunbar09264122011-01-11 19:06:29 +00004775 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
Jim Grosbachfc545182011-09-19 23:31:02 +00004776 Mnemonic == "orr" || Mnemonic == "mvn" ||
Daniel Dunbar09264122011-01-11 19:06:29 +00004777 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
Jim Grosbachfc545182011-09-19 23:31:02 +00004778 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
Evan Chengaca6c822012-04-11 00:13:00 +00004779 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
Jim Grosbachd73c6452011-09-16 18:05:48 +00004780 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
Jim Grosbachfc545182011-09-19 23:31:02 +00004781 Mnemonic == "mla" || Mnemonic == "smlal" ||
4782 Mnemonic == "umlal" || Mnemonic == "umull"))) {
Daniel Dunbar09264122011-01-11 19:06:29 +00004783 CanAcceptCarrySet = true;
Jim Grosbach6c45b752011-09-16 16:39:25 +00004784 } else
Daniel Dunbar09264122011-01-11 19:06:29 +00004785 CanAcceptCarrySet = false;
Daniel Dunbar5a384c82011-01-11 15:59:53 +00004786
Tim Northover2c45a382013-06-26 16:52:40 +00004787 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4788 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4789 Mnemonic == "trap" || Mnemonic == "setend" ||
Joey Gouly2d0175e2013-07-09 09:59:04 +00004790 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4791 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
Joey Gouly0f12aa22013-07-09 11:26:18 +00004792 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4793 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4794 Mnemonic == "vrintm") {
Tim Northover2c45a382013-06-26 16:52:40 +00004795 // These mnemonics are never predicable
Daniel Dunbar5a384c82011-01-11 15:59:53 +00004796 CanAcceptPredicationCode = false;
Tim Northover2c45a382013-06-26 16:52:40 +00004797 } else if (!isThumb()) {
4798 // Some instructions are only predicable in Thumb mode
4799 CanAcceptPredicationCode
4800 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4801 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4802 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4803 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4804 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4805 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4806 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4807 } else if (isThumbOne()) {
4808 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
Jim Grosbach6c45b752011-09-16 16:39:25 +00004809 } else
Daniel Dunbar5a384c82011-01-11 15:59:53 +00004810 CanAcceptPredicationCode = true;
Daniel Dunbar876bb0182011-01-10 12:24:52 +00004811}
4812
Jim Grosbach7283da92011-08-16 21:12:37 +00004813bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4814 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004815 // FIXME: This is all horribly hacky. We really need a better way to deal
4816 // with optional operands like this in the matcher table.
Jim Grosbach7283da92011-08-16 21:12:37 +00004817
4818 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4819 // another does not. Specifically, the MOVW instruction does not. So we
4820 // special case it here and remove the defaulted (non-setting) cc_out
4821 // operand if that's the instruction we're trying to match.
4822 //
4823 // We do this as post-processing of the explicit operands rather than just
4824 // conditionally adding the cc_out in the first place because we need
4825 // to check the type of the parsed immediate operand.
Owen Andersond7791b92011-09-14 22:46:14 +00004826 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
Jim Grosbach7283da92011-08-16 21:12:37 +00004827 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4828 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4829 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4830 return true;
Jim Grosbach58ffdcc2011-08-16 21:34:08 +00004831
4832 // Register-register 'add' for thumb does not have a cc_out operand
4833 // when there are only two register operands.
4834 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4835 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4836 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4837 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4838 return true;
Jim Grosbach0a0b3072011-08-24 21:22:15 +00004839 // Register-register 'add' for thumb does not have a cc_out operand
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004840 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4841 // have to check the immediate range here since Thumb2 has a variant
4842 // that can handle a different range and has a cc_out operand.
Jim Grosbachd0c435c2011-09-16 22:58:42 +00004843 if (((isThumb() && Mnemonic == "add") ||
4844 (isThumbTwo() && Mnemonic == "sub")) &&
4845 Operands.size() == 6 &&
Jim Grosbach0a0b3072011-08-24 21:22:15 +00004846 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4847 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4848 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004849 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
Jim Grosbachdf5a2442012-04-10 17:31:55 +00004850 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004851 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
Jim Grosbach0a0b3072011-08-24 21:22:15 +00004852 return true;
Jim Grosbachd0c435c2011-09-16 22:58:42 +00004853 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4854 // imm0_4095 variant. That's the least-preferred variant when
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004855 // selecting via the generic "add" mnemonic, so to know that we
4856 // should remove the cc_out operand, we have to explicitly check that
4857 // it's not one of the other variants. Ugh.
Jim Grosbachd0c435c2011-09-16 22:58:42 +00004858 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4859 Operands.size() == 6 &&
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004860 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4861 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4862 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4863 // Nest conditions rather than one big 'if' statement for readability.
4864 //
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004865 // If both registers are low, we're in an IT block, and the immediate is
4866 // in range, we should use encoding T1 instead, which has a cc_out.
4867 if (inITBlock() &&
Jim Grosbach9c8b9932011-09-14 21:00:40 +00004868 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004869 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4870 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4871 return false;
Tilmann Schelleref5666f2013-07-03 20:38:01 +00004872 // Check against T3. If the second register is the PC, this is an
4873 // alternate form of ADR, which uses encoding T4, so check for that too.
4874 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4875 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4876 return false;
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004877
4878 // Otherwise, we use encoding T4, which does not have a cc_out
4879 // operand.
4880 return true;
4881 }
4882
Jim Grosbach9c8b9932011-09-14 21:00:40 +00004883 // The thumb2 multiply instruction doesn't have a CCOut register, so
4884 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4885 // use the 16-bit encoding or not.
4886 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4887 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4888 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4889 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4890 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4891 // If the registers aren't low regs, the destination reg isn't the
4892 // same as one of the source regs, or the cc_out operand is zero
4893 // outside of an IT block, we have to use the 32-bit encoding, so
4894 // remove the cc_out operand.
4895 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4896 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
Jim Grosbach6efa7b92011-11-15 19:29:45 +00004897 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
Jim Grosbach9c8b9932011-09-14 21:00:40 +00004898 !inITBlock() ||
4899 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4900 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4901 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4902 static_cast<ARMOperand*>(Operands[4])->getReg())))
4903 return true;
4904
Jim Grosbachefa7e952011-11-15 19:55:16 +00004905 // Also check the 'mul' syntax variant that doesn't specify an explicit
4906 // destination register.
4907 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4908 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4909 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4910 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4911 // If the registers aren't low regs or the cc_out operand is zero
4912 // outside of an IT block, we have to use the 32-bit encoding, so
4913 // remove the cc_out operand.
4914 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4915 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4916 !inITBlock()))
4917 return true;
4918
Jim Grosbach9c8b9932011-09-14 21:00:40 +00004919
Jim Grosbach1d3c1372011-09-01 00:28:52 +00004920
Jim Grosbach4b701af2011-08-24 21:42:27 +00004921 // Register-register 'add/sub' for thumb does not have a cc_out operand
4922 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4923 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4924 // right, this will result in better diagnostics (which operand is off)
4925 // anyway.
4926 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4927 (Operands.size() == 5 || Operands.size() == 6) &&
Jim Grosbach0a0b3072011-08-24 21:22:15 +00004928 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4929 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
Jim Grosbachdf5a2442012-04-10 17:31:55 +00004930 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4931 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4932 (Operands.size() == 6 &&
4933 static_cast<ARMOperand*>(Operands[5])->isImm())))
Jim Grosbach0a0b3072011-08-24 21:22:15 +00004934 return true;
Jim Grosbach58ffdcc2011-08-16 21:34:08 +00004935
Jim Grosbach7283da92011-08-16 21:12:37 +00004936 return false;
4937}
4938
Joey Goulye8602552013-07-19 16:34:16 +00004939bool ARMAsmParser::shouldOmitPredicateOperand(
4940 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4941 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4942 unsigned RegIdx = 3;
4943 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4944 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4945 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4946 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4947 RegIdx = 4;
4948
4949 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4950 (ARMMCRegisterClasses[ARM::DPRRegClassID]
4951 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4952 ARMMCRegisterClasses[ARM::QPRRegClassID]
4953 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4954 return true;
4955 }
Joey Goulyf520d5e2013-07-19 16:45:16 +00004956 return false;
Joey Goulye8602552013-07-19 16:34:16 +00004957}
4958
Joey Gouly5d0564d2013-08-02 19:18:12 +00004959bool ARMAsmParser::isDeprecated(MCInst &Inst, StringRef &Info) {
4960 if (hasV8Ops() && Inst.getOpcode() == ARM::SETEND) {
4961 Info = "armv8";
4962 return true;
4963 }
Joey Goulyfcf67782013-08-02 20:50:01 +00004964 return false;
Joey Gouly5d0564d2013-08-02 19:18:12 +00004965}
4966
Jim Grosbach12952fe2011-11-11 23:08:10 +00004967static bool isDataTypeToken(StringRef Tok) {
4968 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4969 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4970 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4971 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4972 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4973 Tok == ".f" || Tok == ".d";
4974}
4975
4976// FIXME: This bit should probably be handled via an explicit match class
4977// in the .td files that matches the suffix instead of having it be
4978// a literal string token the way it is now.
4979static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4980 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4981}
Chad Rosier9f7a2212013-04-18 22:35:36 +00004982static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
4983 unsigned VariantID);
Daniel Dunbar876bb0182011-01-10 12:24:52 +00004984/// Parse an arm instruction mnemonic followed by its operands.
Chad Rosierf0e87202012-10-25 20:41:34 +00004985bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4986 SMLoc NameLoc,
Daniel Dunbar876bb0182011-01-10 12:24:52 +00004987 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbach8be2f652011-12-09 23:34:09 +00004988 // Apply mnemonic aliases before doing anything else, as the destination
4989 // mnemnonic may include suffices and we want to handle them normally.
4990 // The generic tblgen'erated code does this later, at the start of
4991 // MatchInstructionImpl(), but that's too late for aliases that include
4992 // any sort of suffix.
4993 unsigned AvailableFeatures = getAvailableFeatures();
Chad Rosier9f7a2212013-04-18 22:35:36 +00004994 unsigned AssemblerDialect = getParser().getAssemblerDialect();
4995 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
Jim Grosbach8be2f652011-12-09 23:34:09 +00004996
Jim Grosbachab5830e2011-12-14 02:16:11 +00004997 // First check for the ARM-specific .req directive.
4998 if (Parser.getTok().is(AsmToken::Identifier) &&
4999 Parser.getTok().getIdentifier() == ".req") {
5000 parseDirectiveReq(Name, NameLoc);
5001 // We always return 'error' for this, as we're done with this
5002 // statement and don't need to match the 'instruction."
5003 return true;
5004 }
5005
Daniel Dunbar876bb0182011-01-10 12:24:52 +00005006 // Create the leading tokens for the mnemonic, split by '.' characters.
5007 size_t Start = 0, Next = Name.find('.');
Jim Grosbach7c09e3c2011-07-19 19:13:28 +00005008 StringRef Mnemonic = Name.slice(Start, Next);
Daniel Dunbar876bb0182011-01-10 12:24:52 +00005009
Daniel Dunbar9d944b32011-01-11 15:59:50 +00005010 // Split out the predication code and carry setting flag from the mnemonic.
5011 unsigned PredicationCode;
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00005012 unsigned ProcessorIMod;
Daniel Dunbar9d944b32011-01-11 15:59:50 +00005013 bool CarrySetting;
Jim Grosbach3d1eac82011-08-26 21:43:41 +00005014 StringRef ITMask;
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00005015 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
Jim Grosbach3d1eac82011-08-26 21:43:41 +00005016 ProcessorIMod, ITMask);
Daniel Dunbar876bb0182011-01-10 12:24:52 +00005017
Jim Grosbach1c171b12011-08-25 17:23:55 +00005018 // In Thumb1, only the branch (B) instruction can be predicated.
5019 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005020 Parser.eatToEndOfStatement();
Jim Grosbach1c171b12011-08-25 17:23:55 +00005021 return Error(NameLoc, "conditional execution not supported in Thumb1");
5022 }
5023
Jim Grosbach7c09e3c2011-07-19 19:13:28 +00005024 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5025
Jim Grosbach3d1eac82011-08-26 21:43:41 +00005026 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5027 // is the mask as it will be for the IT encoding if the conditional
5028 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5029 // where the conditional bit0 is zero, the instruction post-processing
5030 // will adjust the mask accordingly.
5031 if (Mnemonic == "it") {
Jim Grosbached16ec42011-08-29 22:24:09 +00005032 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5033 if (ITMask.size() > 3) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005034 Parser.eatToEndOfStatement();
Jim Grosbached16ec42011-08-29 22:24:09 +00005035 return Error(Loc, "too many conditions on IT instruction");
5036 }
Jim Grosbach3d1eac82011-08-26 21:43:41 +00005037 unsigned Mask = 8;
5038 for (unsigned i = ITMask.size(); i != 0; --i) {
5039 char pos = ITMask[i - 1];
5040 if (pos != 't' && pos != 'e') {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005041 Parser.eatToEndOfStatement();
Jim Grosbached16ec42011-08-29 22:24:09 +00005042 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
Jim Grosbach3d1eac82011-08-26 21:43:41 +00005043 }
5044 Mask >>= 1;
5045 if (ITMask[i - 1] == 't')
5046 Mask |= 8;
5047 }
Jim Grosbached16ec42011-08-29 22:24:09 +00005048 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
Jim Grosbach3d1eac82011-08-26 21:43:41 +00005049 }
5050
Jim Grosbach7c09e3c2011-07-19 19:13:28 +00005051 // FIXME: This is all a pretty gross hack. We should automatically handle
5052 // optional operands like this via tblgen.
Bill Wendling219dabd2010-11-21 10:56:05 +00005053
Daniel Dunbar5a384c82011-01-11 15:59:53 +00005054 // Next, add the CCOut and ConditionCode operands, if needed.
5055 //
5056 // For mnemonics which can ever incorporate a carry setting bit or predication
5057 // code, our matching model involves us always generating CCOut and
5058 // ConditionCode operands to match the mnemonic "as written" and then we let
5059 // the matcher deal with finding the right instruction or generating an
5060 // appropriate error.
5061 bool CanAcceptCarrySet, CanAcceptPredicationCode;
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00005062 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
Daniel Dunbar5a384c82011-01-11 15:59:53 +00005063
Jim Grosbach03a8a162011-07-14 22:04:21 +00005064 // If we had a carry-set on an instruction that can't do that, issue an
5065 // error.
5066 if (!CanAcceptCarrySet && CarrySetting) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005067 Parser.eatToEndOfStatement();
Jim Grosbach7c09e3c2011-07-19 19:13:28 +00005068 return Error(NameLoc, "instruction '" + Mnemonic +
Jim Grosbach03a8a162011-07-14 22:04:21 +00005069 "' can not set flags, but 's' suffix specified");
5070 }
Jim Grosbach0a547702011-07-22 17:44:50 +00005071 // If we had a predication code on an instruction that can't do that, issue an
5072 // error.
5073 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005074 Parser.eatToEndOfStatement();
Jim Grosbach0a547702011-07-22 17:44:50 +00005075 return Error(NameLoc, "instruction '" + Mnemonic +
5076 "' is not predicable, but condition code specified");
5077 }
Jim Grosbach03a8a162011-07-14 22:04:21 +00005078
Daniel Dunbar5a384c82011-01-11 15:59:53 +00005079 // Add the carry setting operand, if necessary.
Jim Grosbached16ec42011-08-29 22:24:09 +00005080 if (CanAcceptCarrySet) {
5081 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
Daniel Dunbar5a384c82011-01-11 15:59:53 +00005082 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
Jim Grosbached16ec42011-08-29 22:24:09 +00005083 Loc));
5084 }
Daniel Dunbar5a384c82011-01-11 15:59:53 +00005085
5086 // Add the predication code operand, if necessary.
5087 if (CanAcceptPredicationCode) {
Jim Grosbached16ec42011-08-29 22:24:09 +00005088 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5089 CarrySetting);
Daniel Dunbar5a384c82011-01-11 15:59:53 +00005090 Operands.push_back(ARMOperand::CreateCondCode(
Jim Grosbached16ec42011-08-29 22:24:09 +00005091 ARMCC::CondCodes(PredicationCode), Loc));
Daniel Dunbar876bb0182011-01-10 12:24:52 +00005092 }
Daniel Dunbar188b47b2010-08-11 06:37:20 +00005093
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00005094 // Add the processor imod operand, if necessary.
5095 if (ProcessorIMod) {
5096 Operands.push_back(ARMOperand::CreateImm(
5097 MCConstantExpr::Create(ProcessorIMod, getContext()),
5098 NameLoc, NameLoc));
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00005099 }
5100
Daniel Dunbar188b47b2010-08-11 06:37:20 +00005101 // Add the remaining tokens in the mnemonic.
Daniel Dunbar75d26be2010-08-11 06:37:16 +00005102 while (Next != StringRef::npos) {
5103 Start = Next;
5104 Next = Name.find('.', Start + 1);
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +00005105 StringRef ExtraToken = Name.slice(Start, Next);
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00005106
Jim Grosbach12952fe2011-11-11 23:08:10 +00005107 // Some NEON instructions have an optional datatype suffix that is
5108 // completely ignored. Check for that.
5109 if (isDataTypeToken(ExtraToken) &&
5110 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5111 continue;
5112
Kevin Enderbyc5d09352013-06-18 20:19:24 +00005113 // For for ARM mode generate an error if the .n qualifier is used.
5114 if (ExtraToken == ".n" && !isThumb()) {
5115 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5116 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5117 "arm mode");
5118 }
5119
5120 // The .n qualifier is always discarded as that is what the tables
5121 // and matcher expect. In ARM mode the .w qualifier has no effect,
5122 // so discard it to avoid errors that can be caused by the matcher.
5123 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
Jim Grosbach39c6e1d2011-09-07 16:06:04 +00005124 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5125 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5126 }
Daniel Dunbar75d26be2010-08-11 06:37:16 +00005127 }
5128
5129 // Read the remaining operands.
5130 if (getLexer().isNot(AsmToken::EndOfStatement)) {
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00005131 // Read the first operand.
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00005132 if (parseOperand(Operands, Mnemonic)) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005133 Parser.eatToEndOfStatement();
Chris Lattnera2a9d162010-09-11 16:18:25 +00005134 return true;
5135 }
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00005136
5137 while (getLexer().is(AsmToken::Comma)) {
Sean Callanana83fd7d2010-01-19 20:27:46 +00005138 Parser.Lex(); // Eat the comma.
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00005139
5140 // Parse and remember the operand.
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00005141 if (parseOperand(Operands, Mnemonic)) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005142 Parser.eatToEndOfStatement();
Chris Lattnera2a9d162010-09-11 16:18:25 +00005143 return true;
5144 }
Kevin Enderbyfebe39b2009-10-06 22:26:42 +00005145 }
5146 }
Jim Grosbach624bcc72010-10-29 14:46:02 +00005147
Chris Lattnera2a9d162010-09-11 16:18:25 +00005148 if (getLexer().isNot(AsmToken::EndOfStatement)) {
Jim Grosbachb8d9f512011-10-07 18:27:04 +00005149 SMLoc Loc = getLexer().getLoc();
Jim Grosbachd2037eb2013-02-20 22:21:35 +00005150 Parser.eatToEndOfStatement();
Jim Grosbachb8d9f512011-10-07 18:27:04 +00005151 return Error(Loc, "unexpected token in argument list");
Chris Lattnera2a9d162010-09-11 16:18:25 +00005152 }
Bill Wendlingee7f1f92010-11-06 21:42:12 +00005153
Chris Lattner91689c12010-09-08 05:10:46 +00005154 Parser.Lex(); // Consume the EndOfStatement
Jim Grosbach7c09e3c2011-07-19 19:13:28 +00005155
Jim Grosbach7283da92011-08-16 21:12:37 +00005156 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5157 // do and don't have a cc_out optional-def operand. With some spot-checks
5158 // of the operand list, we can figure out which variant we're trying to
Jim Grosbach1d3c1372011-09-01 00:28:52 +00005159 // parse and adjust accordingly before actually matching. We shouldn't ever
5160 // try to remove a cc_out operand that was explicitly set on the the
5161 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5162 // table driven matcher doesn't fit well with the ARM instruction set.
5163 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
Jim Grosbach7c09e3c2011-07-19 19:13:28 +00005164 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5165 Operands.erase(Operands.begin() + 1);
5166 delete Op;
5167 }
5168
Joey Goulye8602552013-07-19 16:34:16 +00005169 // Some instructions have the same mnemonic, but don't always
5170 // have a predicate. Distinguish them here and delete the
5171 // predicate if needed.
5172 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5173 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5174 Operands.erase(Operands.begin() + 1);
5175 delete Op;
5176 }
5177
Jim Grosbacha03ab0e2011-07-28 21:57:55 +00005178 // ARM mode 'blx' need special handling, as the register operand version
5179 // is predicable, but the label operand version is not. So, we can't rely
5180 // on the Mnemonic based checking to correctly figure out when to put
Jim Grosbach6e5778f2011-10-07 23:24:09 +00005181 // a k_CondCode operand in the list. If we're trying to match the label
5182 // version, remove the k_CondCode operand here.
Jim Grosbacha03ab0e2011-07-28 21:57:55 +00005183 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5184 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5185 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5186 Operands.erase(Operands.begin() + 1);
5187 delete Op;
5188 }
Jim Grosbach8cffa282011-08-11 23:51:13 +00005189
Weiming Zhao8f56f882012-11-16 21:55:34 +00005190 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5191 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5192 // a single GPRPair reg operand is used in the .td file to replace the two
5193 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5194 // expressed as a GPRPair, so we have to manually merge them.
5195 // FIXME: We would really like to be able to tablegen'erate this.
5196 if (!isThumb() && Operands.size() > 4 &&
5197 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5198 bool isLoad = (Mnemonic == "ldrexd");
5199 unsigned Idx = isLoad ? 2 : 3;
5200 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5201 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5202
5203 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5204 // Adjust only if Op1 and Op2 are GPRs.
5205 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5206 MRC.contains(Op2->getReg())) {
5207 unsigned Reg1 = Op1->getReg();
5208 unsigned Reg2 = Op2->getReg();
5209 unsigned Rt = MRI->getEncodingValue(Reg1);
5210 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5211
5212 // Rt2 must be Rt + 1 and Rt must be even.
5213 if (Rt + 1 != Rt2 || (Rt & 1)) {
5214 Error(Op2->getStartLoc(), isLoad ?
5215 "destination operands must be sequential" :
5216 "source operands must be sequential");
5217 return true;
5218 }
5219 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5220 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5221 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5222 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5223 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5224 delete Op1;
5225 delete Op2;
5226 }
5227 }
5228
Kevin Enderby78f95722013-07-31 21:05:30 +00005229 // FIXME: As said above, this is all a pretty gross hack. This instruction
5230 // does not fit with other "subs" and tblgen.
5231 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5232 // so the Mnemonic is the original name "subs" and delete the predicate
5233 // operand so it will match the table entry.
5234 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5235 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5236 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5237 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5238 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5239 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5240 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5241 Operands.erase(Operands.begin());
5242 delete Op0;
5243 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5244
5245 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5246 Operands.erase(Operands.begin() + 1);
5247 delete Op1;
5248 }
Chris Lattnerf29c0b62010-01-14 22:21:20 +00005249 return false;
Kevin Enderbyccab3172009-09-15 00:27:25 +00005250}
5251
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005252// Validate context-sensitive operand constraints.
Jim Grosbach169b2be2011-08-23 18:13:04 +00005253
5254// return 'true' if register list contains non-low GPR registers,
5255// 'false' otherwise. If Reg is in the register list or is HiReg, set
5256// 'containsReg' to true.
5257static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5258 unsigned HiReg, bool &containsReg) {
5259 containsReg = false;
5260 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5261 unsigned OpReg = Inst.getOperand(i).getReg();
5262 if (OpReg == Reg)
5263 containsReg = true;
5264 // Anything other than a low register isn't legal here.
5265 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5266 return true;
5267 }
5268 return false;
5269}
5270
Jim Grosbacha31f2232011-09-07 18:05:34 +00005271// Check if the specified regisgter is in the register list of the inst,
5272// starting at the indicated operand number.
5273static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5274 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5275 unsigned OpReg = Inst.getOperand(i).getReg();
5276 if (OpReg == Reg)
5277 return true;
5278 }
5279 return false;
5280}
5281
Jim Grosbached16ec42011-08-29 22:24:09 +00005282// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5283// the ARMInsts array) instead. Getting that here requires awkward
5284// API changes, though. Better way?
5285namespace llvm {
Benjamin Kramer0d6d0982011-10-22 16:50:00 +00005286extern const MCInstrDesc ARMInsts[];
Jim Grosbached16ec42011-08-29 22:24:09 +00005287}
Benjamin Kramer0d6d0982011-10-22 16:50:00 +00005288static const MCInstrDesc &getInstDesc(unsigned Opcode) {
Jim Grosbached16ec42011-08-29 22:24:09 +00005289 return ARMInsts[Opcode];
5290}
5291
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005292// FIXME: We would really like to be able to tablegen'erate this.
5293bool ARMAsmParser::
5294validateInstruction(MCInst &Inst,
5295 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Benjamin Kramer0d6d0982011-10-22 16:50:00 +00005296 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
Jim Grosbached16ec42011-08-29 22:24:09 +00005297 SMLoc Loc = Operands[0]->getStartLoc();
Mihai Popaad18d3c2013-08-09 10:38:32 +00005298
Jim Grosbached16ec42011-08-29 22:24:09 +00005299 // Check the IT block state first.
Jim Grosbach82f76d12012-01-25 19:52:01 +00005300 // NOTE: BKPT instruction has the interesting property of being
5301 // allowed in IT blocks, but not being predicable. It just always
Owen Anderson44ae2da2011-09-13 17:59:19 +00005302 // executes.
Jim Grosbach82f76d12012-01-25 19:52:01 +00005303 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5304 Inst.getOpcode() != ARM::BKPT) {
Jim Grosbached16ec42011-08-29 22:24:09 +00005305 unsigned bit = 1;
5306 if (ITState.FirstCond)
5307 ITState.FirstCond = false;
5308 else
Jim Grosbacha0d34d32011-09-02 23:22:08 +00005309 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
Jim Grosbached16ec42011-08-29 22:24:09 +00005310 // The instruction must be predicable.
5311 if (!MCID.isPredicable())
5312 return Error(Loc, "instructions in IT block must be predicable");
5313 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5314 unsigned ITCond = bit ? ITState.Cond :
5315 ARMCC::getOppositeCondition(ITState.Cond);
5316 if (Cond != ITCond) {
5317 // Find the condition code Operand to get its SMLoc information.
5318 SMLoc CondLoc;
5319 for (unsigned i = 1; i < Operands.size(); ++i)
5320 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5321 CondLoc = Operands[i]->getStartLoc();
5322 return Error(CondLoc, "incorrect condition in IT block; got '" +
5323 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5324 "', but expected '" +
5325 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5326 }
Jim Grosbachc61fc8f2011-08-31 18:29:05 +00005327 // Check for non-'al' condition codes outside of the IT block.
Jim Grosbached16ec42011-08-29 22:24:09 +00005328 } else if (isThumbTwo() && MCID.isPredicable() &&
5329 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
Mihai Popaad18d3c2013-08-09 10:38:32 +00005330 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5331 Inst.getOpcode() != ARM::t2Bcc)
Jim Grosbached16ec42011-08-29 22:24:09 +00005332 return Error(Loc, "predicated instructions must be in IT block");
5333
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005334 switch (Inst.getOpcode()) {
Jim Grosbach5b96b802011-08-10 20:29:19 +00005335 case ARM::LDRD:
5336 case ARM::LDRD_PRE:
Weiming Zhao8f56f882012-11-16 21:55:34 +00005337 case ARM::LDRD_POST: {
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005338 // Rt2 must be Rt + 1.
Eric Christopher6ac277c2012-08-09 22:10:21 +00005339 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5340 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005341 if (Rt2 != Rt + 1)
5342 return Error(Operands[3]->getStartLoc(),
5343 "destination operands must be sequential");
5344 return false;
5345 }
Jim Grosbacheb09f492011-08-11 20:28:23 +00005346 case ARM::STRD: {
5347 // Rt2 must be Rt + 1.
Eric Christopher6ac277c2012-08-09 22:10:21 +00005348 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5349 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
Jim Grosbacheb09f492011-08-11 20:28:23 +00005350 if (Rt2 != Rt + 1)
5351 return Error(Operands[3]->getStartLoc(),
5352 "source operands must be sequential");
5353 return false;
5354 }
Jim Grosbachf7164b22011-08-10 20:49:18 +00005355 case ARM::STRD_PRE:
Weiming Zhao8f56f882012-11-16 21:55:34 +00005356 case ARM::STRD_POST: {
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005357 // Rt2 must be Rt + 1.
Eric Christopher6ac277c2012-08-09 22:10:21 +00005358 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5359 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005360 if (Rt2 != Rt + 1)
Jim Grosbacheb09f492011-08-11 20:28:23 +00005361 return Error(Operands[3]->getStartLoc(),
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005362 "source operands must be sequential");
5363 return false;
5364 }
Jim Grosbach03f56d92011-07-27 21:09:25 +00005365 case ARM::SBFX:
5366 case ARM::UBFX: {
5367 // width must be in range [1, 32-lsb]
5368 unsigned lsb = Inst.getOperand(2).getImm();
5369 unsigned widthm1 = Inst.getOperand(3).getImm();
5370 if (widthm1 >= 32 - lsb)
5371 return Error(Operands[5]->getStartLoc(),
5372 "bitfield width must be in range [1,32-lsb]");
Jim Grosbach64610e52011-08-16 21:42:31 +00005373 return false;
Jim Grosbach03f56d92011-07-27 21:09:25 +00005374 }
Jim Grosbach90103cc2011-08-18 21:50:53 +00005375 case ARM::tLDMIA: {
Jim Grosbacha31f2232011-09-07 18:05:34 +00005376 // If we're parsing Thumb2, the .w variant is available and handles
5377 // most cases that are normally illegal for a Thumb1 LDM
5378 // instruction. We'll make the transformation in processInstruction()
5379 // if necessary.
5380 //
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +00005381 // Thumb LDM instructions are writeback iff the base register is not
Jim Grosbach90103cc2011-08-18 21:50:53 +00005382 // in the register list.
5383 unsigned Rn = Inst.getOperand(0).getReg();
Jim Grosbach139acd22011-08-22 23:01:07 +00005384 bool hasWritebackToken =
5385 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5386 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
Jim Grosbach169b2be2011-08-23 18:13:04 +00005387 bool listContainsBase;
Jim Grosbacha31f2232011-09-07 18:05:34 +00005388 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
Jim Grosbach169b2be2011-08-23 18:13:04 +00005389 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5390 "registers must be in range r0-r7");
Jim Grosbach90103cc2011-08-18 21:50:53 +00005391 // If we should have writeback, then there should be a '!' token.
Jim Grosbacha31f2232011-09-07 18:05:34 +00005392 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
Jim Grosbach90103cc2011-08-18 21:50:53 +00005393 return Error(Operands[2]->getStartLoc(),
5394 "writeback operator '!' expected");
Jim Grosbacha31f2232011-09-07 18:05:34 +00005395 // If we should not have writeback, there must not be a '!'. This is
5396 // true even for the 32-bit wide encodings.
Jim Grosbach169b2be2011-08-23 18:13:04 +00005397 if (listContainsBase && hasWritebackToken)
Jim Grosbach139acd22011-08-22 23:01:07 +00005398 return Error(Operands[3]->getStartLoc(),
5399 "writeback operator '!' not allowed when base register "
5400 "in register list");
Jim Grosbach90103cc2011-08-18 21:50:53 +00005401
5402 break;
5403 }
Jim Grosbacha31f2232011-09-07 18:05:34 +00005404 case ARM::t2LDMIA_UPD: {
5405 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5406 return Error(Operands[4]->getStartLoc(),
5407 "writeback operator '!' not allowed when base register "
5408 "in register list");
5409 break;
5410 }
Chad Rosier8513ffb2012-08-30 23:20:38 +00005411 case ARM::tMUL: {
5412 // The second source operand must be the same register as the destination
5413 // operand.
Chad Rosier9d1fc362012-08-31 17:24:10 +00005414 //
5415 // In this case, we must directly check the parsed operands because the
5416 // cvtThumbMultiply() function is written in such a way that it guarantees
5417 // this first statement is always true for the new Inst. Essentially, the
5418 // destination is unconditionally copied into the second source operand
5419 // without checking to see if it matches what we actually parsed.
Chad Rosier8513ffb2012-08-30 23:20:38 +00005420 if (Operands.size() == 6 &&
5421 (((ARMOperand*)Operands[3])->getReg() !=
5422 ((ARMOperand*)Operands[5])->getReg()) &&
5423 (((ARMOperand*)Operands[3])->getReg() !=
5424 ((ARMOperand*)Operands[4])->getReg())) {
Chad Rosierdb482ef2012-08-30 23:22:05 +00005425 return Error(Operands[3]->getStartLoc(),
5426 "destination register must match source register");
Chad Rosier8513ffb2012-08-30 23:20:38 +00005427 }
5428 break;
5429 }
Jim Grosbach9bded9d2011-11-10 23:17:11 +00005430 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5431 // so only issue a diagnostic for thumb1. The instructions will be
5432 // switched to the t2 encodings in processInstruction() if necessary.
Jim Grosbach38c59fc2011-08-22 23:17:34 +00005433 case ARM::tPOP: {
Jim Grosbach169b2be2011-08-23 18:13:04 +00005434 bool listContainsBase;
Jim Grosbach9bded9d2011-11-10 23:17:11 +00005435 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5436 !isThumbTwo())
Jim Grosbach169b2be2011-08-23 18:13:04 +00005437 return Error(Operands[2]->getStartLoc(),
5438 "registers must be in range r0-r7 or pc");
Jim Grosbach38c59fc2011-08-22 23:17:34 +00005439 break;
5440 }
5441 case ARM::tPUSH: {
Jim Grosbach169b2be2011-08-23 18:13:04 +00005442 bool listContainsBase;
Jim Grosbach9bded9d2011-11-10 23:17:11 +00005443 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5444 !isThumbTwo())
Jim Grosbach169b2be2011-08-23 18:13:04 +00005445 return Error(Operands[2]->getStartLoc(),
5446 "registers must be in range r0-r7 or lr");
Jim Grosbach38c59fc2011-08-22 23:17:34 +00005447 break;
5448 }
Jim Grosbachd80d1692011-08-23 18:15:37 +00005449 case ARM::tSTMIA_UPD: {
5450 bool listContainsBase;
Jim Grosbach099c9762011-09-16 20:50:13 +00005451 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
Jim Grosbachd80d1692011-08-23 18:15:37 +00005452 return Error(Operands[4]->getStartLoc(),
5453 "registers must be in range r0-r7");
5454 break;
5455 }
Jim Grosbachc6f32b32012-04-27 23:51:36 +00005456 case ARM::tADDrSP: {
5457 // If the non-SP source operand and the destination operand are not the
5458 // same, we need thumb2 (for the wide encoding), or we have an error.
5459 if (!isThumbTwo() &&
5460 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5461 return Error(Operands[4]->getStartLoc(),
5462 "source register must be the same as destination");
5463 }
5464 break;
5465 }
Mihai Popaad18d3c2013-08-09 10:38:32 +00005466 // final range checking for Thumb unconditional branch instructions
5467 case ARM::tB:
5468 if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5469 return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5470 break;
5471 case ARM::t2B: {
5472 int op = (Operands[2]->isImm()) ? 2 : 3;
5473 if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5474 return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5475 break;
5476 }
5477 // final range checking for Thumb conditional branch instructions
5478 case ARM::tBcc:
5479 if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5480 return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5481 break;
5482 case ARM::t2Bcc: {
5483 int op = (Operands[2]->isImm()) ? 2 : 3;
5484 if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<20, 1>())
5485 return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5486 break;
5487 }
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005488 }
5489
Joey Gouly5d0564d2013-08-02 19:18:12 +00005490 StringRef DepInfo;
5491 if (isDeprecated(Inst, DepInfo))
5492 Warning(Loc, "deprecated on " + DepInfo);
5493
Jim Grosbachedaa35a2011-07-26 18:25:39 +00005494 return false;
5495}
5496
Jim Grosbach1a747242012-01-23 23:45:44 +00005497static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
Jim Grosbacheb538222011-12-02 22:34:51 +00005498 switch(Opc) {
Craig Toppere55c5562012-02-07 02:50:20 +00005499 default: llvm_unreachable("unexpected opcode!");
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005500 // VST1LN
Jim Grosbach1e946a42012-01-24 00:43:12 +00005501 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5502 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5503 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5504 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5505 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5506 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5507 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5508 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5509 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005510
5511 // VST2LN
Jim Grosbach1e946a42012-01-24 00:43:12 +00005512 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5513 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5514 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5515 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5516 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
Jim Grosbach2c590522011-12-20 20:46:29 +00005517
Jim Grosbach1e946a42012-01-24 00:43:12 +00005518 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5519 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5520 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5521 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5522 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
Jim Grosbach2c590522011-12-20 20:46:29 +00005523
Jim Grosbach1e946a42012-01-24 00:43:12 +00005524 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5525 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5526 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5527 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5528 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
Jim Grosbach1a747242012-01-23 23:45:44 +00005529
Jim Grosbachd3d36d92012-01-24 00:07:41 +00005530 // VST3LN
Jim Grosbach1e946a42012-01-24 00:43:12 +00005531 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5532 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5533 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5534 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5535 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5536 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5537 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5538 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5539 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5540 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5541 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5542 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5543 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5544 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5545 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
Jim Grosbachd3d36d92012-01-24 00:07:41 +00005546
Jim Grosbach1a747242012-01-23 23:45:44 +00005547 // VST3
Jim Grosbach1e946a42012-01-24 00:43:12 +00005548 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5549 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5550 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5551 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5552 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5553 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5554 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5555 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5556 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5557 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5558 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5559 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5560 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5561 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5562 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5563 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5564 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5565 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
Jim Grosbachda70eac2012-01-24 00:58:13 +00005566
Jim Grosbach8e2722c2012-01-24 18:53:13 +00005567 // VST4LN
5568 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5569 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5570 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5571 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5572 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5573 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5574 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5575 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5576 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5577 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5578 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5579 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5580 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5581 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5582 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5583
Jim Grosbachda70eac2012-01-24 00:58:13 +00005584 // VST4
5585 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5586 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5587 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5588 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5589 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5590 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5591 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5592 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5593 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5594 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5595 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5596 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5597 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5598 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5599 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5600 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5601 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5602 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
Jim Grosbacheb538222011-12-02 22:34:51 +00005603 }
5604}
5605
Jim Grosbach1a747242012-01-23 23:45:44 +00005606static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
Jim Grosbach04945c42011-12-02 00:35:16 +00005607 switch(Opc) {
Craig Toppere55c5562012-02-07 02:50:20 +00005608 default: llvm_unreachable("unexpected opcode!");
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005609 // VLD1LN
Jim Grosbach1e946a42012-01-24 00:43:12 +00005610 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5611 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5612 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5613 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5614 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5615 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5616 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5617 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5618 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005619
5620 // VLD2LN
Jim Grosbach1e946a42012-01-24 00:43:12 +00005621 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5622 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5623 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5624 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5625 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5626 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5627 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5628 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5629 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5630 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5631 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5632 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5633 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5634 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5635 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
Jim Grosbacha8b444b2012-01-23 21:53:26 +00005636
Jim Grosbachb78403c2012-01-24 23:47:04 +00005637 // VLD3DUP
5638 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5639 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5640 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5641 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5642 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5643 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5644 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5645 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5646 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5647 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5648 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5649 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5650 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5651 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5652 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5653 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5654 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5655 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5656
Jim Grosbacha8b444b2012-01-23 21:53:26 +00005657 // VLD3LN
Jim Grosbach1e946a42012-01-24 00:43:12 +00005658 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5659 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5660 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5661 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5662 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5663 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5664 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5665 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5666 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5667 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5668 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5669 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5670 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5671 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5672 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
Jim Grosbachac2af3f2012-01-23 23:20:46 +00005673
5674 // VLD3
Jim Grosbach1e946a42012-01-24 00:43:12 +00005675 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5676 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5677 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5678 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5679 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5680 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5681 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5682 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5683 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5684 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5685 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5686 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5687 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5688 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5689 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5690 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5691 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5692 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
Jim Grosbached561fc2012-01-24 00:43:17 +00005693
Jim Grosbach14952a02012-01-24 18:37:25 +00005694 // VLD4LN
5695 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5696 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5697 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5698 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5699 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5700 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5701 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5702 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5703 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5704 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5705 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5706 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5707 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5708 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5709 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5710
Jim Grosbach086cbfa2012-01-25 00:01:08 +00005711 // VLD4DUP
5712 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5713 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5714 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5715 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5716 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5717 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5718 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5719 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5720 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5721 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5722 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5723 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5724 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5725 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5726 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5727 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5728 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5729 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5730
Jim Grosbached561fc2012-01-24 00:43:17 +00005731 // VLD4
5732 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5733 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5734 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5735 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5736 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5737 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5738 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5739 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5740 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5741 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5742 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5743 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5744 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5745 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5746 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5747 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5748 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5749 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
Jim Grosbach04945c42011-12-02 00:35:16 +00005750 }
5751}
5752
Jim Grosbachafad0532011-11-10 23:42:14 +00005753bool ARMAsmParser::
Jim Grosbach8ba76c62011-08-11 17:35:48 +00005754processInstruction(MCInst &Inst,
5755 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5756 switch (Inst.getOpcode()) {
Jim Grosbache974a6a2012-09-25 00:08:13 +00005757 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5758 case ARM::ADDri: {
5759 if (Inst.getOperand(1).getReg() != ARM::PC ||
5760 Inst.getOperand(5).getReg() != 0)
5761 return false;
5762 MCInst TmpInst;
5763 TmpInst.setOpcode(ARM::ADR);
5764 TmpInst.addOperand(Inst.getOperand(0));
5765 TmpInst.addOperand(Inst.getOperand(2));
5766 TmpInst.addOperand(Inst.getOperand(3));
5767 TmpInst.addOperand(Inst.getOperand(4));
5768 Inst = TmpInst;
5769 return true;
5770 }
Jim Grosbach94298a92012-01-18 22:46:46 +00005771 // Aliases for alternate PC+imm syntax of LDR instructions.
5772 case ARM::t2LDRpcrel:
Kevin Enderby06aa3eb82012-12-14 23:04:25 +00005773 // Select the narrow version if the immediate will fit.
5774 if (Inst.getOperand(1).getImm() > 0 &&
Amaury de la Vieuvilleeac0bad2013-06-18 08:13:05 +00005775 Inst.getOperand(1).getImm() <= 0xff &&
5776 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5777 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
Kevin Enderby06aa3eb82012-12-14 23:04:25 +00005778 Inst.setOpcode(ARM::tLDRpci);
5779 else
5780 Inst.setOpcode(ARM::t2LDRpci);
Jim Grosbach94298a92012-01-18 22:46:46 +00005781 return true;
5782 case ARM::t2LDRBpcrel:
5783 Inst.setOpcode(ARM::t2LDRBpci);
5784 return true;
5785 case ARM::t2LDRHpcrel:
5786 Inst.setOpcode(ARM::t2LDRHpci);
5787 return true;
5788 case ARM::t2LDRSBpcrel:
5789 Inst.setOpcode(ARM::t2LDRSBpci);
5790 return true;
5791 case ARM::t2LDRSHpcrel:
5792 Inst.setOpcode(ARM::t2LDRSHpci);
5793 return true;
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005794 // Handle NEON VST complex aliases.
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00005795 case ARM::VST1LNdWB_register_Asm_8:
5796 case ARM::VST1LNdWB_register_Asm_16:
5797 case ARM::VST1LNdWB_register_Asm_32: {
Jim Grosbacheb538222011-12-02 22:34:51 +00005798 MCInst TmpInst;
5799 // Shuffle the operands around so the lane index operand is in the
5800 // right place.
Jim Grosbach2c590522011-12-20 20:46:29 +00005801 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00005802 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacheb538222011-12-02 22:34:51 +00005803 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5804 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5805 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5806 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5807 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5808 TmpInst.addOperand(Inst.getOperand(1)); // lane
5809 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5810 TmpInst.addOperand(Inst.getOperand(6));
5811 Inst = TmpInst;
5812 return true;
5813 }
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005814
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00005815 case ARM::VST2LNdWB_register_Asm_8:
5816 case ARM::VST2LNdWB_register_Asm_16:
5817 case ARM::VST2LNdWB_register_Asm_32:
5818 case ARM::VST2LNqWB_register_Asm_16:
5819 case ARM::VST2LNqWB_register_Asm_32: {
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005820 MCInst TmpInst;
5821 // Shuffle the operands around so the lane index operand is in the
5822 // right place.
Jim Grosbach2c590522011-12-20 20:46:29 +00005823 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00005824 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005825 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5826 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5827 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5828 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5829 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach2c590522011-12-20 20:46:29 +00005830 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5831 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005832 TmpInst.addOperand(Inst.getOperand(1)); // lane
5833 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5834 TmpInst.addOperand(Inst.getOperand(6));
5835 Inst = TmpInst;
5836 return true;
5837 }
Jim Grosbachd3d36d92012-01-24 00:07:41 +00005838
5839 case ARM::VST3LNdWB_register_Asm_8:
5840 case ARM::VST3LNdWB_register_Asm_16:
5841 case ARM::VST3LNdWB_register_Asm_32:
5842 case ARM::VST3LNqWB_register_Asm_16:
5843 case ARM::VST3LNqWB_register_Asm_32: {
5844 MCInst TmpInst;
5845 // Shuffle the operands around so the lane index operand is in the
5846 // right place.
5847 unsigned Spacing;
5848 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5849 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5850 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5851 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5852 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5853 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5854 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5855 Spacing));
5856 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5857 Spacing * 2));
5858 TmpInst.addOperand(Inst.getOperand(1)); // lane
5859 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5860 TmpInst.addOperand(Inst.getOperand(6));
5861 Inst = TmpInst;
5862 return true;
5863 }
5864
Jim Grosbach8e2722c2012-01-24 18:53:13 +00005865 case ARM::VST4LNdWB_register_Asm_8:
5866 case ARM::VST4LNdWB_register_Asm_16:
5867 case ARM::VST4LNdWB_register_Asm_32:
5868 case ARM::VST4LNqWB_register_Asm_16:
5869 case ARM::VST4LNqWB_register_Asm_32: {
5870 MCInst TmpInst;
5871 // Shuffle the operands around so the lane index operand is in the
5872 // right place.
5873 unsigned Spacing;
5874 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5875 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5876 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5877 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5878 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5879 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5881 Spacing));
5882 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5883 Spacing * 2));
5884 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5885 Spacing * 3));
5886 TmpInst.addOperand(Inst.getOperand(1)); // lane
5887 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5888 TmpInst.addOperand(Inst.getOperand(6));
5889 Inst = TmpInst;
5890 return true;
5891 }
5892
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00005893 case ARM::VST1LNdWB_fixed_Asm_8:
5894 case ARM::VST1LNdWB_fixed_Asm_16:
5895 case ARM::VST1LNdWB_fixed_Asm_32: {
Jim Grosbacheb538222011-12-02 22:34:51 +00005896 MCInst TmpInst;
5897 // Shuffle the operands around so the lane index operand is in the
5898 // right place.
Jim Grosbach2c590522011-12-20 20:46:29 +00005899 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00005900 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacheb538222011-12-02 22:34:51 +00005901 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5902 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5903 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5904 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5905 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5906 TmpInst.addOperand(Inst.getOperand(1)); // lane
5907 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5908 TmpInst.addOperand(Inst.getOperand(5));
5909 Inst = TmpInst;
5910 return true;
5911 }
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005912
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00005913 case ARM::VST2LNdWB_fixed_Asm_8:
5914 case ARM::VST2LNdWB_fixed_Asm_16:
5915 case ARM::VST2LNdWB_fixed_Asm_32:
5916 case ARM::VST2LNqWB_fixed_Asm_16:
5917 case ARM::VST2LNqWB_fixed_Asm_32: {
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005918 MCInst TmpInst;
5919 // Shuffle the operands around so the lane index operand is in the
5920 // right place.
Jim Grosbach2c590522011-12-20 20:46:29 +00005921 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00005922 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005923 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5924 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5925 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5926 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5927 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach2c590522011-12-20 20:46:29 +00005928 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5929 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00005930 TmpInst.addOperand(Inst.getOperand(1)); // lane
5931 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5932 TmpInst.addOperand(Inst.getOperand(5));
5933 Inst = TmpInst;
5934 return true;
5935 }
Jim Grosbachd3d36d92012-01-24 00:07:41 +00005936
5937 case ARM::VST3LNdWB_fixed_Asm_8:
5938 case ARM::VST3LNdWB_fixed_Asm_16:
5939 case ARM::VST3LNdWB_fixed_Asm_32:
5940 case ARM::VST3LNqWB_fixed_Asm_16:
5941 case ARM::VST3LNqWB_fixed_Asm_32: {
5942 MCInst TmpInst;
5943 // Shuffle the operands around so the lane index operand is in the
5944 // right place.
5945 unsigned Spacing;
5946 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5947 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5948 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5949 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5950 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5951 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5952 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5953 Spacing));
5954 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5955 Spacing * 2));
5956 TmpInst.addOperand(Inst.getOperand(1)); // lane
5957 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5958 TmpInst.addOperand(Inst.getOperand(5));
5959 Inst = TmpInst;
5960 return true;
5961 }
5962
Jim Grosbach8e2722c2012-01-24 18:53:13 +00005963 case ARM::VST4LNdWB_fixed_Asm_8:
5964 case ARM::VST4LNdWB_fixed_Asm_16:
5965 case ARM::VST4LNdWB_fixed_Asm_32:
5966 case ARM::VST4LNqWB_fixed_Asm_16:
5967 case ARM::VST4LNqWB_fixed_Asm_32: {
5968 MCInst TmpInst;
5969 // Shuffle the operands around so the lane index operand is in the
5970 // right place.
5971 unsigned Spacing;
5972 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5973 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5974 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5975 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5976 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5977 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5978 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5979 Spacing));
5980 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5981 Spacing * 2));
5982 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5983 Spacing * 3));
5984 TmpInst.addOperand(Inst.getOperand(1)); // lane
5985 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5986 TmpInst.addOperand(Inst.getOperand(5));
5987 Inst = TmpInst;
5988 return true;
5989 }
5990
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00005991 case ARM::VST1LNdAsm_8:
5992 case ARM::VST1LNdAsm_16:
5993 case ARM::VST1LNdAsm_32: {
Jim Grosbacheb538222011-12-02 22:34:51 +00005994 MCInst TmpInst;
5995 // Shuffle the operands around so the lane index operand is in the
5996 // right place.
Jim Grosbach2c590522011-12-20 20:46:29 +00005997 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00005998 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacheb538222011-12-02 22:34:51 +00005999 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6000 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6001 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6002 TmpInst.addOperand(Inst.getOperand(1)); // lane
6003 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6004 TmpInst.addOperand(Inst.getOperand(5));
6005 Inst = TmpInst;
6006 return true;
6007 }
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006008
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00006009 case ARM::VST2LNdAsm_8:
6010 case ARM::VST2LNdAsm_16:
6011 case ARM::VST2LNdAsm_32:
6012 case ARM::VST2LNqAsm_16:
6013 case ARM::VST2LNqAsm_32: {
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006014 MCInst TmpInst;
6015 // Shuffle the operands around so the lane index operand is in the
6016 // right place.
Jim Grosbach2c590522011-12-20 20:46:29 +00006017 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006018 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006019 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6020 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6021 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach2c590522011-12-20 20:46:29 +00006022 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6023 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006024 TmpInst.addOperand(Inst.getOperand(1)); // lane
6025 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6026 TmpInst.addOperand(Inst.getOperand(5));
6027 Inst = TmpInst;
6028 return true;
6029 }
Jim Grosbachd3d36d92012-01-24 00:07:41 +00006030
6031 case ARM::VST3LNdAsm_8:
6032 case ARM::VST3LNdAsm_16:
6033 case ARM::VST3LNdAsm_32:
6034 case ARM::VST3LNqAsm_16:
6035 case ARM::VST3LNqAsm_32: {
6036 MCInst TmpInst;
6037 // Shuffle the operands around so the lane index operand is in the
6038 // right place.
6039 unsigned Spacing;
6040 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6041 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6042 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6043 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6044 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6045 Spacing));
6046 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6047 Spacing * 2));
6048 TmpInst.addOperand(Inst.getOperand(1)); // lane
6049 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6050 TmpInst.addOperand(Inst.getOperand(5));
6051 Inst = TmpInst;
6052 return true;
6053 }
6054
Jim Grosbach8e2722c2012-01-24 18:53:13 +00006055 case ARM::VST4LNdAsm_8:
6056 case ARM::VST4LNdAsm_16:
6057 case ARM::VST4LNdAsm_32:
6058 case ARM::VST4LNqAsm_16:
6059 case ARM::VST4LNqAsm_32: {
6060 MCInst TmpInst;
6061 // Shuffle the operands around so the lane index operand is in the
6062 // right place.
6063 unsigned Spacing;
6064 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6065 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6066 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6067 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6068 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6069 Spacing));
6070 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6071 Spacing * 2));
6072 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6073 Spacing * 3));
6074 TmpInst.addOperand(Inst.getOperand(1)); // lane
6075 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6076 TmpInst.addOperand(Inst.getOperand(5));
6077 Inst = TmpInst;
6078 return true;
6079 }
6080
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006081 // Handle NEON VLD complex aliases.
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00006082 case ARM::VLD1LNdWB_register_Asm_8:
6083 case ARM::VLD1LNdWB_register_Asm_16:
6084 case ARM::VLD1LNdWB_register_Asm_32: {
Jim Grosbachdda976b2011-12-02 22:01:52 +00006085 MCInst TmpInst;
6086 // Shuffle the operands around so the lane index operand is in the
6087 // right place.
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006088 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006089 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbachdda976b2011-12-02 22:01:52 +00006090 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6091 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6092 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6093 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6094 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6095 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6096 TmpInst.addOperand(Inst.getOperand(1)); // lane
6097 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6098 TmpInst.addOperand(Inst.getOperand(6));
6099 Inst = TmpInst;
6100 return true;
6101 }
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006102
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00006103 case ARM::VLD2LNdWB_register_Asm_8:
6104 case ARM::VLD2LNdWB_register_Asm_16:
6105 case ARM::VLD2LNdWB_register_Asm_32:
6106 case ARM::VLD2LNqWB_register_Asm_16:
6107 case ARM::VLD2LNqWB_register_Asm_32: {
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006108 MCInst TmpInst;
6109 // Shuffle the operands around so the lane index operand is in the
6110 // right place.
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006111 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006112 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006113 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006114 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6115 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006116 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6117 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6118 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6119 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6120 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006121 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6122 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006123 TmpInst.addOperand(Inst.getOperand(1)); // lane
6124 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6125 TmpInst.addOperand(Inst.getOperand(6));
6126 Inst = TmpInst;
6127 return true;
6128 }
6129
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006130 case ARM::VLD3LNdWB_register_Asm_8:
6131 case ARM::VLD3LNdWB_register_Asm_16:
6132 case ARM::VLD3LNdWB_register_Asm_32:
6133 case ARM::VLD3LNqWB_register_Asm_16:
6134 case ARM::VLD3LNqWB_register_Asm_32: {
6135 MCInst TmpInst;
6136 // Shuffle the operands around so the lane index operand is in the
6137 // right place.
6138 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006139 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006140 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6142 Spacing));
6143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006144 Spacing * 2));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006145 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6146 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6147 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6148 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6149 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6150 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6151 Spacing));
6152 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006153 Spacing * 2));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006154 TmpInst.addOperand(Inst.getOperand(1)); // lane
6155 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6156 TmpInst.addOperand(Inst.getOperand(6));
6157 Inst = TmpInst;
6158 return true;
6159 }
6160
Jim Grosbach14952a02012-01-24 18:37:25 +00006161 case ARM::VLD4LNdWB_register_Asm_8:
6162 case ARM::VLD4LNdWB_register_Asm_16:
6163 case ARM::VLD4LNdWB_register_Asm_32:
6164 case ARM::VLD4LNqWB_register_Asm_16:
6165 case ARM::VLD4LNqWB_register_Asm_32: {
6166 MCInst TmpInst;
6167 // Shuffle the operands around so the lane index operand is in the
6168 // right place.
6169 unsigned Spacing;
6170 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6171 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6172 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6173 Spacing));
6174 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6175 Spacing * 2));
6176 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6177 Spacing * 3));
6178 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6179 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6180 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6181 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6182 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6183 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6184 Spacing));
6185 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6186 Spacing * 2));
6187 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6188 Spacing * 3));
6189 TmpInst.addOperand(Inst.getOperand(1)); // lane
6190 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6191 TmpInst.addOperand(Inst.getOperand(6));
6192 Inst = TmpInst;
6193 return true;
6194 }
6195
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00006196 case ARM::VLD1LNdWB_fixed_Asm_8:
6197 case ARM::VLD1LNdWB_fixed_Asm_16:
6198 case ARM::VLD1LNdWB_fixed_Asm_32: {
Jim Grosbachdda976b2011-12-02 22:01:52 +00006199 MCInst TmpInst;
6200 // Shuffle the operands around so the lane index operand is in the
6201 // right place.
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006202 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006203 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbachdda976b2011-12-02 22:01:52 +00006204 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6205 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6206 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6207 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6208 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6209 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6210 TmpInst.addOperand(Inst.getOperand(1)); // lane
6211 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6212 TmpInst.addOperand(Inst.getOperand(5));
6213 Inst = TmpInst;
6214 return true;
6215 }
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006216
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00006217 case ARM::VLD2LNdWB_fixed_Asm_8:
6218 case ARM::VLD2LNdWB_fixed_Asm_16:
6219 case ARM::VLD2LNdWB_fixed_Asm_32:
6220 case ARM::VLD2LNqWB_fixed_Asm_16:
6221 case ARM::VLD2LNqWB_fixed_Asm_32: {
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006222 MCInst TmpInst;
6223 // Shuffle the operands around so the lane index operand is in the
6224 // right place.
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006225 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006226 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006227 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006228 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6229 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006230 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6231 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6232 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6233 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6234 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006235 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6236 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006237 TmpInst.addOperand(Inst.getOperand(1)); // lane
6238 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6239 TmpInst.addOperand(Inst.getOperand(5));
6240 Inst = TmpInst;
6241 return true;
6242 }
6243
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006244 case ARM::VLD3LNdWB_fixed_Asm_8:
6245 case ARM::VLD3LNdWB_fixed_Asm_16:
6246 case ARM::VLD3LNdWB_fixed_Asm_32:
6247 case ARM::VLD3LNqWB_fixed_Asm_16:
6248 case ARM::VLD3LNqWB_fixed_Asm_32: {
6249 MCInst TmpInst;
6250 // Shuffle the operands around so the lane index operand is in the
6251 // right place.
6252 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006253 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006254 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6255 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6256 Spacing));
6257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006258 Spacing * 2));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006259 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6260 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6261 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6262 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6263 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6265 Spacing));
6266 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006267 Spacing * 2));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006268 TmpInst.addOperand(Inst.getOperand(1)); // lane
6269 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6270 TmpInst.addOperand(Inst.getOperand(5));
6271 Inst = TmpInst;
6272 return true;
6273 }
6274
Jim Grosbach14952a02012-01-24 18:37:25 +00006275 case ARM::VLD4LNdWB_fixed_Asm_8:
6276 case ARM::VLD4LNdWB_fixed_Asm_16:
6277 case ARM::VLD4LNdWB_fixed_Asm_32:
6278 case ARM::VLD4LNqWB_fixed_Asm_16:
6279 case ARM::VLD4LNqWB_fixed_Asm_32: {
6280 MCInst TmpInst;
6281 // Shuffle the operands around so the lane index operand is in the
6282 // right place.
6283 unsigned Spacing;
6284 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6285 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6286 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6287 Spacing));
6288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6289 Spacing * 2));
6290 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6291 Spacing * 3));
6292 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6293 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6294 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6295 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6296 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6297 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6298 Spacing));
6299 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6300 Spacing * 2));
6301 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302 Spacing * 3));
6303 TmpInst.addOperand(Inst.getOperand(1)); // lane
6304 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6305 TmpInst.addOperand(Inst.getOperand(5));
6306 Inst = TmpInst;
6307 return true;
6308 }
6309
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00006310 case ARM::VLD1LNdAsm_8:
6311 case ARM::VLD1LNdAsm_16:
6312 case ARM::VLD1LNdAsm_32: {
Jim Grosbach04945c42011-12-02 00:35:16 +00006313 MCInst TmpInst;
6314 // Shuffle the operands around so the lane index operand is in the
6315 // right place.
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006316 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006317 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach04945c42011-12-02 00:35:16 +00006318 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6319 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6320 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6321 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6322 TmpInst.addOperand(Inst.getOperand(1)); // lane
6323 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6324 TmpInst.addOperand(Inst.getOperand(5));
6325 Inst = TmpInst;
6326 return true;
6327 }
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006328
Jim Grosbachd28ef9a2012-01-23 19:39:08 +00006329 case ARM::VLD2LNdAsm_8:
6330 case ARM::VLD2LNdAsm_16:
6331 case ARM::VLD2LNdAsm_32:
6332 case ARM::VLD2LNqAsm_16:
6333 case ARM::VLD2LNqAsm_32: {
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006334 MCInst TmpInst;
6335 // Shuffle the operands around so the lane index operand is in the
6336 // right place.
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006337 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006338 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006339 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006340 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6341 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006342 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6343 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6344 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
Jim Grosbach75e2ab52011-12-20 19:21:26 +00006345 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6346 Spacing));
Jim Grosbacha8aa30b2011-12-14 23:25:46 +00006347 TmpInst.addOperand(Inst.getOperand(1)); // lane
6348 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6349 TmpInst.addOperand(Inst.getOperand(5));
6350 Inst = TmpInst;
6351 return true;
6352 }
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006353
6354 case ARM::VLD3LNdAsm_8:
6355 case ARM::VLD3LNdAsm_16:
6356 case ARM::VLD3LNdAsm_32:
6357 case ARM::VLD3LNqAsm_16:
6358 case ARM::VLD3LNqAsm_32: {
6359 MCInst TmpInst;
6360 // Shuffle the operands around so the lane index operand is in the
6361 // right place.
6362 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006363 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006364 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366 Spacing));
6367 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006368 Spacing * 2));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006369 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6370 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6371 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6372 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6373 Spacing));
6374 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006375 Spacing * 2));
Jim Grosbacha8b444b2012-01-23 21:53:26 +00006376 TmpInst.addOperand(Inst.getOperand(1)); // lane
6377 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6378 TmpInst.addOperand(Inst.getOperand(5));
6379 Inst = TmpInst;
6380 return true;
6381 }
6382
Jim Grosbach14952a02012-01-24 18:37:25 +00006383 case ARM::VLD4LNdAsm_8:
6384 case ARM::VLD4LNdAsm_16:
6385 case ARM::VLD4LNdAsm_32:
6386 case ARM::VLD4LNqAsm_16:
6387 case ARM::VLD4LNqAsm_32: {
6388 MCInst TmpInst;
6389 // Shuffle the operands around so the lane index operand is in the
6390 // right place.
6391 unsigned Spacing;
6392 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6393 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6394 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6395 Spacing));
6396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397 Spacing * 2));
6398 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6399 Spacing * 3));
6400 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6401 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6402 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6403 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404 Spacing));
6405 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6406 Spacing * 2));
6407 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6408 Spacing * 3));
6409 TmpInst.addOperand(Inst.getOperand(1)); // lane
6410 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6411 TmpInst.addOperand(Inst.getOperand(5));
6412 Inst = TmpInst;
6413 return true;
6414 }
6415
Jim Grosbachb78403c2012-01-24 23:47:04 +00006416 // VLD3DUP single 3-element structure to all lanes instructions.
6417 case ARM::VLD3DUPdAsm_8:
6418 case ARM::VLD3DUPdAsm_16:
6419 case ARM::VLD3DUPdAsm_32:
6420 case ARM::VLD3DUPqAsm_8:
6421 case ARM::VLD3DUPqAsm_16:
6422 case ARM::VLD3DUPqAsm_32: {
6423 MCInst TmpInst;
6424 unsigned Spacing;
6425 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6426 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6427 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6428 Spacing));
6429 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430 Spacing * 2));
6431 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6432 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6433 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6434 TmpInst.addOperand(Inst.getOperand(4));
6435 Inst = TmpInst;
6436 return true;
6437 }
6438
6439 case ARM::VLD3DUPdWB_fixed_Asm_8:
6440 case ARM::VLD3DUPdWB_fixed_Asm_16:
6441 case ARM::VLD3DUPdWB_fixed_Asm_32:
6442 case ARM::VLD3DUPqWB_fixed_Asm_8:
6443 case ARM::VLD3DUPqWB_fixed_Asm_16:
6444 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6445 MCInst TmpInst;
6446 unsigned Spacing;
6447 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6448 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6449 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6450 Spacing));
6451 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6452 Spacing * 2));
6453 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6454 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6455 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6456 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6457 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6458 TmpInst.addOperand(Inst.getOperand(4));
6459 Inst = TmpInst;
6460 return true;
6461 }
6462
6463 case ARM::VLD3DUPdWB_register_Asm_8:
6464 case ARM::VLD3DUPdWB_register_Asm_16:
6465 case ARM::VLD3DUPdWB_register_Asm_32:
6466 case ARM::VLD3DUPqWB_register_Asm_8:
6467 case ARM::VLD3DUPqWB_register_Asm_16:
6468 case ARM::VLD3DUPqWB_register_Asm_32: {
6469 MCInst TmpInst;
6470 unsigned Spacing;
6471 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6472 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474 Spacing));
6475 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6476 Spacing * 2));
6477 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6478 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6479 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6480 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6481 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6482 TmpInst.addOperand(Inst.getOperand(5));
6483 Inst = TmpInst;
6484 return true;
6485 }
6486
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006487 // VLD3 multiple 3-element structure instructions.
6488 case ARM::VLD3dAsm_8:
6489 case ARM::VLD3dAsm_16:
6490 case ARM::VLD3dAsm_32:
6491 case ARM::VLD3qAsm_8:
6492 case ARM::VLD3qAsm_16:
6493 case ARM::VLD3qAsm_32: {
6494 MCInst TmpInst;
6495 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006496 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006497 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6498 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6499 Spacing));
6500 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6501 Spacing * 2));
6502 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6503 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6504 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6505 TmpInst.addOperand(Inst.getOperand(4));
6506 Inst = TmpInst;
6507 return true;
6508 }
6509
6510 case ARM::VLD3dWB_fixed_Asm_8:
6511 case ARM::VLD3dWB_fixed_Asm_16:
6512 case ARM::VLD3dWB_fixed_Asm_32:
6513 case ARM::VLD3qWB_fixed_Asm_8:
6514 case ARM::VLD3qWB_fixed_Asm_16:
6515 case ARM::VLD3qWB_fixed_Asm_32: {
6516 MCInst TmpInst;
6517 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006518 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006519 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6520 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6521 Spacing));
6522 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6523 Spacing * 2));
6524 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6525 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6526 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6527 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6528 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6529 TmpInst.addOperand(Inst.getOperand(4));
6530 Inst = TmpInst;
6531 return true;
6532 }
6533
6534 case ARM::VLD3dWB_register_Asm_8:
6535 case ARM::VLD3dWB_register_Asm_16:
6536 case ARM::VLD3dWB_register_Asm_32:
6537 case ARM::VLD3qWB_register_Asm_8:
6538 case ARM::VLD3qWB_register_Asm_16:
6539 case ARM::VLD3qWB_register_Asm_32: {
6540 MCInst TmpInst;
6541 unsigned Spacing;
Jim Grosbach1a747242012-01-23 23:45:44 +00006542 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
Jim Grosbachac2af3f2012-01-23 23:20:46 +00006543 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545 Spacing));
6546 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6547 Spacing * 2));
6548 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6549 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6550 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6551 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6552 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6553 TmpInst.addOperand(Inst.getOperand(5));
6554 Inst = TmpInst;
6555 return true;
6556 }
6557
Jim Grosbach086cbfa2012-01-25 00:01:08 +00006558 // VLD4DUP single 3-element structure to all lanes instructions.
6559 case ARM::VLD4DUPdAsm_8:
6560 case ARM::VLD4DUPdAsm_16:
6561 case ARM::VLD4DUPdAsm_32:
6562 case ARM::VLD4DUPqAsm_8:
6563 case ARM::VLD4DUPqAsm_16:
6564 case ARM::VLD4DUPqAsm_32: {
6565 MCInst TmpInst;
6566 unsigned Spacing;
6567 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6568 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6569 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570 Spacing));
6571 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572 Spacing * 2));
6573 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574 Spacing * 3));
6575 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6576 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6577 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6578 TmpInst.addOperand(Inst.getOperand(4));
6579 Inst = TmpInst;
6580 return true;
6581 }
6582
6583 case ARM::VLD4DUPdWB_fixed_Asm_8:
6584 case ARM::VLD4DUPdWB_fixed_Asm_16:
6585 case ARM::VLD4DUPdWB_fixed_Asm_32:
6586 case ARM::VLD4DUPqWB_fixed_Asm_8:
6587 case ARM::VLD4DUPqWB_fixed_Asm_16:
6588 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6589 MCInst TmpInst;
6590 unsigned Spacing;
6591 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6592 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6593 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6594 Spacing));
6595 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6596 Spacing * 2));
6597 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6598 Spacing * 3));
6599 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6600 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6601 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6602 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6603 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6604 TmpInst.addOperand(Inst.getOperand(4));
6605 Inst = TmpInst;
6606 return true;
6607 }
6608
6609 case ARM::VLD4DUPdWB_register_Asm_8:
6610 case ARM::VLD4DUPdWB_register_Asm_16:
6611 case ARM::VLD4DUPdWB_register_Asm_32:
6612 case ARM::VLD4DUPqWB_register_Asm_8:
6613 case ARM::VLD4DUPqWB_register_Asm_16:
6614 case ARM::VLD4DUPqWB_register_Asm_32: {
6615 MCInst TmpInst;
6616 unsigned Spacing;
6617 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6618 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6619 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620 Spacing));
6621 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622 Spacing * 2));
6623 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6624 Spacing * 3));
6625 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6626 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6627 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6628 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6629 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6630 TmpInst.addOperand(Inst.getOperand(5));
6631 Inst = TmpInst;
6632 return true;
6633 }
6634
6635 // VLD4 multiple 4-element structure instructions.
Jim Grosbached561fc2012-01-24 00:43:17 +00006636 case ARM::VLD4dAsm_8:
6637 case ARM::VLD4dAsm_16:
6638 case ARM::VLD4dAsm_32:
6639 case ARM::VLD4qAsm_8:
6640 case ARM::VLD4qAsm_16:
6641 case ARM::VLD4qAsm_32: {
6642 MCInst TmpInst;
6643 unsigned Spacing;
6644 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6645 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6646 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6647 Spacing));
6648 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6649 Spacing * 2));
6650 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6651 Spacing * 3));
6652 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6653 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6654 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6655 TmpInst.addOperand(Inst.getOperand(4));
6656 Inst = TmpInst;
6657 return true;
6658 }
6659
6660 case ARM::VLD4dWB_fixed_Asm_8:
6661 case ARM::VLD4dWB_fixed_Asm_16:
6662 case ARM::VLD4dWB_fixed_Asm_32:
6663 case ARM::VLD4qWB_fixed_Asm_8:
6664 case ARM::VLD4qWB_fixed_Asm_16:
6665 case ARM::VLD4qWB_fixed_Asm_32: {
6666 MCInst TmpInst;
6667 unsigned Spacing;
6668 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6669 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6671 Spacing));
6672 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6673 Spacing * 2));
6674 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6675 Spacing * 3));
6676 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6677 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6678 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6679 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6680 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6681 TmpInst.addOperand(Inst.getOperand(4));
6682 Inst = TmpInst;
6683 return true;
6684 }
6685
6686 case ARM::VLD4dWB_register_Asm_8:
6687 case ARM::VLD4dWB_register_Asm_16:
6688 case ARM::VLD4dWB_register_Asm_32:
6689 case ARM::VLD4qWB_register_Asm_8:
6690 case ARM::VLD4qWB_register_Asm_16:
6691 case ARM::VLD4qWB_register_Asm_32: {
6692 MCInst TmpInst;
6693 unsigned Spacing;
6694 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6695 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6697 Spacing));
6698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6699 Spacing * 2));
6700 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6701 Spacing * 3));
6702 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6703 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6704 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6705 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6706 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6707 TmpInst.addOperand(Inst.getOperand(5));
6708 Inst = TmpInst;
6709 return true;
6710 }
6711
Jim Grosbach1a747242012-01-23 23:45:44 +00006712 // VST3 multiple 3-element structure instructions.
6713 case ARM::VST3dAsm_8:
6714 case ARM::VST3dAsm_16:
6715 case ARM::VST3dAsm_32:
6716 case ARM::VST3qAsm_8:
6717 case ARM::VST3qAsm_16:
6718 case ARM::VST3qAsm_32: {
6719 MCInst TmpInst;
6720 unsigned Spacing;
6721 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6722 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6723 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6724 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6726 Spacing));
6727 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6728 Spacing * 2));
6729 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6730 TmpInst.addOperand(Inst.getOperand(4));
6731 Inst = TmpInst;
6732 return true;
6733 }
6734
6735 case ARM::VST3dWB_fixed_Asm_8:
6736 case ARM::VST3dWB_fixed_Asm_16:
6737 case ARM::VST3dWB_fixed_Asm_32:
6738 case ARM::VST3qWB_fixed_Asm_8:
6739 case ARM::VST3qWB_fixed_Asm_16:
6740 case ARM::VST3qWB_fixed_Asm_32: {
6741 MCInst TmpInst;
6742 unsigned Spacing;
6743 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6744 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6745 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6746 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6747 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6748 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6749 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6750 Spacing));
6751 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6752 Spacing * 2));
6753 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6754 TmpInst.addOperand(Inst.getOperand(4));
6755 Inst = TmpInst;
6756 return true;
6757 }
6758
6759 case ARM::VST3dWB_register_Asm_8:
6760 case ARM::VST3dWB_register_Asm_16:
6761 case ARM::VST3dWB_register_Asm_32:
6762 case ARM::VST3qWB_register_Asm_8:
6763 case ARM::VST3qWB_register_Asm_16:
6764 case ARM::VST3qWB_register_Asm_32: {
6765 MCInst TmpInst;
6766 unsigned Spacing;
6767 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6768 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6769 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6770 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6771 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6772 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6773 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6774 Spacing));
6775 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6776 Spacing * 2));
6777 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6778 TmpInst.addOperand(Inst.getOperand(5));
6779 Inst = TmpInst;
6780 return true;
6781 }
6782
Jim Grosbachda70eac2012-01-24 00:58:13 +00006783 // VST4 multiple 3-element structure instructions.
6784 case ARM::VST4dAsm_8:
6785 case ARM::VST4dAsm_16:
6786 case ARM::VST4dAsm_32:
6787 case ARM::VST4qAsm_8:
6788 case ARM::VST4qAsm_16:
6789 case ARM::VST4qAsm_32: {
6790 MCInst TmpInst;
6791 unsigned Spacing;
6792 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6793 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6794 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6795 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6796 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6797 Spacing));
6798 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6799 Spacing * 2));
6800 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6801 Spacing * 3));
6802 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6803 TmpInst.addOperand(Inst.getOperand(4));
6804 Inst = TmpInst;
6805 return true;
6806 }
6807
6808 case ARM::VST4dWB_fixed_Asm_8:
6809 case ARM::VST4dWB_fixed_Asm_16:
6810 case ARM::VST4dWB_fixed_Asm_32:
6811 case ARM::VST4qWB_fixed_Asm_8:
6812 case ARM::VST4qWB_fixed_Asm_16:
6813 case ARM::VST4qWB_fixed_Asm_32: {
6814 MCInst TmpInst;
6815 unsigned Spacing;
6816 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6817 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6818 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6819 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6820 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6821 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6822 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6823 Spacing));
6824 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6825 Spacing * 2));
6826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6827 Spacing * 3));
6828 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6829 TmpInst.addOperand(Inst.getOperand(4));
6830 Inst = TmpInst;
6831 return true;
6832 }
6833
6834 case ARM::VST4dWB_register_Asm_8:
6835 case ARM::VST4dWB_register_Asm_16:
6836 case ARM::VST4dWB_register_Asm_32:
6837 case ARM::VST4qWB_register_Asm_8:
6838 case ARM::VST4qWB_register_Asm_16:
6839 case ARM::VST4qWB_register_Asm_32: {
6840 MCInst TmpInst;
6841 unsigned Spacing;
6842 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6843 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6844 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6845 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6846 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6847 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6848 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6849 Spacing));
6850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6851 Spacing * 2));
6852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6853 Spacing * 3));
6854 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6855 TmpInst.addOperand(Inst.getOperand(5));
6856 Inst = TmpInst;
6857 return true;
6858 }
6859
Jim Grosbachad66de12012-04-11 00:15:16 +00006860 // Handle encoding choice for the shift-immediate instructions.
6861 case ARM::t2LSLri:
6862 case ARM::t2LSRri:
6863 case ARM::t2ASRri: {
6864 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6865 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6866 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6867 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6868 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6869 unsigned NewOpc;
6870 switch (Inst.getOpcode()) {
6871 default: llvm_unreachable("unexpected opcode");
6872 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6873 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6874 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6875 }
6876 // The Thumb1 operands aren't in the same order. Awesome, eh?
6877 MCInst TmpInst;
6878 TmpInst.setOpcode(NewOpc);
6879 TmpInst.addOperand(Inst.getOperand(0));
6880 TmpInst.addOperand(Inst.getOperand(5));
6881 TmpInst.addOperand(Inst.getOperand(1));
6882 TmpInst.addOperand(Inst.getOperand(2));
6883 TmpInst.addOperand(Inst.getOperand(3));
6884 TmpInst.addOperand(Inst.getOperand(4));
6885 Inst = TmpInst;
6886 return true;
6887 }
6888 return false;
6889 }
6890
Jim Grosbach485e5622011-12-13 22:45:11 +00006891 // Handle the Thumb2 mode MOV complex aliases.
Jim Grosbachb3ef7132011-12-21 20:54:00 +00006892 case ARM::t2MOVsr:
6893 case ARM::t2MOVSsr: {
6894 // Which instruction to expand to depends on the CCOut operand and
6895 // whether we're in an IT block if the register operands are low
6896 // registers.
6897 bool isNarrow = false;
6898 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6899 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6900 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6901 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6902 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6903 isNarrow = true;
6904 MCInst TmpInst;
6905 unsigned newOpc;
6906 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6907 default: llvm_unreachable("unexpected opcode!");
6908 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6909 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6910 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6911 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6912 }
6913 TmpInst.setOpcode(newOpc);
6914 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6915 if (isNarrow)
6916 TmpInst.addOperand(MCOperand::CreateReg(
6917 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6918 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6919 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6920 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6921 TmpInst.addOperand(Inst.getOperand(5));
6922 if (!isNarrow)
6923 TmpInst.addOperand(MCOperand::CreateReg(
6924 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6925 Inst = TmpInst;
6926 return true;
6927 }
Jim Grosbach485e5622011-12-13 22:45:11 +00006928 case ARM::t2MOVsi:
6929 case ARM::t2MOVSsi: {
6930 // Which instruction to expand to depends on the CCOut operand and
6931 // whether we're in an IT block if the register operands are low
6932 // registers.
6933 bool isNarrow = false;
6934 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6935 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6936 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6937 isNarrow = true;
6938 MCInst TmpInst;
6939 unsigned newOpc;
6940 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6941 default: llvm_unreachable("unexpected opcode!");
6942 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6943 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6944 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6945 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
Jim Grosbach8c59bbc2011-12-21 21:04:19 +00006946 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
Jim Grosbach485e5622011-12-13 22:45:11 +00006947 }
Benjamin Kramerbde91762012-06-02 10:20:22 +00006948 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6949 if (Amount == 32) Amount = 0;
Jim Grosbach485e5622011-12-13 22:45:11 +00006950 TmpInst.setOpcode(newOpc);
6951 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6952 if (isNarrow)
6953 TmpInst.addOperand(MCOperand::CreateReg(
6954 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6955 TmpInst.addOperand(Inst.getOperand(1)); // Rn
Jim Grosbach8c59bbc2011-12-21 21:04:19 +00006956 if (newOpc != ARM::t2RRX)
Benjamin Kramerbde91762012-06-02 10:20:22 +00006957 TmpInst.addOperand(MCOperand::CreateImm(Amount));
Jim Grosbach485e5622011-12-13 22:45:11 +00006958 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6959 TmpInst.addOperand(Inst.getOperand(4));
6960 if (!isNarrow)
6961 TmpInst.addOperand(MCOperand::CreateReg(
6962 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6963 Inst = TmpInst;
6964 return true;
6965 }
6966 // Handle the ARM mode MOV complex aliases.
Jim Grosbachabcac562011-11-16 18:31:45 +00006967 case ARM::ASRr:
6968 case ARM::LSRr:
6969 case ARM::LSLr:
6970 case ARM::RORr: {
6971 ARM_AM::ShiftOpc ShiftTy;
6972 switch(Inst.getOpcode()) {
6973 default: llvm_unreachable("unexpected opcode!");
6974 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6975 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6976 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6977 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6978 }
Jim Grosbachabcac562011-11-16 18:31:45 +00006979 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6980 MCInst TmpInst;
6981 TmpInst.setOpcode(ARM::MOVsr);
6982 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6983 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6984 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6985 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6986 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6987 TmpInst.addOperand(Inst.getOperand(4));
6988 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6989 Inst = TmpInst;
6990 return true;
6991 }
Jim Grosbachc14871c2011-11-10 19:18:01 +00006992 case ARM::ASRi:
6993 case ARM::LSRi:
6994 case ARM::LSLi:
6995 case ARM::RORi: {
6996 ARM_AM::ShiftOpc ShiftTy;
Jim Grosbachc14871c2011-11-10 19:18:01 +00006997 switch(Inst.getOpcode()) {
6998 default: llvm_unreachable("unexpected opcode!");
6999 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7000 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7001 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7002 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7003 }
7004 // A shift by zero is a plain MOVr, not a MOVsi.
Jim Grosbach1a2f9ee2011-11-16 19:05:59 +00007005 unsigned Amt = Inst.getOperand(2).getImm();
Jim Grosbachc14871c2011-11-10 19:18:01 +00007006 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
Richard Bartonba5b0cc2012-04-25 18:00:18 +00007007 // A shift by 32 should be encoded as 0 when permitted
7008 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7009 Amt = 0;
Jim Grosbachc14871c2011-11-10 19:18:01 +00007010 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
Jim Grosbach61db5a52011-11-10 16:44:55 +00007011 MCInst TmpInst;
Jim Grosbachc14871c2011-11-10 19:18:01 +00007012 TmpInst.setOpcode(Opc);
Jim Grosbach61db5a52011-11-10 16:44:55 +00007013 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7014 TmpInst.addOperand(Inst.getOperand(1)); // Rn
Jim Grosbachc14871c2011-11-10 19:18:01 +00007015 if (Opc == ARM::MOVsi)
7016 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
Jim Grosbach61db5a52011-11-10 16:44:55 +00007017 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7018 TmpInst.addOperand(Inst.getOperand(4));
7019 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7020 Inst = TmpInst;
Jim Grosbachafad0532011-11-10 23:42:14 +00007021 return true;
Jim Grosbach61db5a52011-11-10 16:44:55 +00007022 }
Jim Grosbach1a2f9ee2011-11-16 19:05:59 +00007023 case ARM::RRXi: {
7024 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7025 MCInst TmpInst;
7026 TmpInst.setOpcode(ARM::MOVsi);
7027 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7028 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7029 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7030 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7031 TmpInst.addOperand(Inst.getOperand(3));
7032 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7033 Inst = TmpInst;
7034 return true;
7035 }
Jim Grosbachd9a9be22011-11-10 23:58:34 +00007036 case ARM::t2LDMIA_UPD: {
7037 // If this is a load of a single register, then we should use
7038 // a post-indexed LDR instruction instead, per the ARM ARM.
7039 if (Inst.getNumOperands() != 5)
7040 return false;
7041 MCInst TmpInst;
7042 TmpInst.setOpcode(ARM::t2LDR_POST);
7043 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7044 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7045 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7046 TmpInst.addOperand(MCOperand::CreateImm(4));
7047 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7048 TmpInst.addOperand(Inst.getOperand(3));
7049 Inst = TmpInst;
7050 return true;
7051 }
7052 case ARM::t2STMDB_UPD: {
7053 // If this is a store of a single register, then we should use
7054 // a pre-indexed STR instruction instead, per the ARM ARM.
7055 if (Inst.getNumOperands() != 5)
7056 return false;
7057 MCInst TmpInst;
7058 TmpInst.setOpcode(ARM::t2STR_PRE);
7059 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7060 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7061 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7062 TmpInst.addOperand(MCOperand::CreateImm(-4));
7063 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7064 TmpInst.addOperand(Inst.getOperand(3));
7065 Inst = TmpInst;
7066 return true;
7067 }
Jim Grosbach8ba76c62011-08-11 17:35:48 +00007068 case ARM::LDMIA_UPD:
7069 // If this is a load of a single register via a 'pop', then we should use
7070 // a post-indexed LDR instruction instead, per the ARM ARM.
7071 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7072 Inst.getNumOperands() == 5) {
7073 MCInst TmpInst;
7074 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7075 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7076 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7077 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7078 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7079 TmpInst.addOperand(MCOperand::CreateImm(4));
7080 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7081 TmpInst.addOperand(Inst.getOperand(3));
7082 Inst = TmpInst;
Jim Grosbachafad0532011-11-10 23:42:14 +00007083 return true;
Jim Grosbach8ba76c62011-08-11 17:35:48 +00007084 }
7085 break;
Jim Grosbach27ad83d2011-08-11 18:07:11 +00007086 case ARM::STMDB_UPD:
7087 // If this is a store of a single register via a 'push', then we should use
7088 // a pre-indexed STR instruction instead, per the ARM ARM.
7089 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7090 Inst.getNumOperands() == 5) {
7091 MCInst TmpInst;
7092 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7093 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7094 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7095 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7096 TmpInst.addOperand(MCOperand::CreateImm(-4));
7097 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7098 TmpInst.addOperand(Inst.getOperand(3));
7099 Inst = TmpInst;
7100 }
7101 break;
Jim Grosbachec9ba982011-12-05 21:06:26 +00007102 case ARM::t2ADDri12:
7103 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7104 // mnemonic was used (not "addw"), encoding T3 is preferred.
7105 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7106 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7107 break;
7108 Inst.setOpcode(ARM::t2ADDri);
7109 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7110 break;
7111 case ARM::t2SUBri12:
7112 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7113 // mnemonic was used (not "subw"), encoding T3 is preferred.
7114 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7115 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7116 break;
7117 Inst.setOpcode(ARM::t2SUBri);
7118 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7119 break;
Jim Grosbache9ab47a2011-08-16 23:57:34 +00007120 case ARM::tADDi8:
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +00007121 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
Jim Grosbach6d606fb2011-08-31 17:07:33 +00007122 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7123 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7124 // to encoding T1 if <Rd> is omitted."
Jim Grosbach199ab902012-03-30 16:31:31 +00007125 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
Jim Grosbache9ab47a2011-08-16 23:57:34 +00007126 Inst.setOpcode(ARM::tADDi3);
Jim Grosbachafad0532011-11-10 23:42:14 +00007127 return true;
7128 }
Jim Grosbache9ab47a2011-08-16 23:57:34 +00007129 break;
Jim Grosbachd0c435c2011-09-16 22:58:42 +00007130 case ARM::tSUBi8:
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +00007131 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
Jim Grosbachd0c435c2011-09-16 22:58:42 +00007132 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7133 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7134 // to encoding T1 if <Rd> is omitted."
Jim Grosbach199ab902012-03-30 16:31:31 +00007135 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
Jim Grosbachd0c435c2011-09-16 22:58:42 +00007136 Inst.setOpcode(ARM::tSUBi3);
Jim Grosbachafad0532011-11-10 23:42:14 +00007137 return true;
7138 }
Jim Grosbachd0c435c2011-09-16 22:58:42 +00007139 break;
Jim Grosbachdef5e342012-03-30 17:20:40 +00007140 case ARM::t2ADDri:
7141 case ARM::t2SUBri: {
7142 // If the destination and first source operand are the same, and
7143 // the flags are compatible with the current IT status, use encoding T2
7144 // instead of T3. For compatibility with the system 'as'. Make sure the
7145 // wide encoding wasn't explicit.
7146 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
Jim Grosbach74005ae2012-03-30 18:39:43 +00007147 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
Jim Grosbachdef5e342012-03-30 17:20:40 +00007148 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7149 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7150 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7151 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7152 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7153 break;
7154 MCInst TmpInst;
7155 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7156 ARM::tADDi8 : ARM::tSUBi8);
7157 TmpInst.addOperand(Inst.getOperand(0));
7158 TmpInst.addOperand(Inst.getOperand(5));
7159 TmpInst.addOperand(Inst.getOperand(0));
7160 TmpInst.addOperand(Inst.getOperand(2));
7161 TmpInst.addOperand(Inst.getOperand(3));
7162 TmpInst.addOperand(Inst.getOperand(4));
7163 Inst = TmpInst;
7164 return true;
7165 }
Jim Grosbache489bab2011-12-05 22:16:39 +00007166 case ARM::t2ADDrr: {
7167 // If the destination and first source operand are the same, and
7168 // there's no setting of the flags, use encoding T2 instead of T3.
7169 // Note that this is only for ADD, not SUB. This mirrors the system
7170 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7171 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7172 Inst.getOperand(5).getReg() != 0 ||
Jim Grosbachb8c719c2011-12-05 22:27:04 +00007173 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7174 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
Jim Grosbache489bab2011-12-05 22:16:39 +00007175 break;
7176 MCInst TmpInst;
7177 TmpInst.setOpcode(ARM::tADDhirr);
7178 TmpInst.addOperand(Inst.getOperand(0));
7179 TmpInst.addOperand(Inst.getOperand(0));
7180 TmpInst.addOperand(Inst.getOperand(2));
7181 TmpInst.addOperand(Inst.getOperand(3));
7182 TmpInst.addOperand(Inst.getOperand(4));
7183 Inst = TmpInst;
7184 return true;
7185 }
Jim Grosbachc6f32b32012-04-27 23:51:36 +00007186 case ARM::tADDrSP: {
7187 // If the non-SP source operand and the destination operand are not the
7188 // same, we need to use the 32-bit encoding if it's available.
7189 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7190 Inst.setOpcode(ARM::t2ADDrr);
7191 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7192 return true;
7193 }
7194 break;
7195 }
Owen Anderson29cfe6c2011-09-09 21:48:23 +00007196 case ARM::tB:
7197 // A Thumb conditional branch outside of an IT block is a tBcc.
Jim Grosbachafad0532011-11-10 23:42:14 +00007198 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
Owen Anderson29cfe6c2011-09-09 21:48:23 +00007199 Inst.setOpcode(ARM::tBcc);
Jim Grosbachafad0532011-11-10 23:42:14 +00007200 return true;
7201 }
Owen Anderson29cfe6c2011-09-09 21:48:23 +00007202 break;
7203 case ARM::t2B:
7204 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
Jim Grosbachafad0532011-11-10 23:42:14 +00007205 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
Owen Anderson29cfe6c2011-09-09 21:48:23 +00007206 Inst.setOpcode(ARM::t2Bcc);
Jim Grosbachafad0532011-11-10 23:42:14 +00007207 return true;
7208 }
Owen Anderson29cfe6c2011-09-09 21:48:23 +00007209 break;
Jim Grosbach99bc8462011-08-31 21:17:31 +00007210 case ARM::t2Bcc:
Jim Grosbacha0d34d32011-09-02 23:22:08 +00007211 // If the conditional is AL or we're in an IT block, we really want t2B.
Jim Grosbachafad0532011-11-10 23:42:14 +00007212 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
Jim Grosbach99bc8462011-08-31 21:17:31 +00007213 Inst.setOpcode(ARM::t2B);
Jim Grosbachafad0532011-11-10 23:42:14 +00007214 return true;
7215 }
Jim Grosbach99bc8462011-08-31 21:17:31 +00007216 break;
Jim Grosbachcbd4ab12011-08-17 22:57:40 +00007217 case ARM::tBcc:
7218 // If the conditional is AL, we really want tB.
Jim Grosbachafad0532011-11-10 23:42:14 +00007219 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
Jim Grosbachcbd4ab12011-08-17 22:57:40 +00007220 Inst.setOpcode(ARM::tB);
Jim Grosbachafad0532011-11-10 23:42:14 +00007221 return true;
7222 }
Jim Grosbach6ddb5682011-08-18 16:08:39 +00007223 break;
Jim Grosbacha31f2232011-09-07 18:05:34 +00007224 case ARM::tLDMIA: {
7225 // If the register list contains any high registers, or if the writeback
7226 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7227 // instead if we're in Thumb2. Otherwise, this should have generated
7228 // an error in validateInstruction().
7229 unsigned Rn = Inst.getOperand(0).getReg();
7230 bool hasWritebackToken =
7231 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7232 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7233 bool listContainsBase;
7234 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7235 (!listContainsBase && !hasWritebackToken) ||
7236 (listContainsBase && hasWritebackToken)) {
7237 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7238 assert (isThumbTwo());
7239 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7240 // If we're switching to the updating version, we need to insert
7241 // the writeback tied operand.
7242 if (hasWritebackToken)
7243 Inst.insert(Inst.begin(),
7244 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
Jim Grosbachafad0532011-11-10 23:42:14 +00007245 return true;
Jim Grosbacha31f2232011-09-07 18:05:34 +00007246 }
7247 break;
7248 }
Jim Grosbach099c9762011-09-16 20:50:13 +00007249 case ARM::tSTMIA_UPD: {
7250 // If the register list contains any high registers, we need to use
7251 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7252 // should have generated an error in validateInstruction().
7253 unsigned Rn = Inst.getOperand(0).getReg();
7254 bool listContainsBase;
7255 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7256 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7257 assert (isThumbTwo());
7258 Inst.setOpcode(ARM::t2STMIA_UPD);
Jim Grosbachafad0532011-11-10 23:42:14 +00007259 return true;
Jim Grosbach099c9762011-09-16 20:50:13 +00007260 }
7261 break;
7262 }
Jim Grosbach9bded9d2011-11-10 23:17:11 +00007263 case ARM::tPOP: {
7264 bool listContainsBase;
7265 // If the register list contains any high registers, we need to use
7266 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7267 // should have generated an error in validateInstruction().
7268 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
Jim Grosbachafad0532011-11-10 23:42:14 +00007269 return false;
Jim Grosbach9bded9d2011-11-10 23:17:11 +00007270 assert (isThumbTwo());
7271 Inst.setOpcode(ARM::t2LDMIA_UPD);
7272 // Add the base register and writeback operands.
7273 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7274 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
Jim Grosbachafad0532011-11-10 23:42:14 +00007275 return true;
Jim Grosbach9bded9d2011-11-10 23:17:11 +00007276 }
7277 case ARM::tPUSH: {
7278 bool listContainsBase;
7279 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
Jim Grosbachafad0532011-11-10 23:42:14 +00007280 return false;
Jim Grosbach9bded9d2011-11-10 23:17:11 +00007281 assert (isThumbTwo());
7282 Inst.setOpcode(ARM::t2STMDB_UPD);
7283 // Add the base register and writeback operands.
7284 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7285 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
Jim Grosbachafad0532011-11-10 23:42:14 +00007286 return true;
Jim Grosbach9bded9d2011-11-10 23:17:11 +00007287 }
Jim Grosbachb908b7a2011-09-10 00:15:36 +00007288 case ARM::t2MOVi: {
7289 // If we can use the 16-bit encoding and the user didn't explicitly
7290 // request the 32-bit variant, transform it here.
7291 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
Jim Grosbach199ab902012-03-30 16:31:31 +00007292 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
Jim Grosbach18b8b172011-09-14 19:12:11 +00007293 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7294 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7295 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
Jim Grosbachb908b7a2011-09-10 00:15:36 +00007296 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7297 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7298 // The operands aren't in the same order for tMOVi8...
7299 MCInst TmpInst;
7300 TmpInst.setOpcode(ARM::tMOVi8);
7301 TmpInst.addOperand(Inst.getOperand(0));
7302 TmpInst.addOperand(Inst.getOperand(4));
7303 TmpInst.addOperand(Inst.getOperand(1));
7304 TmpInst.addOperand(Inst.getOperand(2));
7305 TmpInst.addOperand(Inst.getOperand(3));
7306 Inst = TmpInst;
Jim Grosbachafad0532011-11-10 23:42:14 +00007307 return true;
Jim Grosbachb908b7a2011-09-10 00:15:36 +00007308 }
7309 break;
7310 }
7311 case ARM::t2MOVr: {
7312 // If we can use the 16-bit encoding and the user didn't explicitly
7313 // request the 32-bit variant, transform it here.
7314 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7315 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7316 Inst.getOperand(2).getImm() == ARMCC::AL &&
7317 Inst.getOperand(4).getReg() == ARM::CPSR &&
7318 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7319 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7320 // The operands aren't the same for tMOV[S]r... (no cc_out)
7321 MCInst TmpInst;
7322 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7323 TmpInst.addOperand(Inst.getOperand(0));
7324 TmpInst.addOperand(Inst.getOperand(1));
7325 TmpInst.addOperand(Inst.getOperand(2));
7326 TmpInst.addOperand(Inst.getOperand(3));
7327 Inst = TmpInst;
Jim Grosbachafad0532011-11-10 23:42:14 +00007328 return true;
Jim Grosbachb908b7a2011-09-10 00:15:36 +00007329 }
7330 break;
7331 }
Jim Grosbach82213192011-09-19 20:29:33 +00007332 case ARM::t2SXTH:
Jim Grosbachb3519802011-09-20 00:46:54 +00007333 case ARM::t2SXTB:
7334 case ARM::t2UXTH:
7335 case ARM::t2UXTB: {
Jim Grosbach82213192011-09-19 20:29:33 +00007336 // If we can use the 16-bit encoding and the user didn't explicitly
7337 // request the 32-bit variant, transform it here.
7338 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7339 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7340 Inst.getOperand(2).getImm() == 0 &&
7341 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7342 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
Jim Grosbachb3519802011-09-20 00:46:54 +00007343 unsigned NewOpc;
7344 switch (Inst.getOpcode()) {
7345 default: llvm_unreachable("Illegal opcode!");
7346 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7347 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7348 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7349 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7350 }
Jim Grosbach82213192011-09-19 20:29:33 +00007351 // The operands aren't the same for thumb1 (no rotate operand).
7352 MCInst TmpInst;
7353 TmpInst.setOpcode(NewOpc);
7354 TmpInst.addOperand(Inst.getOperand(0));
7355 TmpInst.addOperand(Inst.getOperand(1));
7356 TmpInst.addOperand(Inst.getOperand(3));
7357 TmpInst.addOperand(Inst.getOperand(4));
7358 Inst = TmpInst;
Jim Grosbachafad0532011-11-10 23:42:14 +00007359 return true;
Jim Grosbach82213192011-09-19 20:29:33 +00007360 }
7361 break;
7362 }
Jim Grosbache2ca9e52011-12-20 00:59:38 +00007363 case ARM::MOVsi: {
7364 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
Richard Bartonba5b0cc2012-04-25 18:00:18 +00007365 // rrx shifts and asr/lsr of #32 is encoded as 0
7366 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7367 return false;
Jim Grosbache2ca9e52011-12-20 00:59:38 +00007368 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7369 // Shifting by zero is accepted as a vanilla 'MOVr'
7370 MCInst TmpInst;
7371 TmpInst.setOpcode(ARM::MOVr);
7372 TmpInst.addOperand(Inst.getOperand(0));
7373 TmpInst.addOperand(Inst.getOperand(1));
7374 TmpInst.addOperand(Inst.getOperand(3));
7375 TmpInst.addOperand(Inst.getOperand(4));
7376 TmpInst.addOperand(Inst.getOperand(5));
7377 Inst = TmpInst;
7378 return true;
7379 }
7380 return false;
7381 }
Jim Grosbach12ccf452011-12-22 18:04:04 +00007382 case ARM::ANDrsi:
7383 case ARM::ORRrsi:
7384 case ARM::EORrsi:
7385 case ARM::BICrsi:
7386 case ARM::SUBrsi:
7387 case ARM::ADDrsi: {
7388 unsigned newOpc;
7389 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7390 if (SOpc == ARM_AM::rrx) return false;
7391 switch (Inst.getOpcode()) {
Craig Toppere55c5562012-02-07 02:50:20 +00007392 default: llvm_unreachable("unexpected opcode!");
Jim Grosbach12ccf452011-12-22 18:04:04 +00007393 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7394 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7395 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7396 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7397 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7398 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7399 }
7400 // If the shift is by zero, use the non-shifted instruction definition.
Richard Barton35aceb82012-07-09 16:31:14 +00007401 // The exception is for right shifts, where 0 == 32
7402 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7403 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
Jim Grosbach12ccf452011-12-22 18:04:04 +00007404 MCInst TmpInst;
7405 TmpInst.setOpcode(newOpc);
7406 TmpInst.addOperand(Inst.getOperand(0));
7407 TmpInst.addOperand(Inst.getOperand(1));
7408 TmpInst.addOperand(Inst.getOperand(2));
7409 TmpInst.addOperand(Inst.getOperand(4));
7410 TmpInst.addOperand(Inst.getOperand(5));
7411 TmpInst.addOperand(Inst.getOperand(6));
7412 Inst = TmpInst;
7413 return true;
7414 }
7415 return false;
7416 }
Jim Grosbach82f76d12012-01-25 19:52:01 +00007417 case ARM::ITasm:
Jim Grosbach3d1eac82011-08-26 21:43:41 +00007418 case ARM::t2IT: {
7419 // The mask bits for all but the first condition are represented as
7420 // the low bit of the condition code value implies 't'. We currently
7421 // always have 1 implies 't', so XOR toggle the bits if the low bit
Richard Bartonf435b092012-04-27 08:42:59 +00007422 // of the condition code is zero.
Jim Grosbach3d1eac82011-08-26 21:43:41 +00007423 MCOperand &MO = Inst.getOperand(1);
7424 unsigned Mask = MO.getImm();
Jim Grosbached16ec42011-08-29 22:24:09 +00007425 unsigned OrigMask = Mask;
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +00007426 unsigned TZ = countTrailingZeros(Mask);
Jim Grosbach3d1eac82011-08-26 21:43:41 +00007427 if ((Inst.getOperand(0).getImm() & 1) == 0) {
Jim Grosbach3d1eac82011-08-26 21:43:41 +00007428 assert(Mask && TZ <= 3 && "illegal IT mask value!");
Benjamin Kramer8bad66e2013-05-19 22:01:57 +00007429 Mask ^= (0xE << TZ) & 0xF;
Richard Bartonf435b092012-04-27 08:42:59 +00007430 }
Jim Grosbach3d1eac82011-08-26 21:43:41 +00007431 MO.setImm(Mask);
Jim Grosbached16ec42011-08-29 22:24:09 +00007432
7433 // Set up the IT block state according to the IT instruction we just
7434 // matched.
7435 assert(!inITBlock() && "nested IT blocks?!");
7436 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7437 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7438 ITState.CurPosition = 0;
7439 ITState.FirstCond = true;
Jim Grosbach3d1eac82011-08-26 21:43:41 +00007440 break;
7441 }
Richard Bartona39625e2012-07-09 16:12:24 +00007442 case ARM::t2LSLrr:
7443 case ARM::t2LSRrr:
7444 case ARM::t2ASRrr:
7445 case ARM::t2SBCrr:
7446 case ARM::t2RORrr:
7447 case ARM::t2BICrr:
7448 {
Richard Bartond5660372012-07-09 16:14:28 +00007449 // Assemblers should use the narrow encodings of these instructions when permissible.
Richard Bartona39625e2012-07-09 16:12:24 +00007450 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7451 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7452 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
Richard Barton984d0ba2012-07-09 18:30:56 +00007453 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7454 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
Richard Bartona39625e2012-07-09 16:12:24 +00007455 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7456 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7457 unsigned NewOpc;
7458 switch (Inst.getOpcode()) {
7459 default: llvm_unreachable("unexpected opcode");
7460 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7461 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7462 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7463 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7464 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7465 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7466 }
7467 MCInst TmpInst;
7468 TmpInst.setOpcode(NewOpc);
7469 TmpInst.addOperand(Inst.getOperand(0));
7470 TmpInst.addOperand(Inst.getOperand(5));
7471 TmpInst.addOperand(Inst.getOperand(1));
7472 TmpInst.addOperand(Inst.getOperand(2));
7473 TmpInst.addOperand(Inst.getOperand(3));
7474 TmpInst.addOperand(Inst.getOperand(4));
7475 Inst = TmpInst;
7476 return true;
7477 }
7478 return false;
7479 }
7480 case ARM::t2ANDrr:
7481 case ARM::t2EORrr:
7482 case ARM::t2ADCrr:
7483 case ARM::t2ORRrr:
7484 {
Richard Bartond5660372012-07-09 16:14:28 +00007485 // Assemblers should use the narrow encodings of these instructions when permissible.
Richard Bartona39625e2012-07-09 16:12:24 +00007486 // These instructions are special in that they are commutable, so shorter encodings
7487 // are available more often.
7488 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7489 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7490 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7491 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
Richard Barton984d0ba2012-07-09 18:30:56 +00007492 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7493 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
Richard Bartona39625e2012-07-09 16:12:24 +00007494 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7495 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7496 unsigned NewOpc;
7497 switch (Inst.getOpcode()) {
7498 default: llvm_unreachable("unexpected opcode");
7499 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7500 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7501 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7502 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7503 }
7504 MCInst TmpInst;
7505 TmpInst.setOpcode(NewOpc);
7506 TmpInst.addOperand(Inst.getOperand(0));
7507 TmpInst.addOperand(Inst.getOperand(5));
7508 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7509 TmpInst.addOperand(Inst.getOperand(1));
7510 TmpInst.addOperand(Inst.getOperand(2));
7511 } else {
7512 TmpInst.addOperand(Inst.getOperand(2));
7513 TmpInst.addOperand(Inst.getOperand(1));
7514 }
7515 TmpInst.addOperand(Inst.getOperand(3));
7516 TmpInst.addOperand(Inst.getOperand(4));
7517 Inst = TmpInst;
7518 return true;
7519 }
7520 return false;
7521 }
Jim Grosbach8ba76c62011-08-11 17:35:48 +00007522 }
Jim Grosbachafad0532011-11-10 23:42:14 +00007523 return false;
Jim Grosbach8ba76c62011-08-11 17:35:48 +00007524}
7525
Jim Grosbach3e941ae2011-08-16 20:45:50 +00007526unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7527 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7528 // suffix depending on whether they're in an IT block or not.
Jim Grosbachb7fa2c02011-08-16 22:20:01 +00007529 unsigned Opc = Inst.getOpcode();
Benjamin Kramer0d6d0982011-10-22 16:50:00 +00007530 const MCInstrDesc &MCID = getInstDesc(Opc);
Jim Grosbach3e941ae2011-08-16 20:45:50 +00007531 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7532 assert(MCID.hasOptionalDef() &&
7533 "optionally flag setting instruction missing optional def operand");
7534 assert(MCID.NumOperands == Inst.getNumOperands() &&
7535 "operand count mismatch!");
7536 // Find the optional-def operand (cc_out).
7537 unsigned OpNo;
7538 for (OpNo = 0;
7539 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7540 ++OpNo)
7541 ;
7542 // If we're parsing Thumb1, reject it completely.
7543 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7544 return Match_MnemonicFail;
7545 // If we're parsing Thumb2, which form is legal depends on whether we're
7546 // in an IT block.
Jim Grosbached16ec42011-08-29 22:24:09 +00007547 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7548 !inITBlock())
Jim Grosbach3e941ae2011-08-16 20:45:50 +00007549 return Match_RequiresITBlock;
Jim Grosbached16ec42011-08-29 22:24:09 +00007550 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7551 inITBlock())
7552 return Match_RequiresNotITBlock;
Jim Grosbach3e941ae2011-08-16 20:45:50 +00007553 }
Jim Grosbachb7fa2c02011-08-16 22:20:01 +00007554 // Some high-register supporting Thumb1 encodings only allow both registers
7555 // to be from r0-r7 when in Thumb2.
7556 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7557 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7558 isARMLowRegister(Inst.getOperand(2).getReg()))
7559 return Match_RequiresThumb2;
7560 // Others only require ARMv6 or later.
Jim Grosbachf86cd372011-08-19 20:46:54 +00007561 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
Jim Grosbachb7fa2c02011-08-16 22:20:01 +00007562 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7563 isARMLowRegister(Inst.getOperand(1).getReg()))
7564 return Match_RequiresV6;
Jim Grosbach3e941ae2011-08-16 20:45:50 +00007565 return Match_Success;
7566}
7567
Jim Grosbach5117ef72012-04-24 22:40:08 +00007568static const char *getSubtargetFeatureName(unsigned Val);
Chris Lattner9487de62010-10-28 21:28:01 +00007569bool ARMAsmParser::
Chad Rosier49963552012-10-13 00:26:04 +00007570MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
Chris Lattner9487de62010-10-28 21:28:01 +00007571 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
Chad Rosier49963552012-10-13 00:26:04 +00007572 MCStreamer &Out, unsigned &ErrorInfo,
7573 bool MatchingInlineAsm) {
Chris Lattner9487de62010-10-28 21:28:01 +00007574 MCInst Inst;
Jim Grosbach120a96a2011-08-15 23:03:29 +00007575 unsigned MatchResult;
Weiming Zhao8f56f882012-11-16 21:55:34 +00007576
Chad Rosier2f480a82012-10-12 22:53:36 +00007577 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
Chad Rosier49963552012-10-13 00:26:04 +00007578 MatchingInlineAsm);
Kevin Enderby3164a342010-12-09 19:19:43 +00007579 switch (MatchResult) {
Jim Grosbach120a96a2011-08-15 23:03:29 +00007580 default: break;
Chris Lattnerd27b05e2010-10-28 21:41:58 +00007581 case Match_Success:
Jim Grosbachedaa35a2011-07-26 18:25:39 +00007582 // Context sensitive operand constraints aren't handled by the matcher,
7583 // so check them here.
Jim Grosbacha0d34d32011-09-02 23:22:08 +00007584 if (validateInstruction(Inst, Operands)) {
7585 // Still progress the IT block, otherwise one wrong condition causes
7586 // nasty cascading errors.
7587 forwardITPosition();
Jim Grosbachedaa35a2011-07-26 18:25:39 +00007588 return true;
Jim Grosbacha0d34d32011-09-02 23:22:08 +00007589 }
Jim Grosbachedaa35a2011-07-26 18:25:39 +00007590
Jim Grosbach8ba76c62011-08-11 17:35:48 +00007591 // Some instructions need post-processing to, for example, tweak which
Jim Grosbachafad0532011-11-10 23:42:14 +00007592 // encoding is selected. Loop on it while changes happen so the
7593 // individual transformations can chain off each other. E.g.,
7594 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7595 while (processInstruction(Inst, Operands))
7596 ;
Jim Grosbach8ba76c62011-08-11 17:35:48 +00007597
Jim Grosbacha0d34d32011-09-02 23:22:08 +00007598 // Only move forward at the very end so that everything in validate
7599 // and process gets a consistent answer about whether we're in an IT
7600 // block.
7601 forwardITPosition();
7602
Jim Grosbach82f76d12012-01-25 19:52:01 +00007603 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7604 // doesn't actually encode.
7605 if (Inst.getOpcode() == ARM::ITasm)
7606 return false;
7607
Jim Grosbach5e5eabb2012-01-26 23:20:15 +00007608 Inst.setLoc(IDLoc);
Chris Lattner9487de62010-10-28 21:28:01 +00007609 Out.EmitInstruction(Inst);
7610 return false;
Jim Grosbach5117ef72012-04-24 22:40:08 +00007611 case Match_MissingFeature: {
7612 assert(ErrorInfo && "Unknown missing feature!");
7613 // Special case the error message for the very common case where only
7614 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7615 std::string Msg = "instruction requires:";
7616 unsigned Mask = 1;
7617 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7618 if (ErrorInfo & Mask) {
7619 Msg += " ";
7620 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7621 }
7622 Mask <<= 1;
7623 }
7624 return Error(IDLoc, Msg);
7625 }
Chris Lattnerd27b05e2010-10-28 21:41:58 +00007626 case Match_InvalidOperand: {
7627 SMLoc ErrorLoc = IDLoc;
7628 if (ErrorInfo != ~0U) {
7629 if (ErrorInfo >= Operands.size())
7630 return Error(IDLoc, "too few operands for instruction");
Jim Grosbach624bcc72010-10-29 14:46:02 +00007631
Chris Lattnerd27b05e2010-10-28 21:41:58 +00007632 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7633 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7634 }
Jim Grosbach624bcc72010-10-29 14:46:02 +00007635
Chris Lattnerd27b05e2010-10-28 21:41:58 +00007636 return Error(ErrorLoc, "invalid operand for instruction");
Chris Lattner9487de62010-10-28 21:28:01 +00007637 }
Chris Lattnerd27b05e2010-10-28 21:41:58 +00007638 case Match_MnemonicFail:
Benjamin Kramer673824b2012-04-15 17:04:27 +00007639 return Error(IDLoc, "invalid instruction",
7640 ((ARMOperand*)Operands[0])->getLocRange());
Jim Grosbached16ec42011-08-29 22:24:09 +00007641 case Match_RequiresNotITBlock:
7642 return Error(IDLoc, "flag setting instruction only valid outside IT block");
Jim Grosbach3e941ae2011-08-16 20:45:50 +00007643 case Match_RequiresITBlock:
7644 return Error(IDLoc, "instruction only valid inside IT block");
Jim Grosbachb7fa2c02011-08-16 22:20:01 +00007645 case Match_RequiresV6:
7646 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7647 case Match_RequiresThumb2:
7648 return Error(IDLoc, "instruction variant requires Thumb2");
Quentin Colombeta83d5e92013-04-26 17:54:54 +00007649 case Match_ImmRange0_4: {
7650 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7651 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7652 return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7653 }
Jim Grosbach087affe2012-06-22 23:56:48 +00007654 case Match_ImmRange0_15: {
7655 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7656 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7657 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7658 }
Chris Lattnerd27b05e2010-10-28 21:41:58 +00007659 }
Jim Grosbach624bcc72010-10-29 14:46:02 +00007660
Eric Christopher91d7b902010-10-29 09:26:59 +00007661 llvm_unreachable("Implement any new match types added!");
Chris Lattner9487de62010-10-28 21:28:01 +00007662}
7663
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007664/// parseDirective parses the arm specific directives
Kevin Enderbyccab3172009-09-15 00:27:25 +00007665bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7666 StringRef IDVal = DirectiveID.getIdentifier();
7667 if (IDVal == ".word")
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007668 return parseDirectiveWord(4, DirectiveID.getLoc());
Kevin Enderby146dcf22009-10-15 20:48:48 +00007669 else if (IDVal == ".thumb")
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007670 return parseDirectiveThumb(DirectiveID.getLoc());
Jim Grosbach7f882392011-12-07 18:04:19 +00007671 else if (IDVal == ".arm")
7672 return parseDirectiveARM(DirectiveID.getLoc());
Kevin Enderby146dcf22009-10-15 20:48:48 +00007673 else if (IDVal == ".thumb_func")
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007674 return parseDirectiveThumbFunc(DirectiveID.getLoc());
Kevin Enderby146dcf22009-10-15 20:48:48 +00007675 else if (IDVal == ".code")
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007676 return parseDirectiveCode(DirectiveID.getLoc());
Kevin Enderby146dcf22009-10-15 20:48:48 +00007677 else if (IDVal == ".syntax")
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007678 return parseDirectiveSyntax(DirectiveID.getLoc());
Jim Grosbachab5830e2011-12-14 02:16:11 +00007679 else if (IDVal == ".unreq")
7680 return parseDirectiveUnreq(DirectiveID.getLoc());
Jason W Kim135d2442011-12-20 17:38:12 +00007681 else if (IDVal == ".arch")
7682 return parseDirectiveArch(DirectiveID.getLoc());
7683 else if (IDVal == ".eabi_attribute")
7684 return parseDirectiveEabiAttr(DirectiveID.getLoc());
Logan Chien4ea23b52013-05-10 16:17:24 +00007685 else if (IDVal == ".fnstart")
7686 return parseDirectiveFnStart(DirectiveID.getLoc());
7687 else if (IDVal == ".fnend")
7688 return parseDirectiveFnEnd(DirectiveID.getLoc());
7689 else if (IDVal == ".cantunwind")
7690 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7691 else if (IDVal == ".personality")
7692 return parseDirectivePersonality(DirectiveID.getLoc());
7693 else if (IDVal == ".handlerdata")
7694 return parseDirectiveHandlerData(DirectiveID.getLoc());
7695 else if (IDVal == ".setfp")
7696 return parseDirectiveSetFP(DirectiveID.getLoc());
7697 else if (IDVal == ".pad")
7698 return parseDirectivePad(DirectiveID.getLoc());
7699 else if (IDVal == ".save")
7700 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7701 else if (IDVal == ".vsave")
7702 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
Kevin Enderbyccab3172009-09-15 00:27:25 +00007703 return true;
7704}
7705
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007706/// parseDirectiveWord
Kevin Enderbyccab3172009-09-15 00:27:25 +00007707/// ::= .word [ expression (, expression)* ]
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007708bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
Kevin Enderbyccab3172009-09-15 00:27:25 +00007709 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7710 for (;;) {
7711 const MCExpr *Value;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00007712 if (getParser().parseExpression(Value))
Kevin Enderbyccab3172009-09-15 00:27:25 +00007713 return true;
7714
Eric Christopherbf7bc492013-01-09 03:52:05 +00007715 getParser().getStreamer().EmitValue(Value, Size);
Kevin Enderbyccab3172009-09-15 00:27:25 +00007716
7717 if (getLexer().is(AsmToken::EndOfStatement))
7718 break;
Jim Grosbach624bcc72010-10-29 14:46:02 +00007719
Kevin Enderbyccab3172009-09-15 00:27:25 +00007720 // FIXME: Improve diagnostic.
7721 if (getLexer().isNot(AsmToken::Comma))
7722 return Error(L, "unexpected token in directive");
Sean Callanana83fd7d2010-01-19 20:27:46 +00007723 Parser.Lex();
Kevin Enderbyccab3172009-09-15 00:27:25 +00007724 }
7725 }
7726
Sean Callanana83fd7d2010-01-19 20:27:46 +00007727 Parser.Lex();
Kevin Enderbyccab3172009-09-15 00:27:25 +00007728 return false;
7729}
7730
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007731/// parseDirectiveThumb
Kevin Enderby146dcf22009-10-15 20:48:48 +00007732/// ::= .thumb
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007733bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
Kevin Enderby146dcf22009-10-15 20:48:48 +00007734 if (getLexer().isNot(AsmToken::EndOfStatement))
7735 return Error(L, "unexpected token in directive");
Sean Callanana83fd7d2010-01-19 20:27:46 +00007736 Parser.Lex();
Kevin Enderby146dcf22009-10-15 20:48:48 +00007737
Tim Northovera2292d02013-06-10 23:20:58 +00007738 if (!hasThumb())
7739 return Error(L, "target does not support Thumb mode");
7740
Jim Grosbach7f882392011-12-07 18:04:19 +00007741 if (!isThumb())
7742 SwitchMode();
7743 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7744 return false;
7745}
7746
7747/// parseDirectiveARM
7748/// ::= .arm
7749bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7750 if (getLexer().isNot(AsmToken::EndOfStatement))
7751 return Error(L, "unexpected token in directive");
7752 Parser.Lex();
7753
Tim Northovera2292d02013-06-10 23:20:58 +00007754 if (!hasARM())
7755 return Error(L, "target does not support ARM mode");
7756
Jim Grosbach7f882392011-12-07 18:04:19 +00007757 if (isThumb())
7758 SwitchMode();
7759 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
Kevin Enderby146dcf22009-10-15 20:48:48 +00007760 return false;
7761}
7762
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007763/// parseDirectiveThumbFunc
Kevin Enderby146dcf22009-10-15 20:48:48 +00007764/// ::= .thumbfunc symbol_name
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007765bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
Bill Wendlingbc07a892013-06-18 07:20:20 +00007766 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7767 bool isMachO = MAI->hasSubsectionsViaSymbols();
Rafael Espindolae90c1cb2011-05-16 16:17:21 +00007768 StringRef Name;
Jim Grosbach1152cc02011-12-21 22:30:16 +00007769 bool needFuncName = true;
Rafael Espindolae90c1cb2011-05-16 16:17:21 +00007770
Jim Grosbach1152cc02011-12-21 22:30:16 +00007771 // Darwin asm has (optionally) function name after .thumb_func direction
Rafael Espindolae90c1cb2011-05-16 16:17:21 +00007772 // ELF doesn't
7773 if (isMachO) {
7774 const AsmToken &Tok = Parser.getTok();
Jim Grosbach1152cc02011-12-21 22:30:16 +00007775 if (Tok.isNot(AsmToken::EndOfStatement)) {
7776 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7777 return Error(L, "unexpected token in .thumb_func directive");
7778 Name = Tok.getIdentifier();
7779 Parser.Lex(); // Consume the identifier token.
7780 needFuncName = false;
7781 }
Rafael Espindolae90c1cb2011-05-16 16:17:21 +00007782 }
7783
Jim Grosbach1152cc02011-12-21 22:30:16 +00007784 if (getLexer().isNot(AsmToken::EndOfStatement))
Kevin Enderby146dcf22009-10-15 20:48:48 +00007785 return Error(L, "unexpected token in directive");
Jim Grosbach1152cc02011-12-21 22:30:16 +00007786
7787 // Eat the end of statement and any blank lines that follow.
7788 while (getLexer().is(AsmToken::EndOfStatement))
7789 Parser.Lex();
Kevin Enderby146dcf22009-10-15 20:48:48 +00007790
Rafael Espindolae90c1cb2011-05-16 16:17:21 +00007791 // FIXME: assuming function name will be the line following .thumb_func
Jim Grosbach1152cc02011-12-21 22:30:16 +00007792 // We really should be checking the next symbol definition even if there's
7793 // stuff in between.
7794 if (needFuncName) {
Jim Grosbach42ba6282011-11-10 20:48:53 +00007795 Name = Parser.getTok().getIdentifier();
Rafael Espindolae90c1cb2011-05-16 16:17:21 +00007796 }
7797
Jim Grosbachc6db8ce2010-11-05 22:33:53 +00007798 // Mark symbol as a thumb symbol.
7799 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7800 getParser().getStreamer().EmitThumbFunc(Func);
Kevin Enderby146dcf22009-10-15 20:48:48 +00007801 return false;
7802}
7803
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007804/// parseDirectiveSyntax
Kevin Enderby146dcf22009-10-15 20:48:48 +00007805/// ::= .syntax unified | divided
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007806bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
Sean Callanan936b0d32010-01-19 21:44:56 +00007807 const AsmToken &Tok = Parser.getTok();
Kevin Enderby146dcf22009-10-15 20:48:48 +00007808 if (Tok.isNot(AsmToken::Identifier))
7809 return Error(L, "unexpected token in .syntax directive");
Benjamin Kramer92d89982010-07-14 22:38:02 +00007810 StringRef Mode = Tok.getString();
Duncan Sands257eba42010-06-29 13:04:35 +00007811 if (Mode == "unified" || Mode == "UNIFIED")
Sean Callanana83fd7d2010-01-19 20:27:46 +00007812 Parser.Lex();
Duncan Sands257eba42010-06-29 13:04:35 +00007813 else if (Mode == "divided" || Mode == "DIVIDED")
Kevin Enderbye9f2f0c2011-01-27 23:22:36 +00007814 return Error(L, "'.syntax divided' arm asssembly not supported");
Kevin Enderby146dcf22009-10-15 20:48:48 +00007815 else
7816 return Error(L, "unrecognized syntax mode in .syntax directive");
7817
7818 if (getLexer().isNot(AsmToken::EndOfStatement))
Sean Callanan936b0d32010-01-19 21:44:56 +00007819 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
Sean Callanana83fd7d2010-01-19 20:27:46 +00007820 Parser.Lex();
Kevin Enderby146dcf22009-10-15 20:48:48 +00007821
7822 // TODO tell the MC streamer the mode
7823 // getParser().getStreamer().Emit???();
7824 return false;
7825}
7826
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007827/// parseDirectiveCode
Kevin Enderby146dcf22009-10-15 20:48:48 +00007828/// ::= .code 16 | 32
Jim Grosbacheab1c0d2011-07-26 17:10:22 +00007829bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
Sean Callanan936b0d32010-01-19 21:44:56 +00007830 const AsmToken &Tok = Parser.getTok();
Kevin Enderby146dcf22009-10-15 20:48:48 +00007831 if (Tok.isNot(AsmToken::Integer))
7832 return Error(L, "unexpected token in .code directive");
Sean Callanan936b0d32010-01-19 21:44:56 +00007833 int64_t Val = Parser.getTok().getIntVal();
Duncan Sands257eba42010-06-29 13:04:35 +00007834 if (Val == 16)
Sean Callanana83fd7d2010-01-19 20:27:46 +00007835 Parser.Lex();
Duncan Sands257eba42010-06-29 13:04:35 +00007836 else if (Val == 32)
Sean Callanana83fd7d2010-01-19 20:27:46 +00007837 Parser.Lex();
Kevin Enderby146dcf22009-10-15 20:48:48 +00007838 else
7839 return Error(L, "invalid operand to .code directive");
7840
7841 if (getLexer().isNot(AsmToken::EndOfStatement))
Sean Callanan936b0d32010-01-19 21:44:56 +00007842 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
Sean Callanana83fd7d2010-01-19 20:27:46 +00007843 Parser.Lex();
Kevin Enderby146dcf22009-10-15 20:48:48 +00007844
Evan Cheng284b4672011-07-08 22:36:29 +00007845 if (Val == 16) {
Tim Northovera2292d02013-06-10 23:20:58 +00007846 if (!hasThumb())
7847 return Error(L, "target does not support Thumb mode");
7848
Jim Grosbachf471ac32011-09-06 18:46:23 +00007849 if (!isThumb())
Evan Cheng91111d22011-07-09 05:47:46 +00007850 SwitchMode();
Jim Grosbachf471ac32011-09-06 18:46:23 +00007851 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
Evan Cheng284b4672011-07-08 22:36:29 +00007852 } else {
Tim Northovera2292d02013-06-10 23:20:58 +00007853 if (!hasARM())
7854 return Error(L, "target does not support ARM mode");
7855
Jim Grosbachf471ac32011-09-06 18:46:23 +00007856 if (isThumb())
Evan Cheng91111d22011-07-09 05:47:46 +00007857 SwitchMode();
Jim Grosbachf471ac32011-09-06 18:46:23 +00007858 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
Evan Cheng45543ba2011-07-08 22:49:55 +00007859 }
Jim Grosbach2db0ea02010-11-05 22:40:53 +00007860
Kevin Enderby146dcf22009-10-15 20:48:48 +00007861 return false;
7862}
7863
Jim Grosbachab5830e2011-12-14 02:16:11 +00007864/// parseDirectiveReq
7865/// ::= name .req registername
7866bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7867 Parser.Lex(); // Eat the '.req' token.
7868 unsigned Reg;
7869 SMLoc SRegLoc, ERegLoc;
7870 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00007871 Parser.eatToEndOfStatement();
Jim Grosbachab5830e2011-12-14 02:16:11 +00007872 return Error(SRegLoc, "register name expected");
7873 }
7874
7875 // Shouldn't be anything else.
7876 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00007877 Parser.eatToEndOfStatement();
Jim Grosbachab5830e2011-12-14 02:16:11 +00007878 return Error(Parser.getTok().getLoc(),
7879 "unexpected input in .req directive.");
7880 }
7881
7882 Parser.Lex(); // Consume the EndOfStatement
7883
7884 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7885 return Error(SRegLoc, "redefinition of '" + Name +
7886 "' does not match original.");
7887
7888 return false;
7889}
7890
7891/// parseDirectiveUneq
7892/// ::= .unreq registername
7893bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7894 if (Parser.getTok().isNot(AsmToken::Identifier)) {
Jim Grosbachd2037eb2013-02-20 22:21:35 +00007895 Parser.eatToEndOfStatement();
Jim Grosbachab5830e2011-12-14 02:16:11 +00007896 return Error(L, "unexpected input in .unreq directive.");
7897 }
7898 RegisterReqs.erase(Parser.getTok().getIdentifier());
7899 Parser.Lex(); // Eat the identifier.
7900 return false;
7901}
7902
Jason W Kim135d2442011-12-20 17:38:12 +00007903/// parseDirectiveArch
7904/// ::= .arch token
7905bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7906 return true;
7907}
7908
7909/// parseDirectiveEabiAttr
7910/// ::= .eabi_attribute int, int
7911bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7912 return true;
7913}
7914
Logan Chien4ea23b52013-05-10 16:17:24 +00007915/// parseDirectiveFnStart
7916/// ::= .fnstart
7917bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
7918 if (FnStartLoc.isValid()) {
7919 Error(L, ".fnstart starts before the end of previous one");
7920 Error(FnStartLoc, "previous .fnstart starts here");
7921 return true;
7922 }
7923
7924 FnStartLoc = L;
7925 getParser().getStreamer().EmitFnStart();
7926 return false;
7927}
7928
7929/// parseDirectiveFnEnd
7930/// ::= .fnend
7931bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
7932 // Check the ordering of unwind directives
7933 if (!FnStartLoc.isValid())
7934 return Error(L, ".fnstart must precede .fnend directive");
7935
7936 // Reset the unwind directives parser state
7937 resetUnwindDirectiveParserState();
7938
7939 getParser().getStreamer().EmitFnEnd();
7940 return false;
7941}
7942
7943/// parseDirectiveCantUnwind
7944/// ::= .cantunwind
7945bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
7946 // Check the ordering of unwind directives
7947 CantUnwindLoc = L;
7948 if (!FnStartLoc.isValid())
7949 return Error(L, ".fnstart must precede .cantunwind directive");
7950 if (HandlerDataLoc.isValid()) {
7951 Error(L, ".cantunwind can't be used with .handlerdata directive");
7952 Error(HandlerDataLoc, ".handlerdata was specified here");
7953 return true;
7954 }
7955 if (PersonalityLoc.isValid()) {
7956 Error(L, ".cantunwind can't be used with .personality directive");
7957 Error(PersonalityLoc, ".personality was specified here");
7958 return true;
7959 }
7960
7961 getParser().getStreamer().EmitCantUnwind();
7962 return false;
7963}
7964
7965/// parseDirectivePersonality
7966/// ::= .personality name
7967bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
7968 // Check the ordering of unwind directives
7969 PersonalityLoc = L;
7970 if (!FnStartLoc.isValid())
7971 return Error(L, ".fnstart must precede .personality directive");
7972 if (CantUnwindLoc.isValid()) {
7973 Error(L, ".personality can't be used with .cantunwind directive");
7974 Error(CantUnwindLoc, ".cantunwind was specified here");
7975 return true;
7976 }
7977 if (HandlerDataLoc.isValid()) {
7978 Error(L, ".personality must precede .handlerdata directive");
7979 Error(HandlerDataLoc, ".handlerdata was specified here");
7980 return true;
7981 }
7982
7983 // Parse the name of the personality routine
7984 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7985 Parser.eatToEndOfStatement();
7986 return Error(L, "unexpected input in .personality directive.");
7987 }
7988 StringRef Name(Parser.getTok().getIdentifier());
7989 Parser.Lex();
7990
7991 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
7992 getParser().getStreamer().EmitPersonality(PR);
7993 return false;
7994}
7995
7996/// parseDirectiveHandlerData
7997/// ::= .handlerdata
7998bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
7999 // Check the ordering of unwind directives
8000 HandlerDataLoc = L;
8001 if (!FnStartLoc.isValid())
8002 return Error(L, ".fnstart must precede .personality directive");
8003 if (CantUnwindLoc.isValid()) {
8004 Error(L, ".handlerdata can't be used with .cantunwind directive");
8005 Error(CantUnwindLoc, ".cantunwind was specified here");
8006 return true;
8007 }
8008
8009 getParser().getStreamer().EmitHandlerData();
8010 return false;
8011}
8012
8013/// parseDirectiveSetFP
8014/// ::= .setfp fpreg, spreg [, offset]
8015bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8016 // Check the ordering of unwind directives
8017 if (!FnStartLoc.isValid())
8018 return Error(L, ".fnstart must precede .setfp directive");
8019 if (HandlerDataLoc.isValid())
8020 return Error(L, ".setfp must precede .handlerdata directive");
8021
8022 // Parse fpreg
8023 SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8024 int NewFPReg = tryParseRegister();
8025 if (NewFPReg == -1)
8026 return Error(NewFPRegLoc, "frame pointer register expected");
8027
8028 // Consume comma
8029 if (!Parser.getTok().is(AsmToken::Comma))
8030 return Error(Parser.getTok().getLoc(), "comma expected");
8031 Parser.Lex(); // skip comma
8032
8033 // Parse spreg
8034 SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8035 int NewSPReg = tryParseRegister();
8036 if (NewSPReg == -1)
8037 return Error(NewSPRegLoc, "stack pointer register expected");
8038
8039 if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8040 return Error(NewSPRegLoc,
8041 "register should be either $sp or the latest fp register");
8042
8043 // Update the frame pointer register
8044 FPReg = NewFPReg;
8045
8046 // Parse offset
8047 int64_t Offset = 0;
8048 if (Parser.getTok().is(AsmToken::Comma)) {
8049 Parser.Lex(); // skip comma
8050
8051 if (Parser.getTok().isNot(AsmToken::Hash) &&
8052 Parser.getTok().isNot(AsmToken::Dollar)) {
8053 return Error(Parser.getTok().getLoc(), "'#' expected");
8054 }
8055 Parser.Lex(); // skip hash token.
8056
8057 const MCExpr *OffsetExpr;
8058 SMLoc ExLoc = Parser.getTok().getLoc();
8059 SMLoc EndLoc;
8060 if (getParser().parseExpression(OffsetExpr, EndLoc))
8061 return Error(ExLoc, "malformed setfp offset");
8062 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8063 if (!CE)
8064 return Error(ExLoc, "setfp offset must be an immediate");
8065
8066 Offset = CE->getValue();
8067 }
8068
8069 getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8070 static_cast<unsigned>(NewSPReg),
8071 Offset);
8072 return false;
8073}
8074
8075/// parseDirective
8076/// ::= .pad offset
8077bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8078 // Check the ordering of unwind directives
8079 if (!FnStartLoc.isValid())
8080 return Error(L, ".fnstart must precede .pad directive");
8081 if (HandlerDataLoc.isValid())
8082 return Error(L, ".pad must precede .handlerdata directive");
8083
8084 // Parse the offset
8085 if (Parser.getTok().isNot(AsmToken::Hash) &&
8086 Parser.getTok().isNot(AsmToken::Dollar)) {
8087 return Error(Parser.getTok().getLoc(), "'#' expected");
8088 }
8089 Parser.Lex(); // skip hash token.
8090
8091 const MCExpr *OffsetExpr;
8092 SMLoc ExLoc = Parser.getTok().getLoc();
8093 SMLoc EndLoc;
8094 if (getParser().parseExpression(OffsetExpr, EndLoc))
8095 return Error(ExLoc, "malformed pad offset");
8096 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8097 if (!CE)
8098 return Error(ExLoc, "pad offset must be an immediate");
8099
8100 getParser().getStreamer().EmitPad(CE->getValue());
8101 return false;
8102}
8103
8104/// parseDirectiveRegSave
8105/// ::= .save { registers }
8106/// ::= .vsave { registers }
8107bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8108 // Check the ordering of unwind directives
8109 if (!FnStartLoc.isValid())
8110 return Error(L, ".fnstart must precede .save or .vsave directives");
8111 if (HandlerDataLoc.isValid())
8112 return Error(L, ".save or .vsave must precede .handlerdata directive");
8113
Benjamin Kramer23632bd2013-08-03 22:16:24 +00008114 // RAII object to make sure parsed operands are deleted.
8115 struct CleanupObject {
8116 SmallVector<MCParsedAsmOperand *, 1> Operands;
8117 ~CleanupObject() {
8118 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8119 delete Operands[I];
8120 }
8121 } CO;
8122
Logan Chien4ea23b52013-05-10 16:17:24 +00008123 // Parse the register list
Benjamin Kramer23632bd2013-08-03 22:16:24 +00008124 if (parseRegisterList(CO.Operands))
Logan Chien4ea23b52013-05-10 16:17:24 +00008125 return true;
Benjamin Kramer23632bd2013-08-03 22:16:24 +00008126 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
Logan Chien4ea23b52013-05-10 16:17:24 +00008127 if (!IsVector && !Op->isRegList())
8128 return Error(L, ".save expects GPR registers");
8129 if (IsVector && !Op->isDPRRegList())
8130 return Error(L, ".vsave expects DPR registers");
8131
8132 getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8133 return false;
8134}
8135
Kevin Enderby8be42bd2009-10-30 22:55:57 +00008136/// Force static initialization.
Kevin Enderbyccab3172009-09-15 00:27:25 +00008137extern "C" void LLVMInitializeARMAsmParser() {
Evan Cheng11424442011-07-26 00:24:13 +00008138 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8139 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
Kevin Enderbyccab3172009-09-15 00:27:25 +00008140}
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00008141
Chris Lattner3e4582a2010-09-06 19:11:01 +00008142#define GET_REGISTER_MATCHER
Craig Topper3ec7c2a2012-04-25 06:56:34 +00008143#define GET_SUBTARGET_FEATURE_NAME
Chris Lattner3e4582a2010-09-06 19:11:01 +00008144#define GET_MATCHER_IMPLEMENTATION
Daniel Dunbar5cd4d0f2010-08-11 05:24:50 +00008145#include "ARMGenAsmMatcher.inc"
Jim Grosbach231e7aa2013-02-06 06:00:11 +00008146
8147// Define this matcher function after the auto-generated include so we
8148// have the match class enum definitions.
8149unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8150 unsigned Kind) {
8151 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8152 // If the kind is a token for a literal immediate, check if our asm
8153 // operand matches. This is for InstAliases which have a fixed-value
8154 // immediate in the syntax.
8155 if (Kind == MCK__35_0 && Op->isImm()) {
8156 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8157 if (!CE)
8158 return Match_InvalidOperand;
8159 if (CE->getValue() == 0)
8160 return Match_Success;
8161 }
8162 return Match_InvalidOperand;
8163}