Matt Arsenault | d0799df | 2016-01-30 05:10:59 +0000 | [diff] [blame^] | 1 | ; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA %s |
| 2 | |
| 3 | declare i32 @llvm.amdgcn.workgroup.id.x() #0 |
| 4 | declare i32 @llvm.amdgcn.workgroup.id.y() #0 |
| 5 | declare i32 @llvm.amdgcn.workgroup.id.z() #0 |
| 6 | |
| 7 | declare i32 @llvm.amdgcn.workitem.id.x() #0 |
| 8 | declare i32 @llvm.amdgcn.workitem.id.y() #0 |
| 9 | declare i32 @llvm.amdgcn.workitem.id.z() #0 |
| 10 | |
| 11 | declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 |
| 12 | |
| 13 | ; HSA: define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { |
| 14 | define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { |
| 15 | %val = call i32 @llvm.amdgcn.workgroup.id.x() |
| 16 | store i32 %val, i32 addrspace(1)* %ptr |
| 17 | ret void |
| 18 | } |
| 19 | |
| 20 | ; HSA: define void @use_tgid_y(i32 addrspace(1)* %ptr) #2 { |
| 21 | define void @use_tgid_y(i32 addrspace(1)* %ptr) #1 { |
| 22 | %val = call i32 @llvm.amdgcn.workgroup.id.y() |
| 23 | store i32 %val, i32 addrspace(1)* %ptr |
| 24 | ret void |
| 25 | } |
| 26 | |
| 27 | ; HSA: define void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #2 { |
| 28 | define void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #1 { |
| 29 | %val0 = call i32 @llvm.amdgcn.workgroup.id.y() |
| 30 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 31 | %val1 = call i32 @llvm.amdgcn.workgroup.id.y() |
| 32 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 33 | ret void |
| 34 | } |
| 35 | |
| 36 | ; HSA: define void @use_tgid_x_y(i32 addrspace(1)* %ptr) #2 { |
| 37 | define void @use_tgid_x_y(i32 addrspace(1)* %ptr) #1 { |
| 38 | %val0 = call i32 @llvm.amdgcn.workgroup.id.x() |
| 39 | %val1 = call i32 @llvm.amdgcn.workgroup.id.y() |
| 40 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 41 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 42 | ret void |
| 43 | } |
| 44 | |
| 45 | ; HSA: define void @use_tgid_z(i32 addrspace(1)* %ptr) #3 { |
| 46 | define void @use_tgid_z(i32 addrspace(1)* %ptr) #1 { |
| 47 | %val = call i32 @llvm.amdgcn.workgroup.id.z() |
| 48 | store i32 %val, i32 addrspace(1)* %ptr |
| 49 | ret void |
| 50 | } |
| 51 | |
| 52 | ; HSA: define void @use_tgid_x_z(i32 addrspace(1)* %ptr) #3 { |
| 53 | define void @use_tgid_x_z(i32 addrspace(1)* %ptr) #1 { |
| 54 | %val0 = call i32 @llvm.amdgcn.workgroup.id.x() |
| 55 | %val1 = call i32 @llvm.amdgcn.workgroup.id.z() |
| 56 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 57 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 58 | ret void |
| 59 | } |
| 60 | |
| 61 | ; HSA: define void @use_tgid_y_z(i32 addrspace(1)* %ptr) #4 { |
| 62 | define void @use_tgid_y_z(i32 addrspace(1)* %ptr) #1 { |
| 63 | %val0 = call i32 @llvm.amdgcn.workgroup.id.y() |
| 64 | %val1 = call i32 @llvm.amdgcn.workgroup.id.z() |
| 65 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 66 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 67 | ret void |
| 68 | } |
| 69 | |
| 70 | ; HSA: define void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #4 { |
| 71 | define void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #1 { |
| 72 | %val0 = call i32 @llvm.amdgcn.workgroup.id.x() |
| 73 | %val1 = call i32 @llvm.amdgcn.workgroup.id.y() |
| 74 | %val2 = call i32 @llvm.amdgcn.workgroup.id.z() |
| 75 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 76 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 77 | store volatile i32 %val2, i32 addrspace(1)* %ptr |
| 78 | ret void |
| 79 | } |
| 80 | |
| 81 | ; HSA: define void @use_tidig_x(i32 addrspace(1)* %ptr) #1 { |
| 82 | define void @use_tidig_x(i32 addrspace(1)* %ptr) #1 { |
| 83 | %val = call i32 @llvm.amdgcn.workitem.id.x() |
| 84 | store i32 %val, i32 addrspace(1)* %ptr |
| 85 | ret void |
| 86 | } |
| 87 | |
| 88 | ; HSA: define void @use_tidig_y(i32 addrspace(1)* %ptr) #5 { |
| 89 | define void @use_tidig_y(i32 addrspace(1)* %ptr) #1 { |
| 90 | %val = call i32 @llvm.amdgcn.workitem.id.y() |
| 91 | store i32 %val, i32 addrspace(1)* %ptr |
| 92 | ret void |
| 93 | } |
| 94 | |
| 95 | ; HSA: define void @use_tidig_z(i32 addrspace(1)* %ptr) #6 { |
| 96 | define void @use_tidig_z(i32 addrspace(1)* %ptr) #1 { |
| 97 | %val = call i32 @llvm.amdgcn.workitem.id.z() |
| 98 | store i32 %val, i32 addrspace(1)* %ptr |
| 99 | ret void |
| 100 | } |
| 101 | |
| 102 | ; HSA: define void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 { |
| 103 | define void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 { |
| 104 | %val0 = call i32 @llvm.amdgcn.workitem.id.x() |
| 105 | %val1 = call i32 @llvm.amdgcn.workgroup.id.x() |
| 106 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 107 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 108 | ret void |
| 109 | } |
| 110 | |
| 111 | ; HSA: define void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #7 { |
| 112 | define void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #1 { |
| 113 | %val0 = call i32 @llvm.amdgcn.workitem.id.y() |
| 114 | %val1 = call i32 @llvm.amdgcn.workgroup.id.y() |
| 115 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 116 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 117 | ret void |
| 118 | } |
| 119 | |
| 120 | ; HSA: define void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #8 { |
| 121 | define void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #1 { |
| 122 | %val0 = call i32 @llvm.amdgcn.workitem.id.x() |
| 123 | %val1 = call i32 @llvm.amdgcn.workitem.id.y() |
| 124 | %val2 = call i32 @llvm.amdgcn.workitem.id.z() |
| 125 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 126 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 127 | store volatile i32 %val2, i32 addrspace(1)* %ptr |
| 128 | ret void |
| 129 | } |
| 130 | |
| 131 | ; HSA: define void @use_all_workitems(i32 addrspace(1)* %ptr) #9 { |
| 132 | define void @use_all_workitems(i32 addrspace(1)* %ptr) #1 { |
| 133 | %val0 = call i32 @llvm.amdgcn.workitem.id.x() |
| 134 | %val1 = call i32 @llvm.amdgcn.workitem.id.y() |
| 135 | %val2 = call i32 @llvm.amdgcn.workitem.id.z() |
| 136 | %val3 = call i32 @llvm.amdgcn.workgroup.id.x() |
| 137 | %val4 = call i32 @llvm.amdgcn.workgroup.id.y() |
| 138 | %val5 = call i32 @llvm.amdgcn.workgroup.id.z() |
| 139 | store volatile i32 %val0, i32 addrspace(1)* %ptr |
| 140 | store volatile i32 %val1, i32 addrspace(1)* %ptr |
| 141 | store volatile i32 %val2, i32 addrspace(1)* %ptr |
| 142 | store volatile i32 %val3, i32 addrspace(1)* %ptr |
| 143 | store volatile i32 %val4, i32 addrspace(1)* %ptr |
| 144 | store volatile i32 %val5, i32 addrspace(1)* %ptr |
| 145 | ret void |
| 146 | } |
| 147 | |
| 148 | ; HSA: define void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #10 { |
| 149 | define void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 { |
| 150 | %dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() |
| 151 | %bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* |
| 152 | %val = load i32, i32 addrspace(2)* %bc |
| 153 | store i32 %val, i32 addrspace(1)* %ptr |
| 154 | ret void |
| 155 | } |
| 156 | |
| 157 | attributes #0 = { nounwind readnone } |
| 158 | attributes #1 = { nounwind } |
| 159 | |
| 160 | ; HSA: attributes #0 = { nounwind readnone } |
| 161 | ; HSA: attributes #1 = { nounwind } |
| 162 | ; HSA: attributes #2 = { nounwind "amdgpu-work-group-id-y" } |
| 163 | ; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-z" } |
| 164 | ; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" } |
| 165 | ; HSA: attributes #5 = { nounwind "amdgpu-work-item-id-y" } |
| 166 | ; HSA: attributes #6 = { nounwind "amdgpu-work-item-id-z" } |
| 167 | ; HSA: attributes #7 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-item-id-y" } |
| 168 | ; HSA: attributes #8 = { nounwind "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" } |
| 169 | ; HSA: attributes #9 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" } |
| 170 | ; HSA: attributes #10 = { nounwind "amdgpu-dispatch-ptr" } |