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Jason W Kimb3212452010-09-30 02:17:26 +00001//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Jim Grosbach45e50d82011-08-16 17:06:20 +000010#include "MCTargetDesc/ARMMCTargetDesc.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000011#include "MCTargetDesc/ARMAddressingModes.h"
Joe Abbey8e72eb72014-09-16 09:18:23 +000012#include "MCTargetDesc/ARMAsmBackend.h"
13#include "MCTargetDesc/ARMAsmBackendDarwin.h"
14#include "MCTargetDesc/ARMAsmBackendELF.h"
15#include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
Evan Chengad5f4852011-07-23 00:00:19 +000016#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMFixupKinds.h"
Quentin Colombet77ca8b82013-01-14 21:34:09 +000018#include "llvm/ADT/StringSwitch.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000019#include "llvm/MC/MCAsmBackend.h"
Jason W Kimb3212452010-09-30 02:17:26 +000020#include "llvm/MC/MCAssembler.h"
Jim Grosbache78031a2012-04-30 22:30:43 +000021#include "llvm/MC/MCContext.h"
Jim Grosbach87055ed2010-12-08 01:16:55 +000022#include "llvm/MC/MCDirectives.h"
Rafael Espindolaf0e24d42010-12-17 16:59:53 +000023#include "llvm/MC/MCELFObjectWriter.h"
Jason W Kimb3212452010-09-30 02:17:26 +000024#include "llvm/MC/MCExpr.h"
Craig Topper6e80c282012-03-26 06:58:25 +000025#include "llvm/MC/MCFixupKindInfo.h"
Daniel Dunbar73b87132010-12-16 16:08:33 +000026#include "llvm/MC/MCMachObjectWriter.h"
Jason W Kimb3212452010-09-30 02:17:26 +000027#include "llvm/MC/MCObjectWriter.h"
Jason W Kimb3212452010-09-30 02:17:26 +000028#include "llvm/MC/MCSectionELF.h"
29#include "llvm/MC/MCSectionMachO.h"
Jim Grosbach45e50d82011-08-16 17:06:20 +000030#include "llvm/MC/MCSubtargetInfo.h"
Jim Grosbach3b50c9e2012-01-18 00:23:57 +000031#include "llvm/MC/MCValue.h"
Wesley Peck18510902010-10-22 15:52:49 +000032#include "llvm/Support/ELF.h"
Jason W Kimb3212452010-09-30 02:17:26 +000033#include "llvm/Support/ErrorHandling.h"
Charles Davis8bdfafd2013-09-01 04:28:48 +000034#include "llvm/Support/MachO.h"
Vedant Kumar366dd9fd2015-08-21 21:52:48 +000035#include "llvm/Support/TargetParser.h"
Jason W Kimb3212452010-09-30 02:17:26 +000036#include "llvm/Support/raw_ostream.h"
Jason W Kimb3212452010-09-30 02:17:26 +000037using namespace llvm;
38
39namespace {
Rafael Espindola6b5e56c2010-12-17 17:45:22 +000040class ARMELFObjectWriter : public MCELFObjectTargetWriter {
41public:
Rafael Espindola1ad40952011-12-21 17:00:36 +000042 ARMELFObjectWriter(uint8_t OSABI)
Joe Abbey8e72eb72014-09-16 09:18:23 +000043 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
44 /*HasRelocationAddend*/ false) {}
Rafael Espindola6b5e56c2010-12-17 17:45:22 +000045};
46
Joe Abbey8e72eb72014-09-16 09:18:23 +000047const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
48 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
49 // This table *must* be in the order that the fixup_* kinds are defined in
50 // ARMFixupKinds.h.
51 //
52 // Name Offset (bits) Size (bits) Flags
53 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
54 {"fixup_t2_ldst_pcrel_12", 0, 32,
55 MCFixupKindInfo::FKF_IsPCRel |
56 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
57 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
58 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
59 {"fixup_t2_pcrel_10", 0, 32,
60 MCFixupKindInfo::FKF_IsPCRel |
61 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
62 {"fixup_thumb_adr_pcrel_10", 0, 8,
63 MCFixupKindInfo::FKF_IsPCRel |
64 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
65 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
66 {"fixup_t2_adr_pcrel_12", 0, 32,
67 MCFixupKindInfo::FKF_IsPCRel |
68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
69 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
73 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
74 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
75 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
76 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
77 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
78 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
79 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
80 {"fixup_arm_thumb_cp", 0, 8,
81 MCFixupKindInfo::FKF_IsPCRel |
82 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
83 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
85 // - 19.
86 {"fixup_arm_movt_hi16", 0, 20, 0},
87 {"fixup_arm_movw_lo16", 0, 20, 0},
88 {"fixup_t2_movt_hi16", 0, 20, 0},
89 {"fixup_t2_movw_lo16", 0, 20, 0},
90 };
91 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
92 // This table *must* be in the order that the fixup_* kinds are defined in
93 // ARMFixupKinds.h.
94 //
95 // Name Offset (bits) Size (bits) Flags
96 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
97 {"fixup_t2_ldst_pcrel_12", 0, 32,
98 MCFixupKindInfo::FKF_IsPCRel |
99 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
100 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
102 {"fixup_t2_pcrel_10", 0, 32,
103 MCFixupKindInfo::FKF_IsPCRel |
104 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
105 {"fixup_thumb_adr_pcrel_10", 8, 8,
106 MCFixupKindInfo::FKF_IsPCRel |
107 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
108 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
109 {"fixup_t2_adr_pcrel_12", 0, 32,
110 MCFixupKindInfo::FKF_IsPCRel |
111 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
112 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
113 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
114 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
115 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
116 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
117 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
118 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
119 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
120 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
121 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
122 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
123 {"fixup_arm_thumb_cp", 8, 8,
124 MCFixupKindInfo::FKF_IsPCRel |
125 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
126 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
127 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
128 // - 19.
129 {"fixup_arm_movt_hi16", 12, 20, 0},
130 {"fixup_arm_movw_lo16", 12, 20, 0},
131 {"fixup_t2_movt_hi16", 12, 20, 0},
132 {"fixup_t2_movw_lo16", 12, 20, 0},
133 };
Jim Grosbach45e50d82011-08-16 17:06:20 +0000134
Joe Abbey8e72eb72014-09-16 09:18:23 +0000135 if (Kind < FirstTargetFixupKind)
136 return MCAsmBackend::getFixupKindInfo(Kind);
137
138 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
139 "Invalid kind!");
140 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
141}
142
143void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
144 switch (Flag) {
145 default:
146 break;
147 case MCAF_Code16:
148 setIsThumb(true);
149 break;
150 case MCAF_Code32:
151 setIsThumb(false);
152 break;
Jim Grosbach45e50d82011-08-16 17:06:20 +0000153 }
Joe Abbey8e72eb72014-09-16 09:18:23 +0000154}
Chris Lattner9fdd10d2010-11-17 05:41:32 +0000155} // end anonymous namespace
Jason W Kimb3212452010-09-30 02:17:26 +0000156
Tim Northover42335572015-04-06 18:44:42 +0000157unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000158 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2];
Tim Northover42335572015-04-06 18:44:42 +0000159
Jim Grosbach34a7c6d2011-12-05 23:45:46 +0000160 switch (Op) {
Joe Abbey8e72eb72014-09-16 09:18:23 +0000161 default:
162 return Op;
163 case ARM::tBcc:
Aaron Ballmanac336242015-04-07 13:28:37 +0000164 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000165 case ARM::tLDRpci:
Aaron Ballmanac336242015-04-07 13:28:37 +0000166 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000167 case ARM::tADR:
Aaron Ballmanac336242015-04-07 13:28:37 +0000168 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000169 case ARM::tB:
Aaron Ballmanac336242015-04-07 13:28:37 +0000170 return HasThumb2 ? (unsigned)ARM::t2B : Op;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000171 case ARM::tCBZ:
172 return ARM::tHINT;
173 case ARM::tCBNZ:
174 return ARM::tHINT;
Jim Grosbach34a7c6d2011-12-05 23:45:46 +0000175 }
176}
177
Jim Grosbachaba3de92012-01-18 18:52:16 +0000178bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
Jim Grosbach34a7c6d2011-12-05 23:45:46 +0000179 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
180 return true;
Jason W Kimb3212452010-09-30 02:17:26 +0000181 return false;
182}
183
Joe Abbey8e72eb72014-09-16 09:18:23 +0000184bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
Eli Bendersky4d9ada02013-01-08 00:22:56 +0000185 const MCRelaxableFragment *DF,
Jim Grosbach25b63fa2011-12-06 00:47:03 +0000186 const MCAsmLayout &Layout) const {
Benjamin Kramer116e99a2012-01-19 21:11:13 +0000187 switch ((unsigned)Fixup.getKind()) {
Jim Grosbachc4aa60f2012-03-19 21:32:32 +0000188 case ARM::fixup_arm_thumb_br: {
189 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
190 // low bit being an implied zero. There's an implied +4 offset for the
191 // branch, so we adjust the other way here to determine what's
192 // encodable.
193 //
194 // Relax if the value is too big for a (signed) i8.
195 int64_t Offset = int64_t(Value) - 4;
196 return Offset > 2046 || Offset < -2048;
197 }
Jim Grosbachcb80eb22012-01-18 21:54:16 +0000198 case ARM::fixup_arm_thumb_bcc: {
199 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
200 // low bit being an implied zero. There's an implied +4 offset for the
201 // branch, so we adjust the other way here to determine what's
202 // encodable.
203 //
204 // Relax if the value is too big for a (signed) i8.
205 int64_t Offset = int64_t(Value) - 4;
206 return Offset > 254 || Offset < -256;
207 }
Jim Grosbach44e5c392012-01-19 02:09:38 +0000208 case ARM::fixup_thumb_adr_pcrel_10:
Jim Grosbachcb80eb22012-01-18 21:54:16 +0000209 case ARM::fixup_arm_thumb_cp: {
Jim Grosbachb008df42012-01-19 01:50:30 +0000210 // If the immediate is negative, greater than 1020, or not a multiple
211 // of four, the wide version of the instruction must be used.
Jim Grosbachcb80eb22012-01-18 21:54:16 +0000212 int64_t Offset = int64_t(Value) - 4;
Jim Grosbachb008df42012-01-19 01:50:30 +0000213 return Offset > 1020 || Offset < 0 || Offset & 3;
Jim Grosbachcb80eb22012-01-18 21:54:16 +0000214 }
Kevin Enderby9bd296a2014-01-10 00:43:32 +0000215 case ARM::fixup_arm_thumb_cb:
216 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
217 // instruction it is is actually out of range for the instruction.
218 // It will be changed to a NOP.
219 int64_t Offset = (Value & ~1);
220 return Offset == 2;
Jim Grosbachcb80eb22012-01-18 21:54:16 +0000221 }
Benjamin Kramer116e99a2012-01-19 21:11:13 +0000222 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
Jim Grosbach25b63fa2011-12-06 00:47:03 +0000223}
224
Jim Grosbachaba3de92012-01-18 18:52:16 +0000225void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
Jim Grosbach34a7c6d2011-12-05 23:45:46 +0000226 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
227
228 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
229 if (RelaxedOp == Inst.getOpcode()) {
230 SmallString<256> Tmp;
231 raw_svector_ostream OS(Tmp);
232 Inst.dump_pretty(OS);
233 OS << "\n";
234 report_fatal_error("unexpected instruction to relax: " + OS.str());
235 }
236
Kevin Enderby9bd296a2014-01-10 00:43:32 +0000237 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
238 // have to change the operands too.
239 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
240 RelaxedOp == ARM::tHINT) {
241 Res.setOpcode(RelaxedOp);
Jim Grosbache9119e42015-05-13 18:37:00 +0000242 Res.addOperand(MCOperand::createImm(0));
243 Res.addOperand(MCOperand::createImm(14));
244 Res.addOperand(MCOperand::createReg(0));
Kevin Enderby9bd296a2014-01-10 00:43:32 +0000245 return;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000246 }
Kevin Enderby9bd296a2014-01-10 00:43:32 +0000247
248 // The rest of instructions we're relaxing have the same operands.
Jim Grosbach34a7c6d2011-12-05 23:45:46 +0000249 // We just need to update to the proper opcode.
250 Res = Inst;
251 Res.setOpcode(RelaxedOp);
Jason W Kimb3212452010-09-30 02:17:26 +0000252}
253
Jim Grosbachaba3de92012-01-18 18:52:16 +0000254bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
Jim Grosbach45e50d82011-08-16 17:06:20 +0000255 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
256 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
Joe Abbey8e72eb72014-09-16 09:18:23 +0000257 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
Jim Grosbach7ccdb7c2011-11-16 22:40:25 +0000258 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
Jim Grosbach87055ed2010-12-08 01:16:55 +0000259 if (isThumb()) {
Joe Abbey8e72eb72014-09-16 09:18:23 +0000260 const uint16_t nopEncoding =
261 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
Jim Grosbach97f1de72010-12-17 19:03:02 +0000262 uint64_t NumNops = Count / 2;
263 for (uint64_t i = 0; i != NumNops; ++i)
Jim Grosbach36e60e92015-06-04 22:24:41 +0000264 OW->write16(nopEncoding);
Jim Grosbach97f1de72010-12-17 19:03:02 +0000265 if (Count & 1)
Jim Grosbach36e60e92015-06-04 22:24:41 +0000266 OW->write8(0);
Jim Grosbach87055ed2010-12-08 01:16:55 +0000267 return true;
268 }
269 // ARM mode
Joe Abbey8e72eb72014-09-16 09:18:23 +0000270 const uint32_t nopEncoding =
271 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
Jim Grosbach97f1de72010-12-17 19:03:02 +0000272 uint64_t NumNops = Count / 4;
273 for (uint64_t i = 0; i != NumNops; ++i)
Jim Grosbach36e60e92015-06-04 22:24:41 +0000274 OW->write32(nopEncoding);
Jim Grosbach45e50d82011-08-16 17:06:20 +0000275 // FIXME: should this function return false when unable to write exactly
276 // 'Count' bytes with NOP encodings?
Jim Grosbach97f1de72010-12-17 19:03:02 +0000277 switch (Count % 4) {
Joe Abbey8e72eb72014-09-16 09:18:23 +0000278 default:
279 break; // No leftover bytes to write
280 case 1:
Jim Grosbach36e60e92015-06-04 22:24:41 +0000281 OW->write8(0);
Joe Abbey8e72eb72014-09-16 09:18:23 +0000282 break;
283 case 2:
Jim Grosbach36e60e92015-06-04 22:24:41 +0000284 OW->write16(0);
Joe Abbey8e72eb72014-09-16 09:18:23 +0000285 break;
286 case 3:
Jim Grosbach36e60e92015-06-04 22:24:41 +0000287 OW->write16(0);
288 OW->write8(0xa0);
Joe Abbey8e72eb72014-09-16 09:18:23 +0000289 break;
Jim Grosbach97f1de72010-12-17 19:03:02 +0000290 }
291
Rafael Espindola0ed15432010-10-25 17:50:35 +0000292 return true;
Jim Grosbach58bce992010-09-30 03:20:34 +0000293}
Jason W Kimb3212452010-09-30 02:17:26 +0000294
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000295static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
296 if (IsLittleEndian) {
297 // Note that the halfwords are stored high first and low second in thumb;
298 // so we need to swap the fixup value here to map properly.
299 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
300 Swapped |= (Value & 0x0000FFFF) << 16;
301 return Swapped;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000302 } else
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000303 return Value;
304}
305
306static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
307 bool IsLittleEndian) {
308 uint32_t Value;
309
310 if (IsLittleEndian) {
311 Value = (SecondHalf & 0xFFFF) << 16;
312 Value |= (FirstHalf & 0xFFFF);
313 } else {
314 Value = (SecondHalf & 0xFFFF);
315 Value |= (FirstHalf & 0xFFFF) << 16;
316 }
317
318 return Value;
319}
320
Jim Grosbache78031a2012-04-30 22:30:43 +0000321static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000322 bool IsPCRel, MCContext *Ctx,
323 bool IsLittleEndian) {
Jim Grosbache78031a2012-04-30 22:30:43 +0000324 unsigned Kind = Fixup.getKind();
Jason W Kimfc5c5222010-12-01 22:46:50 +0000325 switch (Kind) {
326 default:
327 llvm_unreachable("Unknown fixup kind!");
Jim Grosbach4416dfa2010-12-17 18:39:10 +0000328 case FK_Data_1:
329 case FK_Data_2:
Jason W Kimfc5c5222010-12-01 22:46:50 +0000330 case FK_Data_4:
Jason W Kimfc5c5222010-12-01 22:46:50 +0000331 return Value;
Saleem Abdulrasoolfc6b85b2014-05-08 01:35:57 +0000332 case FK_SecRel_2:
333 return Value;
Saleem Abdulrasool729c7a02014-05-04 23:13:15 +0000334 case FK_SecRel_4:
335 return Value;
Jason W Kimd5e6e542010-12-03 19:40:23 +0000336 case ARM::fixup_arm_movt_hi16:
Rafael Espindola5904e122014-03-29 06:26:49 +0000337 if (!IsPCRel)
338 Value >>= 16;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000339 // Fallthrough
Rafael Espindola5904e122014-03-29 06:26:49 +0000340 case ARM::fixup_arm_movw_lo16: {
Jason W Kimd5e6e542010-12-03 19:40:23 +0000341 unsigned Hi4 = (Value & 0xF000) >> 12;
342 unsigned Lo12 = Value & 0x0FFF;
343 // inst{19-16} = Hi4;
344 // inst{11-0} = Lo12;
345 Value = (Hi4 << 16) | (Lo12);
346 return Value;
347 }
Evan Chengd4a5c052011-01-14 02:38:49 +0000348 case ARM::fixup_t2_movt_hi16:
Rafael Espindola5904e122014-03-29 06:26:49 +0000349 if (!IsPCRel)
350 Value >>= 16;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000351 // Fallthrough
Rafael Espindola5904e122014-03-29 06:26:49 +0000352 case ARM::fixup_t2_movw_lo16: {
Evan Chengd4a5c052011-01-14 02:38:49 +0000353 unsigned Hi4 = (Value & 0xF000) >> 12;
354 unsigned i = (Value & 0x800) >> 11;
355 unsigned Mid3 = (Value & 0x700) >> 8;
356 unsigned Lo8 = Value & 0x0FF;
357 // inst{19-16} = Hi4;
358 // inst{26} = i;
359 // inst{14-12} = Mid3;
360 // inst{7-0} = Lo8;
Jim Grosbachd76f43e2011-09-30 22:02:45 +0000361 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000362 return swapHalfWords(Value, IsLittleEndian);
Evan Chengd4a5c052011-01-14 02:38:49 +0000363 }
Owen Anderson3e6ee1d2010-12-09 01:51:07 +0000364 case ARM::fixup_arm_ldst_pcrel_12:
Jason W Kimfc5c5222010-12-01 22:46:50 +0000365 // ARM PC-relative values are offset by 8.
Owen Anderson3ef19d92010-12-09 20:27:52 +0000366 Value -= 4;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000367 // FALLTHROUGH
Owen Anderson3e6ee1d2010-12-09 01:51:07 +0000368 case ARM::fixup_t2_ldst_pcrel_12: {
369 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
Owen Anderson3ef19d92010-12-09 20:27:52 +0000370 Value -= 4;
Owen Anderson3e6ee1d2010-12-09 01:51:07 +0000371 bool isAdd = true;
Jason W Kimfc5c5222010-12-01 22:46:50 +0000372 if ((int64_t)Value < 0) {
373 Value = -Value;
374 isAdd = false;
375 }
Jim Grosbache78031a2012-04-30 22:30:43 +0000376 if (Ctx && Value >= 4096)
Jim Grosbach6f482002015-05-18 18:43:14 +0000377 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
Jason W Kimfc5c5222010-12-01 22:46:50 +0000378 Value |= isAdd << 23;
Jim Grosbach3aeb8672010-12-13 19:18:13 +0000379
Owen Anderson3e6ee1d2010-12-09 01:51:07 +0000380 // Same addressing mode as fixup_arm_pcrel_10,
381 // but with 16-bit halfwords swapped.
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000382 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
383 return swapHalfWords(Value, IsLittleEndian);
Jim Grosbach3aeb8672010-12-13 19:18:13 +0000384
Jason W Kimfc5c5222010-12-01 22:46:50 +0000385 return Value;
386 }
Jim Grosbach509dc2a2010-12-14 22:28:03 +0000387 case ARM::fixup_thumb_adr_pcrel_10:
388 return ((Value - 4) >> 2) & 0xff;
Jim Grosbachce2bd8d2010-12-02 00:28:45 +0000389 case ARM::fixup_arm_adr_pcrel_12: {
390 // ARM PC-relative values are offset by 8.
391 Value -= 8;
392 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
393 if ((int64_t)Value < 0) {
394 Value = -Value;
395 opc = 2; // 0b0010
396 }
Jim Grosbache78031a2012-04-30 22:30:43 +0000397 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
Jim Grosbach6f482002015-05-18 18:43:14 +0000398 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
Jim Grosbachce2bd8d2010-12-02 00:28:45 +0000399 // Encode the immediate and shift the opcode into place.
400 return ARM_AM::getSOImmVal(Value) | (opc << 21);
401 }
Jim Grosbache34793e2010-12-14 16:25:15 +0000402
Owen Anderson6d375e52010-12-14 00:36:49 +0000403 case ARM::fixup_t2_adr_pcrel_12: {
404 Value -= 4;
405 unsigned opc = 0;
406 if ((int64_t)Value < 0) {
407 Value = -Value;
408 opc = 5;
409 }
410
411 uint32_t out = (opc << 21);
Owen Anderson8543d4f2011-03-23 22:03:44 +0000412 out |= (Value & 0x800) << 15;
Owen Anderson6d375e52010-12-14 00:36:49 +0000413 out |= (Value & 0x700) << 4;
414 out |= (Value & 0x0FF);
Jim Grosbache34793e2010-12-14 16:25:15 +0000415
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000416 return swapHalfWords(out, IsLittleEndian);
Owen Anderson6d375e52010-12-14 00:36:49 +0000417 }
Jim Grosbache34793e2010-12-14 16:25:15 +0000418
Jason W Kimd2e2f562011-02-04 19:47:15 +0000419 case ARM::fixup_arm_condbranch:
420 case ARM::fixup_arm_uncondbranch:
James Molloyfb5cd602012-03-30 09:15:32 +0000421 case ARM::fixup_arm_uncondbl:
422 case ARM::fixup_arm_condbl:
Jim Grosbach7b811d32012-02-27 21:36:23 +0000423 case ARM::fixup_arm_blx:
Jason W Kimfc5c5222010-12-01 22:46:50 +0000424 // These values don't encode the low two bits since they're always zero.
425 // Offset by 8 just as above.
Joe Abbey8e72eb72014-09-16 09:18:23 +0000426 if (const MCSymbolRefExpr *SRE =
427 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
Saleem Abdulrasool6e00ca82014-01-30 04:02:31 +0000428 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
429 return 0;
Jim Grosbach9e199462010-12-06 23:57:07 +0000430 return 0xffffff & ((Value - 8) >> 2);
Owen Anderson578074b2010-12-13 19:31:11 +0000431 case ARM::fixup_t2_uncondbranch: {
Owen Anderson235c2762010-12-10 23:02:28 +0000432 Value = Value - 4;
Owen Anderson302d5fd2010-12-09 00:27:41 +0000433 Value >>= 1; // Low bit is not encoded.
Jim Grosbach3aeb8672010-12-13 19:18:13 +0000434
Jim Grosbachf588c512010-12-13 19:25:46 +0000435 uint32_t out = 0;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000436 bool I = Value & 0x800000;
Owen Anderson578074b2010-12-13 19:31:11 +0000437 bool J1 = Value & 0x400000;
438 bool J2 = Value & 0x200000;
439 J1 ^= I;
440 J2 ^= I;
Jim Grosbache34793e2010-12-14 16:25:15 +0000441
Joe Abbey8e72eb72014-09-16 09:18:23 +0000442 out |= I << 26; // S bit
443 out |= !J1 << 13; // J1 bit
444 out |= !J2 << 11; // J2 bit
445 out |= (Value & 0x1FF800) << 5; // imm6 field
446 out |= (Value & 0x0007FF); // imm11 field
Jim Grosbache34793e2010-12-14 16:25:15 +0000447
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000448 return swapHalfWords(out, IsLittleEndian);
Owen Anderson578074b2010-12-13 19:31:11 +0000449 }
450 case ARM::fixup_t2_condbranch: {
451 Value = Value - 4;
452 Value >>= 1; // Low bit is not encoded.
Jim Grosbache34793e2010-12-14 16:25:15 +0000453
Owen Anderson578074b2010-12-13 19:31:11 +0000454 uint64_t out = 0;
Owen Anderson14e41272010-12-09 01:02:09 +0000455 out |= (Value & 0x80000) << 7; // S bit
456 out |= (Value & 0x40000) >> 7; // J2 bit
457 out |= (Value & 0x20000) >> 4; // J1 bit
458 out |= (Value & 0x1F800) << 5; // imm6 field
459 out |= (Value & 0x007FF); // imm11 field
Jim Grosbach3aeb8672010-12-13 19:18:13 +0000460
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000461 return swapHalfWords(out, IsLittleEndian);
Owen Anderson302d5fd2010-12-09 00:27:41 +0000462 }
Jim Grosbach9e199462010-12-06 23:57:07 +0000463 case ARM::fixup_arm_thumb_bl: {
Saleem Abdulrasool077fd252014-01-26 22:29:36 +0000464 // The value doesn't encode the low bit (always zero) and is offset by
465 // four. The 32-bit immediate value is encoded as
466 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
467 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
468 // The value is encoded into disjoint bit positions in the destination
469 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
470 // J = either J1 or J2 bit
471 //
472 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
473 //
474 // Note that the halfwords are stored high first, low second; so we need
475 // to transpose the fixup value here to map properly.
476 uint32_t offset = (Value - 4) >> 1;
477 uint32_t signBit = (offset & 0x800000) >> 23;
478 uint32_t I1Bit = (offset & 0x400000) >> 22;
479 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
480 uint32_t I2Bit = (offset & 0x200000) >> 21;
481 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
482 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
483 uint32_t imm11Bits = (offset & 0x000007FF);
NAKAMURA Takumi8018a292013-06-11 06:52:36 +0000484
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000485 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
486 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
Joe Abbey8e72eb72014-09-16 09:18:23 +0000487 (uint16_t)imm11Bits);
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000488 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
Bill Wendling3392bfc2010-12-09 00:39:08 +0000489 }
490 case ARM::fixup_arm_thumb_blx: {
Saleem Abdulrasool077fd252014-01-26 22:29:36 +0000491 // The value doesn't encode the low two bits (always zero) and is offset by
492 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
493 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
494 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
495 // The value is encoded into disjoint bit positions in the destination
496 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
497 // J = either J1 or J2 bit, 0 = zero.
498 //
499 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
500 //
501 // Note that the halfwords are stored high first, low second; so we need
502 // to transpose the fixup value here to map properly.
503 uint32_t offset = (Value - 2) >> 2;
Joe Abbey8e72eb72014-09-16 09:18:23 +0000504 if (const MCSymbolRefExpr *SRE =
505 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
Saleem Abdulrasool6e00ca82014-01-30 04:02:31 +0000506 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
507 offset = 0;
Saleem Abdulrasool077fd252014-01-26 22:29:36 +0000508 uint32_t signBit = (offset & 0x400000) >> 22;
509 uint32_t I1Bit = (offset & 0x200000) >> 21;
510 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
511 uint32_t I2Bit = (offset & 0x100000) >> 20;
512 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
513 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
514 uint32_t imm10LBits = (offset & 0x3FF);
NAKAMURA Takumi8018a292013-06-11 06:52:36 +0000515
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000516 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
517 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
Joe Abbey8e72eb72014-09-16 09:18:23 +0000518 ((uint16_t)imm10LBits) << 1);
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000519 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
Jim Grosbach9e199462010-12-06 23:57:07 +0000520 }
Bill Wendling8a6449c2010-12-08 01:57:09 +0000521 case ARM::fixup_arm_thumb_cp:
Jim Grosbach3c685612010-12-08 20:32:07 +0000522 // Offset by 4, and don't encode the low two bits. Two bytes of that
523 // 'off by 4' is implicitly handled by the half-word ordering of the
524 // Thumb encoding, so we only need to adjust by 2 here.
525 return ((Value - 2) >> 2) & 0xff;
Jim Grosbach68b27eb2010-12-09 19:50:12 +0000526 case ARM::fixup_arm_thumb_cb: {
Bill Wendlinga7d6aa92010-12-08 23:01:43 +0000527 // Offset by 4 and don't encode the lower bit, which is always 0.
528 uint32_t Binary = (Value - 4) >> 1;
Owen Andersonf636a642010-12-14 19:42:53 +0000529 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
Bill Wendlinga7d6aa92010-12-08 23:01:43 +0000530 }
Jim Grosbache119da12010-12-10 18:21:33 +0000531 case ARM::fixup_arm_thumb_br:
532 // Offset by 4 and don't encode the lower bit, which is always 0.
533 return ((Value - 4) >> 1) & 0x7ff;
Jim Grosbach78485ad2010-12-10 17:13:40 +0000534 case ARM::fixup_arm_thumb_bcc:
535 // Offset by 4 and don't encode the lower bit, which is always 0.
536 return ((Value - 4) >> 1) & 0xff;
Jim Grosbach8648c102011-12-19 23:06:24 +0000537 case ARM::fixup_arm_pcrel_10_unscaled: {
538 Value = Value - 8; // ARM fixups offset by an additional word and don't
539 // need to adjust for the half-word ordering.
540 bool isAdd = true;
541 if ((int64_t)Value < 0) {
542 Value = -Value;
543 isAdd = false;
544 }
Jim Grosbach913cc302012-03-30 21:54:22 +0000545 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
Jim Grosbache78031a2012-04-30 22:30:43 +0000546 if (Ctx && Value >= 256)
Jim Grosbach6f482002015-05-18 18:43:14 +0000547 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
Jim Grosbach913cc302012-03-30 21:54:22 +0000548 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
Jim Grosbach8648c102011-12-19 23:06:24 +0000549 return Value | (isAdd << 23);
550 }
Jim Grosbach3c685612010-12-08 20:32:07 +0000551 case ARM::fixup_arm_pcrel_10:
Owen Anderson4743d752010-12-10 22:46:47 +0000552 Value = Value - 4; // ARM fixups offset by an additional word and don't
Jim Grosbach3c685612010-12-08 20:32:07 +0000553 // need to adjust for the half-word ordering.
Joe Abbey8e72eb72014-09-16 09:18:23 +0000554 // Fall through.
Jim Grosbach3c685612010-12-08 20:32:07 +0000555 case ARM::fixup_t2_pcrel_10: {
556 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
Owen Anderson4743d752010-12-10 22:46:47 +0000557 Value = Value - 4;
Jason W Kimfc5c5222010-12-01 22:46:50 +0000558 bool isAdd = true;
559 if ((int64_t)Value < 0) {
560 Value = -Value;
561 isAdd = false;
562 }
563 // These values don't encode the low two bits since they're always zero.
564 Value >>= 2;
Jim Grosbache78031a2012-04-30 22:30:43 +0000565 if (Ctx && Value >= 256)
Jim Grosbach6f482002015-05-18 18:43:14 +0000566 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
Jason W Kimfc5c5222010-12-01 22:46:50 +0000567 Value |= isAdd << 23;
Jim Grosbach3c685612010-12-08 20:32:07 +0000568
Jim Grosbach8648c102011-12-19 23:06:24 +0000569 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
570 // swapped.
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000571 if (Kind == ARM::fixup_t2_pcrel_10)
572 return swapHalfWords(Value, IsLittleEndian);
Jim Grosbach3c685612010-12-08 20:32:07 +0000573
Jason W Kimfc5c5222010-12-01 22:46:50 +0000574 return Value;
575 }
576 }
577}
578
Jim Grosbache78031a2012-04-30 22:30:43 +0000579void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
580 const MCAsmLayout &Layout,
581 const MCFixup &Fixup,
582 const MCFragment *DF,
Rafael Espindola3e3de5e2014-03-28 16:06:09 +0000583 const MCValue &Target, uint64_t &Value,
Jim Grosbache78031a2012-04-30 22:30:43 +0000584 bool &IsResolved) {
585 const MCSymbolRefExpr *A = Target.getSymA();
586 // Some fixups to thumb function symbols need the low bit (thumb bit)
587 // twiddled.
588 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
589 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
590 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
591 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
592 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
593 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
594 if (A) {
Rafael Espindola972756b2015-04-06 16:10:05 +0000595 const MCSymbol &Sym = A->getSymbol();
Jim Grosbache78031a2012-04-30 22:30:43 +0000596 if (Asm.isThumbFunc(&Sym))
597 Value |= 1;
598 }
599 }
Logan Chiend5c48aa2014-02-05 14:15:16 +0000600 // For Thumb1 BL instruction, it is possible to be a long jump between
601 // the basic blocks of the same function. Thus, we would like to resolve
602 // the offset when the destination has the same MCFragment.
603 if (A && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
Rafael Espindola972756b2015-04-06 16:10:05 +0000604 const MCSymbol &Sym = A->getSymbol();
Rafael Espindola4d37b2a2015-05-29 21:45:01 +0000605 IsResolved = (Sym.getFragment() == DF);
Logan Chiend5c48aa2014-02-05 14:15:16 +0000606 }
Jim Grosbache78031a2012-04-30 22:30:43 +0000607 // We must always generate a relocation for BL/BLX instructions if we have
608 // a symbol to reference, as the linker relies on knowing the destination
609 // symbol's thumb-ness to get interworking right.
610 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
Jim Grosbache78031a2012-04-30 22:30:43 +0000611 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
612 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
613 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
614 IsResolved = false;
615
616 // Try to get the encoded value for the fixup as-if we're mapping it into
617 // the instruction. This allows adjustFixupValue() to issue a diagnostic
618 // if the value aren't invalid.
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000619 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(),
620 IsLittleEndian);
Jim Grosbache78031a2012-04-30 22:30:43 +0000621}
622
Bill Wendlingf09c44c2010-12-07 23:11:00 +0000623/// getFixupKindNumBytes - The number of bytes the fixup may change.
Jim Grosbach9d6d77a2010-11-11 18:04:49 +0000624static unsigned getFixupKindNumBytes(unsigned Kind) {
Jim Grosbach90987142010-11-09 01:37:15 +0000625 switch (Kind) {
Jim Grosbach9e199462010-12-06 23:57:07 +0000626 default:
627 llvm_unreachable("Unknown fixup kind!");
Bill Wendling8a6449c2010-12-08 01:57:09 +0000628
Jim Grosbach4416dfa2010-12-17 18:39:10 +0000629 case FK_Data_1:
Jim Grosbach78485ad2010-12-10 17:13:40 +0000630 case ARM::fixup_arm_thumb_bcc:
Bill Wendling8a6449c2010-12-08 01:57:09 +0000631 case ARM::fixup_arm_thumb_cp:
Jim Grosbach509dc2a2010-12-14 22:28:03 +0000632 case ARM::fixup_thumb_adr_pcrel_10:
Bill Wendling8a6449c2010-12-08 01:57:09 +0000633 return 1;
634
Jim Grosbach4416dfa2010-12-17 18:39:10 +0000635 case FK_Data_2:
Jim Grosbache119da12010-12-10 18:21:33 +0000636 case ARM::fixup_arm_thumb_br:
Jim Grosbach68b27eb2010-12-09 19:50:12 +0000637 case ARM::fixup_arm_thumb_cb:
Bill Wendlinga7d6aa92010-12-08 23:01:43 +0000638 return 2;
639
Jim Grosbach8648c102011-12-19 23:06:24 +0000640 case ARM::fixup_arm_pcrel_10_unscaled:
Jim Grosbach9e199462010-12-06 23:57:07 +0000641 case ARM::fixup_arm_ldst_pcrel_12:
642 case ARM::fixup_arm_pcrel_10:
643 case ARM::fixup_arm_adr_pcrel_12:
James Molloyfb5cd602012-03-30 09:15:32 +0000644 case ARM::fixup_arm_uncondbl:
645 case ARM::fixup_arm_condbl:
Jim Grosbach7b811d32012-02-27 21:36:23 +0000646 case ARM::fixup_arm_blx:
Jason W Kimd2e2f562011-02-04 19:47:15 +0000647 case ARM::fixup_arm_condbranch:
648 case ARM::fixup_arm_uncondbranch:
Jim Grosbach9e199462010-12-06 23:57:07 +0000649 return 3;
Bill Wendling8a6449c2010-12-08 01:57:09 +0000650
651 case FK_Data_4:
Owen Anderson3e6ee1d2010-12-09 01:51:07 +0000652 case ARM::fixup_t2_ldst_pcrel_12:
Owen Anderson578074b2010-12-13 19:31:11 +0000653 case ARM::fixup_t2_condbranch:
654 case ARM::fixup_t2_uncondbranch:
Owen Anderson0f7142d2010-12-08 00:18:36 +0000655 case ARM::fixup_t2_pcrel_10:
Owen Anderson6d375e52010-12-14 00:36:49 +0000656 case ARM::fixup_t2_adr_pcrel_12:
Jim Grosbach9e199462010-12-06 23:57:07 +0000657 case ARM::fixup_arm_thumb_bl:
Bill Wendling3392bfc2010-12-09 00:39:08 +0000658 case ARM::fixup_arm_thumb_blx:
Evan Chengd4a5c052011-01-14 02:38:49 +0000659 case ARM::fixup_arm_movt_hi16:
660 case ARM::fixup_arm_movw_lo16:
Evan Chengd4a5c052011-01-14 02:38:49 +0000661 case ARM::fixup_t2_movt_hi16:
662 case ARM::fixup_t2_movw_lo16:
Jim Grosbach9e199462010-12-06 23:57:07 +0000663 return 4;
Saleem Abdulrasool729c7a02014-05-04 23:13:15 +0000664
Saleem Abdulrasoolfc6b85b2014-05-08 01:35:57 +0000665 case FK_SecRel_2:
666 return 2;
Saleem Abdulrasool729c7a02014-05-04 23:13:15 +0000667 case FK_SecRel_4:
668 return 4;
Jim Grosbach90987142010-11-09 01:37:15 +0000669 }
670}
671
Christian Pirker2a111602014-03-28 14:35:30 +0000672/// getFixupKindContainerSizeBytes - The number of bytes of the
673/// container involved in big endian.
674static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
675 switch (Kind) {
676 default:
677 llvm_unreachable("Unknown fixup kind!");
678
679 case FK_Data_1:
680 return 1;
681 case FK_Data_2:
682 return 2;
683 case FK_Data_4:
684 return 4;
685
686 case ARM::fixup_arm_thumb_bcc:
687 case ARM::fixup_arm_thumb_cp:
688 case ARM::fixup_thumb_adr_pcrel_10:
689 case ARM::fixup_arm_thumb_br:
690 case ARM::fixup_arm_thumb_cb:
691 // Instruction size is 2 bytes.
692 return 2;
693
694 case ARM::fixup_arm_pcrel_10_unscaled:
695 case ARM::fixup_arm_ldst_pcrel_12:
696 case ARM::fixup_arm_pcrel_10:
697 case ARM::fixup_arm_adr_pcrel_12:
698 case ARM::fixup_arm_uncondbl:
699 case ARM::fixup_arm_condbl:
700 case ARM::fixup_arm_blx:
701 case ARM::fixup_arm_condbranch:
702 case ARM::fixup_arm_uncondbranch:
703 case ARM::fixup_t2_ldst_pcrel_12:
704 case ARM::fixup_t2_condbranch:
705 case ARM::fixup_t2_uncondbranch:
706 case ARM::fixup_t2_pcrel_10:
707 case ARM::fixup_t2_adr_pcrel_12:
708 case ARM::fixup_arm_thumb_bl:
709 case ARM::fixup_arm_thumb_blx:
710 case ARM::fixup_arm_movt_hi16:
711 case ARM::fixup_arm_movw_lo16:
Christian Pirker2a111602014-03-28 14:35:30 +0000712 case ARM::fixup_t2_movt_hi16:
713 case ARM::fixup_t2_movw_lo16:
Christian Pirker2a111602014-03-28 14:35:30 +0000714 // Instruction size is 4 bytes.
715 return 4;
716 }
717}
718
Benjamin Kramer07ea85a2012-11-24 14:36:43 +0000719void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
Rafael Espindola5904e122014-03-29 06:26:49 +0000720 unsigned DataSize, uint64_t Value,
721 bool IsPCRel) const {
Jim Grosbach9d6d77a2010-11-11 18:04:49 +0000722 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
Christian Pirkerfdce7ce2014-05-06 10:05:11 +0000723 Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian);
Joe Abbey8e72eb72014-09-16 09:18:23 +0000724 if (!Value)
725 return; // Doesn't change encoding.
Jim Grosbach90987142010-11-09 01:37:15 +0000726
Bill Wendlingf09c44c2010-12-07 23:11:00 +0000727 unsigned Offset = Fixup.getOffset();
728 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
729
Christian Pirker2a111602014-03-28 14:35:30 +0000730 // Used to point to big endian bytes.
731 unsigned FullSizeBytes;
Christian Pirker875629f2014-05-20 09:24:37 +0000732 if (!IsLittleEndian) {
Christian Pirker2a111602014-03-28 14:35:30 +0000733 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
Christian Pirker875629f2014-05-20 09:24:37 +0000734 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!");
735 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
736 }
Christian Pirker2a111602014-03-28 14:35:30 +0000737
Benjamin Kramer07ea85a2012-11-24 14:36:43 +0000738 // For each byte of the fragment that the fixup touches, mask in the bits from
739 // the fixup value. The Value has been "split up" into the appropriate
740 // bitfields above.
Christian Pirker2a111602014-03-28 14:35:30 +0000741 for (unsigned i = 0; i != NumBytes; ++i) {
742 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
743 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
744 }
Jason W Kimb3212452010-09-30 02:17:26 +0000745}
Bill Wendling721724e2010-12-07 23:05:20 +0000746
Vedant Kumar366dd9fd2015-08-21 21:52:48 +0000747static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
Chandler Carruthbb47b9a2015-08-30 02:09:48 +0000748 unsigned AK = ARM::parseArch(Arch);
Vedant Kumar366dd9fd2015-08-21 21:52:48 +0000749 switch (AK) {
750 default:
751 return MachO::CPU_SUBTYPE_ARM_V7;
752 case ARM::AK_ARMV4T:
753 return MachO::CPU_SUBTYPE_ARM_V4T;
754 case ARM::AK_ARMV6:
755 case ARM::AK_ARMV6K:
756 return MachO::CPU_SUBTYPE_ARM_V6;
757 case ARM::AK_ARMV5:
758 return MachO::CPU_SUBTYPE_ARM_V5;
759 case ARM::AK_ARMV5T:
760 case ARM::AK_ARMV5E:
761 case ARM::AK_ARMV5TE:
762 case ARM::AK_ARMV5TEJ:
763 return MachO::CPU_SUBTYPE_ARM_V5TEJ;
764 case ARM::AK_ARMV7:
765 return MachO::CPU_SUBTYPE_ARM_V7;
766 case ARM::AK_ARMV7S:
767 return MachO::CPU_SUBTYPE_ARM_V7S;
768 case ARM::AK_ARMV7K:
769 return MachO::CPU_SUBTYPE_ARM_V7K;
770 case ARM::AK_ARMV6M:
771 case ARM::AK_ARMV6SM:
772 return MachO::CPU_SUBTYPE_ARM_V6M;
773 case ARM::AK_ARMV7M:
774 return MachO::CPU_SUBTYPE_ARM_V7M;
775 case ARM::AK_ARMV7EM:
776 return MachO::CPU_SUBTYPE_ARM_V7EM;
777 }
778}
779
Bill Wendling58e2d3d2013-09-09 02:37:14 +0000780MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
Daniel Sanders418caf52015-06-10 10:35:34 +0000781 const MCRegisterInfo &MRI,
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000782 const TargetTuple &TT, StringRef CPU,
Daniel Sanders418caf52015-06-10 10:35:34 +0000783 bool isLittle) {
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000784 switch (TT.getObjectFormat()) {
Joe Abbey8e72eb72014-09-16 09:18:23 +0000785 default:
786 llvm_unreachable("unsupported object format");
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000787 case TargetTuple::MachO: {
788 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName());
789 return new ARMAsmBackendDarwin(T, TT, CS);
Owen Anderson975ddf82011-04-01 21:07:39 +0000790 }
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000791 case TargetTuple::COFF:
792 assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported");
793 return new ARMAsmBackendWinCOFF(T, TT);
794 case TargetTuple::ELF:
795 assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target");
796 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
797 return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
Saleem Abdulrasool84b952b2014-04-27 03:48:22 +0000798 }
Jason W Kimb3212452010-09-30 02:17:26 +0000799}
Christian Pirker2a111602014-03-28 14:35:30 +0000800
Christian Pirkerdc9ff752014-04-01 15:19:30 +0000801MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
Christian Pirker2a111602014-03-28 14:35:30 +0000802 const MCRegisterInfo &MRI,
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000803 const TargetTuple &TT,
804 StringRef CPU) {
Christian Pirker2a111602014-03-28 14:35:30 +0000805 return createARMAsmBackend(T, MRI, TT, CPU, true);
806}
807
Christian Pirkerdc9ff752014-04-01 15:19:30 +0000808MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
Christian Pirker2a111602014-03-28 14:35:30 +0000809 const MCRegisterInfo &MRI,
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000810 const TargetTuple &TT,
811 StringRef CPU) {
Christian Pirker2a111602014-03-28 14:35:30 +0000812 return createARMAsmBackend(T, MRI, TT, CPU, false);
813}
814
Christian Pirkerdc9ff752014-04-01 15:19:30 +0000815MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
Joe Abbey8e72eb72014-09-16 09:18:23 +0000816 const MCRegisterInfo &MRI,
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000817 const TargetTuple &TT,
818 StringRef CPU) {
Christian Pirker2a111602014-03-28 14:35:30 +0000819 return createARMAsmBackend(T, MRI, TT, CPU, true);
820}
821
Christian Pirkerdc9ff752014-04-01 15:19:30 +0000822MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
Joe Abbey8e72eb72014-09-16 09:18:23 +0000823 const MCRegisterInfo &MRI,
Daniel Sanders18d4b0d2015-09-15 13:17:40 +0000824 const TargetTuple &TT,
825 StringRef CPU) {
Christian Pirker2a111602014-03-28 14:35:30 +0000826 return createARMAsmBackend(T, MRI, TT, CPU, false);
827}