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gerrit-public.fairphone.software / toolchain / llvm-project / d229bfd20d2ed88116f8b6b1b6ec5424551638a0 / . / llvm / test / CodeGen / X86 / combine-smax.ll
blob: a7f339dba5d8033d1d3bcc44d136a4d65c8a0b17 [file] [log] [blame]
Simon Pilgrimd229bfd2018-02-10 23:38:50 +0000[diff] [blame^]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
9
10define <16 x i8> @test_v16i8_nosignbit(<16 x i8> %a, <16 x i8> %b) {
11; SSE2-LABEL: test_v16i8_nosignbit:
12; SSE2: # %bb.0:
13; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
14; SSE2-NEXT: pand %xmm2, %xmm0
15; SSE2-NEXT: pand %xmm2, %xmm1
16; SSE2-NEXT: movdqa %xmm0, %xmm2
17; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
18; SSE2-NEXT: pand %xmm2, %xmm0
19; SSE2-NEXT: pandn %xmm1, %xmm2
20; SSE2-NEXT: por %xmm0, %xmm2
21; SSE2-NEXT: movdqa %xmm2, %xmm0
22; SSE2-NEXT: retq
23;
24; SSE41-LABEL: test_v16i8_nosignbit:
25; SSE41: # %bb.0:
26; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
27; SSE41-NEXT: pand %xmm2, %xmm0
28; SSE41-NEXT: pand %xmm2, %xmm1
29; SSE41-NEXT: pmaxsb %xmm1, %xmm0
30; SSE41-NEXT: retq
31;
32; SSE42-LABEL: test_v16i8_nosignbit:
33; SSE42: # %bb.0:
34; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
35; SSE42-NEXT: pand %xmm2, %xmm0
36; SSE42-NEXT: pand %xmm2, %xmm1
37; SSE42-NEXT: pmaxsb %xmm1, %xmm0
38; SSE42-NEXT: retq
39;
40; AVX-LABEL: test_v16i8_nosignbit:
41; AVX: # %bb.0:
42; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
43; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
44; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1
45; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
46; AVX-NEXT: retq
47 %1 = and <16 x i8> %a, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
48 %2 = and <16 x i8> %b, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
49 %3 = icmp sgt <16 x i8> %1, %2
50 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
51 ret <16 x i8> %4
52}