blob: 014686feee0e056b37d6d4a48565ca445d5e4649 [file] [log] [blame]
David Peixotto6eecb282013-02-13 19:21:47 +00001;PR14492 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
2;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
3;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
4
Stephen Lind24ab202013-07-14 06:24:09 +00005;EXPECTED-LABEL: foo:
6;CHECK-LABEL: foo:
David Peixotto6eecb282013-02-13 19:21:47 +00007define i32 @foo(i32* %a) nounwind optsize {
8entry:
Manman Renf0499ba2013-04-29 22:58:55 +00009 %0 = load i32* %a, align 4
David Peixotto6eecb282013-02-13 19:21:47 +000010 %arrayidx1 = getelementptr inbounds i32* %a, i32 1
Manman Renf0499ba2013-04-29 22:58:55 +000011 %1 = load i32* %arrayidx1, align 4
David Peixotto6eecb282013-02-13 19:21:47 +000012 %arrayidx2 = getelementptr inbounds i32* %a, i32 2
Manman Renf0499ba2013-04-29 22:58:55 +000013 %2 = load i32* %arrayidx2, align 4
David Peixotto6eecb282013-02-13 19:21:47 +000014 %add.ptr = getelementptr inbounds i32* %a, i32 3
15;Make sure we do not have a duplicated register in the front of the reg list
16;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
17;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]],
18 tail call void @bar(i32* %add.ptr) nounwind optsize
19 %add = add nsw i32 %1, %0
20 %add3 = add nsw i32 %add, %2
21 ret i32 %add3
22}
23
24declare void @bar(i32*) optsize