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gerrit-public.fairphone.software / toolchain / llvm-project / d24ab20e9b11d2076d8b9d5cd96f41a6b9c399fb / . / llvm / test / CodeGen / ARM / fast-isel-ext.ll
blob: 15d0d3ce5f681a0892700f0cfdc7d80ee70299cf [file] [log] [blame]
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]1; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=v7
JF Bastien18db1f22013-06-14 02:49:43 +0000[diff] [blame]2; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=v7
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]3; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios | FileCheck %s --check-prefix=prev6
JF Bastien18db1f22013-06-14 02:49:43 +0000[diff] [blame]4; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi | FileCheck %s --check-prefix=prev6
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]5; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios | FileCheck %s --check-prefix=prev6
JF Bastien18db1f22013-06-14 02:49:43 +0000[diff] [blame]6; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi | FileCheck %s --check-prefix=prev6
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]7; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=v7
8
9; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
10; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
11; using two shifts.
12
13; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
14; and therefore must set flags. {{s?}} below denotes this, instead of
15; duplicating tests.
16
17; zext
18
19define i8 @zext_1_8(i1 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]20; v7-LABEL: zext_1_8:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]21; v7: and r0, r0, #1
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]22; prev6-LABEL: zext_1_8:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]23; prev6: and r0, r0, #1
24 %r = zext i1 %a to i8
25 ret i8 %r
26}
27
28define i16 @zext_1_16(i1 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]29; v7-LABEL: zext_1_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]30; v7: and r0, r0, #1
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]31; prev6-LABEL: zext_1_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]32; prev6: and r0, r0, #1
33 %r = zext i1 %a to i16
34 ret i16 %r
35}
36
37define i32 @zext_1_32(i1 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]38; v7-LABEL: zext_1_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]39; v7: and r0, r0, #1
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]40; prev6-LABEL: zext_1_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]41; prev6: and r0, r0, #1
42 %r = zext i1 %a to i32
43 ret i32 %r
44}
45
46define i16 @zext_8_16(i8 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]47; v7-LABEL: zext_8_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]48; v7: and r0, r0, #255
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]49; prev6-LABEL: zext_8_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]50; prev6: and r0, r0, #255
51 %r = zext i8 %a to i16
52 ret i16 %r
53}
54
55define i32 @zext_8_32(i8 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]56; v7-LABEL: zext_8_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]57; v7: and r0, r0, #255
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]58; prev6-LABEL: zext_8_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]59; prev6: and r0, r0, #255
60 %r = zext i8 %a to i32
61 ret i32 %r
62}
63
64define i32 @zext_16_32(i16 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]65; v7-LABEL: zext_16_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]66; v7: uxth r0, r0
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]67; prev6-LABEL: zext_16_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]68; prev6: lsl{{s?}} r0, r0, #16
69; prev6: lsr{{s?}} r0, r0, #16
70 %r = zext i16 %a to i32
71 ret i32 %r
72}
73
74; sext
75
76define i8 @sext_1_8(i1 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]77; v7-LABEL: sext_1_8:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]78; v7: lsl{{s?}} r0, r0, #31
79; v7: asr{{s?}} r0, r0, #31
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]80; prev6-LABEL: sext_1_8:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]81; prev6: lsl{{s?}} r0, r0, #31
82; prev6: asr{{s?}} r0, r0, #31
83 %r = sext i1 %a to i8
84 ret i8 %r
85}
86
87define i16 @sext_1_16(i1 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]88; v7-LABEL: sext_1_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]89; v7: lsl{{s?}} r0, r0, #31
90; v7: asr{{s?}} r0, r0, #31
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]91; prev6-LABEL: sext_1_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]92; prev6: lsl{{s?}} r0, r0, #31
93; prev6: asr{{s?}} r0, r0, #31
94 %r = sext i1 %a to i16
95 ret i16 %r
96}
97
98define i32 @sext_1_32(i1 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]99; v7-LABEL: sext_1_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]100; v7: lsl{{s?}} r0, r0, #31
101; v7: asr{{s?}} r0, r0, #31
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]102; prev6-LABEL: sext_1_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]103; prev6: lsl{{s?}} r0, r0, #31
104; prev6: asr{{s?}} r0, r0, #31
105 %r = sext i1 %a to i32
106 ret i32 %r
107}
108
109define i16 @sext_8_16(i8 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]110; v7-LABEL: sext_8_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]111; v7: sxtb r0, r0
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]112; prev6-LABEL: sext_8_16:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]113; prev6: lsl{{s?}} r0, r0, #24
114; prev6: asr{{s?}} r0, r0, #24
115 %r = sext i8 %a to i16
116 ret i16 %r
117}
118
119define i32 @sext_8_32(i8 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]120; v7-LABEL: sext_8_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]121; v7: sxtb r0, r0
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]122; prev6-LABEL: sext_8_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]123; prev6: lsl{{s?}} r0, r0, #24
124; prev6: asr{{s?}} r0, r0, #24
125 %r = sext i8 %a to i32
126 ret i32 %r
127}
128
129define i32 @sext_16_32(i16 %a) nounwind ssp {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]130; v7-LABEL: sext_16_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]131; v7: sxth r0, r0
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame^]132; prev6-LABEL: sext_16_32:
JF Bastien06ce03d2013-06-07 20:10:37 +0000[diff] [blame]133; prev6: lsl{{s?}} r0, r0, #16
134; prev6: asr{{s?}} r0, r0, #16
135 %r = sext i16 %a to i32
136 ret i32 %r
137}