blob: 9e511fce956f11dc9f25401f3b5e97873c20a282 [file] [log] [blame]
Anton Korobeynikov568afeb2012-11-21 17:28:27 +00001; RUN: llc < %s | FileCheck %s
2
3target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
4target triple = "msp430---elf"
5
6declare void @llvm.va_start(i8*) nounwind
7declare void @llvm.va_end(i8*) nounwind
8declare void @llvm.va_copy(i8*, i8*) nounwind
9
10define void @va_start(i16 %a, ...) nounwind {
11entry:
Stephen Lind24ab202013-07-14 06:24:09 +000012; CHECK-LABEL: va_start:
Anton Korobeynikov568afeb2012-11-21 17:28:27 +000013; CHECK: sub.w #2, r1
14 %vl = alloca i8*, align 2
15 %vl1 = bitcast i8** %vl to i8*
16; CHECK-NEXT: mov.w r1, [[REG:r[0-9]+]]
17; CHECK-NEXT: add.w #6, [[REG]]
18; CHECK-NEXT: mov.w [[REG]], 0(r1)
19 call void @llvm.va_start(i8* %vl1)
20 call void @llvm.va_end(i8* %vl1)
21 ret void
22}
23
24define i16 @va_arg(i8* %vl) nounwind {
25entry:
Stephen Lind24ab202013-07-14 06:24:09 +000026; CHECK-LABEL: va_arg:
Anton Korobeynikov568afeb2012-11-21 17:28:27 +000027 %vl.addr = alloca i8*, align 2
28; CHECK: mov.w r15, 0(r1)
29 store i8* %vl, i8** %vl.addr, align 2
30; CHECK: mov.w r15, [[REG:r[0-9]+]]
31; CHECK-NEXT: add.w #2, [[REG]]
32; CHECK-NEXT: mov.w [[REG]], 0(r1)
33 %0 = va_arg i8** %vl.addr, i16
34; CHECK-NEXT: mov.w 0(r15), r15
35 ret i16 %0
36}
37
38define void @va_copy(i8* %vl) nounwind {
39entry:
Stephen Lind24ab202013-07-14 06:24:09 +000040; CHECK-LABEL: va_copy:
Anton Korobeynikov568afeb2012-11-21 17:28:27 +000041 %vl.addr = alloca i8*, align 2
42 %vl2 = alloca i8*, align 2
43; CHECK: mov.w r15, 2(r1)
44 store i8* %vl, i8** %vl.addr, align 2
45 %0 = bitcast i8** %vl2 to i8*
46 %1 = bitcast i8** %vl.addr to i8*
47; CHECK-NEXT: mov.w r15, 0(r1)
48 call void @llvm.va_copy(i8* %0, i8* %1)
49 ret void
50}