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gerrit-public.fairphone.software / toolchain / llvm-project / d3d086d6794e901bde43b1c1a374a4b1d571d7e7 / . / llvm / lib / Target / SparcV9 / SparcV9Instr.def
blob: 53d24a596a441678bb35bc986fae7510cde0ff61 [file] [log] [blame]
Brian Gaeke03cac372004-04-25 07:04:49 +0000[diff] [blame]1//===-- SparcV9Instr.def - SparcV9 Instruction Information -------*- C++ -*-==//
John Criswell29265fe2003-10-21 15:17:13 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]9//
10// This file describes all of the instructions that the sparc backend uses. It
11// relys on an external 'I' macro being defined that takes the arguments
Chris Lattner1e5e3f02002-10-25 01:43:26 +0000[diff] [blame]12// specified below, and is used to make all of the information relevant to an
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]13// instruction be in one place.
14//
15//===----------------------------------------------------------------------===//
16
17// NOTE: No include guards desired
18
19#ifndef I
20#errror "Must define I macro before including SparcInstr.def!"
21#endif
22
23// Constants for defining the maximum constant size field.
24// One #define per bit size
25//
26#define B5 ((1 << 5) - 1)
27#define B6 ((1 << 6) - 1)
28#define B12 ((1 << 12) - 1)
29#define B15 ((1 << 15) - 1)
30#define B18 ((1 << 18) - 1)
31#define B21 ((1 << 21) - 1)
32#define B22 ((1 << 22) - 1)
33#define B29 ((1 << 29) - 1)
34
35// Arguments passed into the I macro
36// enum name,
37// opCodeString,
38// numOperands,
39// resultPosition (0-based; -1 if no result),
40// maxImmedConst,
41// immedIsSignExtended,
42// numDelaySlots (in cycles)
43// latency (in cycles)
44// instr sched class (defined above)
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]45// instr class flags (defined in TargetInstrInfo.h)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]46
Brian Gaeke186e3d102004-07-02 04:57:37 +0000[diff] [blame]47#define BRANCHFLAGS M_BRANCH_FLAG|M_TERMINATOR_FLAG
48#define RETFLAGS M_RET_FLAG|M_TERMINATOR_FLAG
Ruchira Sasanka9d8950d2001-11-03 19:59:59 +0000[diff] [blame]49
Vikram S. Adve40378e32001-09-30 23:46:57 +0000[diff] [blame]50I(NOP, "nop", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]51
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]52// Set high-order bits of register and clear low-order bits
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]53I(SETHI, "sethi", 2, 1, B22, false, 0, 1, SPARC_IEUN, 0)
Vikram S. Adve40378e32001-09-30 23:46:57 +0000[diff] [blame]54
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]55// Add or add with carry.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]56I(ADDr , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
57I(ADDi , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
58I(ADDccr, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
59I(ADDcci, "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
60I(ADDCr , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
61I(ADDCi , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
62I(ADDCccr, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
63I(ADDCcci, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]64
65// Subtract or subtract with carry.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]66I(SUBr , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
67I(SUBi , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
68I(SUBccr , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
69I(SUBcci , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
70I(SUBCr , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
71I(SUBCi , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
72I(SUBCccr, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
73I(SUBCcci, "subccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]74
75// Integer multiply, signed divide, unsigned divide.
76// Note that the deprecated 32-bit multiply and multiply-step are not used.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]77I(MULXr , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, 0)
78I(MULXi , "mulx", 3, 2, B12, true , 0, 3, SPARC_IEUN, 0)
79I(SDIVXr, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
80I(SDIVXi, "sdivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
81I(UDIVXr, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
82I(UDIVXi, "udivx", 3, 2, B12, true , 0, 6, SPARC_IEUN, 0)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]83
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]84 // Floating point add, subtract, compare.
85 // Note that destination of FCMP* instructions is operand 0, not operand 2.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]86I(FADDS, "fadds", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
87I(FADDD, "faddd", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
88I(FADDQ, "faddq", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
89I(FSUBS, "fsubs", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
90I(FSUBD, "fsubd", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
91I(FSUBQ, "fsubq", 3, 2, 0, false, 0, 3, SPARC_FPA, 0)
92I(FCMPS, "fcmps", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
93I(FCMPD, "fcmpd", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
94I(FCMPQ, "fcmpq", 3, 0, 0, false, 0, 3, SPARC_FPA, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]95// NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
Vikram S. Advea5619eb2001-10-28 21:41:01 +0000[diff] [blame]96
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]97// Floating point multiply or divide.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]98I(FMULS , "fmuls", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
99I(FMULD , "fmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
100I(FMULQ , "fmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
101I(FSMULD, "fsmuld", 3, 2, 0, false, 0, 3, SPARC_FPM, 0)
102I(FDMULQ, "fdmulq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
103I(FDIVS , "fdivs", 3, 2, 0, false, 0, 12, SPARC_FPM, 0)
104I(FDIVD , "fdivd", 3, 2, 0, false, 0, 22, SPARC_FPM, 0)
105I(FDIVQ , "fdivq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
106I(FSQRTS, "fsqrts", 3, 2, 0, false, 0, 12, SPARC_FPM, 0)
107I(FSQRTD, "fsqrtd", 3, 2, 0, false, 0, 22, SPARC_FPM, 0)
108I(FSQRTQ, "fsqrtq", 3, 2, 0, false, 0, 0, SPARC_FPM, 0)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]109
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]110// Logical operations
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]111I(ANDr , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
112I(ANDi , "and", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
113I(ANDccr , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
114I(ANDcci , "andcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
115I(ANDNr , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
116I(ANDNi , "andn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
117I(ANDNccr, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
118I(ANDNcci, "andncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
Misha Brukmandb69beb2003-05-27 22:32:38 +0000[diff] [blame]119
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]120I(ORr , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
121I(ORi , "or", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
122I(ORccr , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
123I(ORcci , "orcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
124I(ORNr , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
125I(ORNi , "orn", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
126I(ORNccr, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
127I(ORNcci, "orncc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
Misha Brukmandb69beb2003-05-27 22:32:38 +0000[diff] [blame]128
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]129I(XORr , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
130I(XORi , "xor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
131I(XORccr , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
132I(XORcci , "xorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
133I(XNORr , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
134I(XNORi , "xnor", 3, 2, B12, true , 0, 1, SPARC_IEUN, 0)
135I(XNORccr, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
136I(XNORcci, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, 0)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]137
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]138// Shift operations
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]139I(SLLr5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
140I(SLLi5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
141I(SRLr5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
142I(SRLi5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
143I(SRAr5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
144I(SRAi5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, 0)
145I(SLLXr6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
146I(SLLXi6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
147I(SRLXr6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
148I(SRLXi6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
149I(SRAXr6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
150I(SRAXi6, "srax", 3, 2, B6, true , 0, 1, SPARC_IEU0, 0)
Misha Brukmandb69beb2003-05-27 22:32:38 +0000[diff] [blame]151
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]152// Floating point move, negate, and abs instructions
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]153I(FMOVS, "fmovs", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
154I(FMOVD, "fmovd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
155//I(FMOVQ, "fmovq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
156I(FNEGS, "fnegs", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
157I(FNEGD, "fnegd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
158//I(FNEGQ, "fnegq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
159I(FABSS, "fabss", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
160I(FABSD, "fabsd", 2, 1, 0, false, 0, 1, SPARC_FPA, 0)
161//I(FABSQ, "fabsq", 2, 1, 0, false, 0, ?, SPARC_FPA, 0)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]162
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]163// Convert from floating point to floating point formats
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]164I(FSTOD, "fstod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
165I(FSTOQ, "fstoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
166I(FDTOS, "fdtos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
167I(FDTOQ, "fdtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
168I(FQTOS, "fqtos", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
169I(FQTOD, "fqtod", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]170
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]171// Convert from floating point to integer formats.
172// Note that this accesses both integer and floating point registers.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]173I(FSTOX, "fstox", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
174I(FDTOX, "fdtox", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
175I(FQTOX, "fqtox", 2, 1, 0, false, 0, 2, SPARC_FPA, 0)
176I(FSTOI, "fstoi", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
177I(FDTOI, "fdtoi", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
178I(FQTOI, "fqtoi", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]179
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]180// Convert from integer to floating point formats
181// Note that this accesses both integer and floating point registers.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]182I(FXTOS, "fxtos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
183I(FXTOD, "fxtod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
184I(FXTOQ, "fxtoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
185I(FITOS, "fitos", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
186I(FITOD, "fitod", 2, 1, 0, false, 0, 3, SPARC_FPA, 0)
187I(FITOQ, "fitoq", 2, 1, 0, false, 0, 0, SPARC_FPA, 0)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]188
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]189// Branch on integer comparison with zero.
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]190// Latency excludes the delay slot since it can be issued in same cycle.
Brian Gaeke186e3d102004-07-02 04:57:37 +0000[diff] [blame]191I(BRZ , "brz", 2, -1, B15, true , 1, 1, SPARC_CTI, BRANCHFLAGS)
192I(BRLEZ, "brlez", 2, -1, B15, true , 1, 1, SPARC_CTI, BRANCHFLAGS)
193I(BRLZ , "brlz", 2, -1, B15, true , 1, 1, SPARC_CTI, BRANCHFLAGS)
194I(BRNZ , "brnz", 2, -1, B15, true , 1, 1, SPARC_CTI, BRANCHFLAGS)
195I(BRGZ , "brgz", 2, -1, B15, true , 1, 1, SPARC_CTI, BRANCHFLAGS)
196I(BRGEZ, "brgez", 2, -1, B15, true , 1, 1, SPARC_CTI, BRANCHFLAGS)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]197
198// Branch on integer condition code.
199// The first argument specifies the ICC register: %icc or %xcc
200// Latency includes the delay slot.
Brian Gaeke186e3d102004-07-02 04:57:37 +0000[diff] [blame]201I(BA , "ba", 1, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
202I(BN , "bn", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
203I(BNE , "bne", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
204I(BE , "be", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
205I(BG , "bg", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
206I(BLE , "ble", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
207I(BGE , "bge", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
208I(BL , "bl", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
209I(BGU , "bgu", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
210I(BLEU, "bleu", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
211I(BCC , "bcc", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
212I(BCS , "bcs", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
213I(BPOS, "bpos", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
214I(BNEG, "bneg", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
215I(BVC , "bvc", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
216I(BVS , "bvs", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]217
218// Branch on floating point condition code.
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]219// The first argument is the FCCn register (0 <= n <= 3).
220// Latency includes the delay slot.
Brian Gaeke186e3d102004-07-02 04:57:37 +0000[diff] [blame]221I(FBA , "fba", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
222I(FBN , "fbn", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
223I(FBU , "fbu", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
224I(FBG , "fbg", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
225I(FBUG , "fbug", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
226I(FBL , "fbl", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
227I(FBUL , "fbul", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
228I(FBLG , "fblg", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
229I(FBNE , "fbne", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
230I(FBE , "fbe", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
231I(FBUE , "fbue", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
232I(FBGE , "fbge", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
233I(FBUGE, "fbuge", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
234I(FBLE , "fble", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
235I(FBULE, "fbule", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
236I(FBO , "fbo", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG|BRANCHFLAGS)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]237
238// Conditional move on integer comparison with zero.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]239I(MOVRZr , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
240I(MOVRZi , "movrz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
241I(MOVRLEZr, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
242I(MOVRLEZi, "movrlez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
243I(MOVRLZr , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
244I(MOVRLZi , "movrlz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
245I(MOVRNZr , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
246I(MOVRNZi , "movrnz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
247I(MOVRGZr , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
248I(MOVRGZi , "movrgz", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
249I(MOVRGEZr, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
250I(MOVRGEZi, "movrgez", 3, 2, B12, true , 0, 2, SPARC_SINGLE, 0)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]251
252// Conditional move on integer condition code.
253// The first argument specifies the ICC register: %icc or %xcc
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]254I(MOVAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
255I(MOVAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
256I(MOVNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
257I(MOVNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
258I(MOVNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
259I(MOVNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
260I(MOVEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
261I(MOVEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
262I(MOVGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
263I(MOVGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
264I(MOVLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
265I(MOVLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
266I(MOVGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
267I(MOVGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
268I(MOVLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
269I(MOVLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
270I(MOVGUr , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
271I(MOVGUi , "movgu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
272I(MOVLEUr, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
273I(MOVLEUi, "movleu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
274I(MOVCCr , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
275I(MOVCCi , "movcc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
276I(MOVCSr , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
277I(MOVCSi , "movcs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
278I(MOVPOSr, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
279I(MOVPOSi, "movpos", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
280I(MOVNEGr, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
281I(MOVNEGi, "movneg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
282I(MOVVCr , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
283I(MOVVCi , "movvc", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
284I(MOVVSr , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
285I(MOVVSi , "movvs", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]286
287// Conditional move (of integer register) on floating point condition code.
288// The first argument is the FCCn register (0 <= n <= 3).
289// Note that the enum name above is not the same as the assembly mnemonic
290// because some of the assembly mnemonics are the same as the move on
291// integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]292I(MOVFAr , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
293I(MOVFAi , "mova", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
294I(MOVFNr , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
295I(MOVFNi , "movn", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
296I(MOVFUr , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
297I(MOVFUi , "movu", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
298I(MOVFGr , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
299I(MOVFGi , "movg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
300I(MOVFUGr , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
301I(MOVFUGi , "movug", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
302I(MOVFLr , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
303I(MOVFLi , "movl", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
304I(MOVFULr , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
305I(MOVFULi , "movul", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
306I(MOVFLGr , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
307I(MOVFLGi , "movlg", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
308I(MOVFNEr , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
309I(MOVFNEi , "movne", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
310I(MOVFEr , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
311I(MOVFEi , "move", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
312I(MOVFUEr , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
313I(MOVFUEi , "movue", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
314I(MOVFGEr , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
315I(MOVFGEi , "movge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
316I(MOVFUGEr, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
317I(MOVFUGEi, "movuge", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
318I(MOVFLEr , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
319I(MOVFLEi , "movle", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
320I(MOVFULEr, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
321I(MOVFULEi, "movule", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
322I(MOVFOr , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
323I(MOVFOi , "movo", 3, 2, B12, true , 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]324
325// Conditional move of floating point register on each of the above:
326// i. on integer comparison with zero.
327// ii. on integer condition code
328// iii. on floating point condition code
329// Note that the same set is repeated for S,D,Q register classes.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]330I(FMOVRSZ ,"fmovrsz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
331I(FMOVRSLEZ,"fmovrslez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
332I(FMOVRSLZ ,"fmovrslz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
333I(FMOVRSNZ ,"fmovrsnz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
334I(FMOVRSGZ ,"fmovrsgz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
335I(FMOVRSGEZ,"fmovrsgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]336
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]337I(FMOVSA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
338I(FMOVSN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
339I(FMOVSNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
340I(FMOVSE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
341I(FMOVSG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
342I(FMOVSLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
343I(FMOVSGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
344I(FMOVSL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
345I(FMOVSGU , "fmovsgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
346I(FMOVSLEU, "fmovsleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
347I(FMOVSCC , "fmovscc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
348I(FMOVSCS , "fmovscs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
349I(FMOVSPOS, "fmovspos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
350I(FMOVSNEG, "fmovsneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
351I(FMOVSVC , "fmovsvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
352I(FMOVSVS , "fmovsvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]353
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]354I(FMOVSFA , "fmovsa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
355I(FMOVSFN , "fmovsn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
356I(FMOVSFU , "fmovsu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
357I(FMOVSFG , "fmovsg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
358I(FMOVSFUG , "fmovsug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
359I(FMOVSFL , "fmovsl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
360I(FMOVSFUL , "fmovsul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
361I(FMOVSFLG , "fmovslg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
362I(FMOVSFNE , "fmovsne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
363I(FMOVSFE , "fmovse", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
364I(FMOVSFUE , "fmovsue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
365I(FMOVSFGE , "fmovsge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
366I(FMOVSFUGE, "fmovsuge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
367I(FMOVSFLE , "fmovsle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
368I(FMOVSFULE, "fmovslue",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
369I(FMOVSFO , "fmovso", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]370
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]371I(FMOVRDZ , "fmovrdz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
372I(FMOVRDLEZ, "fmovrdlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
373I(FMOVRDLZ , "fmovrdlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
374I(FMOVRDNZ , "fmovrdnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
375I(FMOVRDGZ , "fmovrdgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
376I(FMOVRDGEZ, "fmovrdgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]377
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]378I(FMOVDA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
379I(FMOVDN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
380I(FMOVDNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
381I(FMOVDE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
382I(FMOVDG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
383I(FMOVDLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
384I(FMOVDGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
385I(FMOVDL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
386I(FMOVDGU , "fmovdgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
387I(FMOVDLEU, "fmovdleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
388I(FMOVDCC , "fmovdcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
389I(FMOVDCS , "fmovdcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
390I(FMOVDPOS, "fmovdpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
391I(FMOVDNEG, "fmovdneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
392I(FMOVDVC , "fmovdvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
393I(FMOVDVS , "fmovdvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]394
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]395I(FMOVDFA , "fmovda", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
396I(FMOVDFN , "fmovdn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
397I(FMOVDFU , "fmovdu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
398I(FMOVDFG , "fmovdg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
399I(FMOVDFUG , "fmovdug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
400I(FMOVDFL , "fmovdl", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
401I(FMOVDFUL , "fmovdul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
402I(FMOVDFLG , "fmovdlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
403I(FMOVDFNE , "fmovdne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
404I(FMOVDFE , "fmovde", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
405I(FMOVDFUE , "fmovdue", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
406I(FMOVDFGE , "fmovdge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
407I(FMOVDFUGE, "fmovduge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
408I(FMOVDFLE , "fmovdle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
409I(FMOVDFULE, "fmovdule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
410I(FMOVDFO , "fmovdo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]411
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]412I(FMOVRQZ , "fmovrqz", 3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
413I(FMOVRQLEZ, "fmovrqlez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
414I(FMOVRQLZ , "fmovrqlz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
415I(FMOVRQNZ , "fmovrqnz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
416I(FMOVRQGZ , "fmovrqgz",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
417I(FMOVRQGEZ, "fmovrqgez",3, 2, 0, false, 0, 2, SPARC_SINGLE, 0)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]418
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]419I(FMOVQA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
420I(FMOVQN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
421I(FMOVQNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
422I(FMOVQE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
423I(FMOVQG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
424I(FMOVQLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
425I(FMOVQGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
426I(FMOVQL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
427I(FMOVQGU , "fmovqgu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
428I(FMOVQLEU, "fmovqleu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
429I(FMOVQCC , "fmovqcc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
430I(FMOVQCS , "fmovqcs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
431I(FMOVQPOS, "fmovqpos", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
432I(FMOVQNEG, "fmovqneg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
433I(FMOVQVC , "fmovqvc", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
434I(FMOVQVS , "fmovqvs", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]435
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]436I(FMOVQFA , "fmovqa", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
437I(FMOVQFN , "fmovqn", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
438I(FMOVQFU , "fmovqu", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
439I(FMOVQFG , "fmovqg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
440I(FMOVQFUG , "fmovqug", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
441I(FMOVQFL , "fmovql", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
442I(FMOVQFUL , "fmovqul", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
443I(FMOVQFLG , "fmovqlg", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
444I(FMOVQFNE , "fmovqne", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
445I(FMOVQFE , "fmovqe", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
446I(FMOVQFUE , "fmovque", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
447I(FMOVQFGE , "fmovqge", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
448I(FMOVQFUGE, "fmovquge",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
449I(FMOVQFLE , "fmovqle", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
450I(FMOVQFULE, "fmovqule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG )
451I(FMOVQFO , "fmovqo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]452
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]453// Load integer instructions
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]454// Latency includes 1 cycle for address generation (Sparc IIi),
455// plus 3 cycles assumed for average miss penalty (bias towards L1 hits).
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]456// Signed loads of less than 64 bits need an extra cycle for sign-extension.
457//
458// Not reflected here: After a 3-cycle loads, all subsequent consecutive
459// loads also require 3 cycles to avoid contention for the load return
460// stage. Latency returns to 2 cycles after the first cycle with no load.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]461I(LDSBr, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
462I(LDSBi, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
463I(LDSHr, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
464I(LDSHi, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
465I(LDSWr, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
466I(LDSWi, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_LOAD_FLAG)
467I(LDUBr, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
468I(LDUBi, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
469I(LDUHr, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
470I(LDUHi, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
471I(LDUWr, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
472I(LDUWi, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
473I(LDXr , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
474I(LDXi , "ldx" , 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]475
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]476// Load floating-point instructions
477// Latency includes 1 cycle for address generation (Sparc IIi)
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]478I(LDFr , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
479I(LDFi , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
480I(LDDFr, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
481I(LDDFi, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
482I(LDQFr, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
483I(LDQFi, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
484I(LDFSRr, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
485I(LDFSRi, "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
486I(LDXFSRr, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
487I(LDXFSRi, "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_LOAD_FLAG)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]488
489// Store integer instructions.
490// Requires 1 cycle for address generation (Sparc IIi).
491// Default latency is 0 because value is not explicitly used.
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]492I(STBr, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
493I(STBi, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
494I(STHr, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
495I(STHi, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
496I(STWr, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
497I(STWi, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
498I(STXr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
499I(STXi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]500
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]501// Store floating-point instructions (Sparc IIi)
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]502I(STFr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
503I(STFi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
504I(STDFr, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
505I(STDFi, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
506I(STFSRr, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
507I(STFSRi, "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
508I(STXFSRr, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
509I(STXFSRi, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_STORE_FLAG)
Vikram S. Advebe08b5e2002-03-24 03:33:53 +0000[diff] [blame]510
Vikram S. Adved76d82b2002-09-28 17:00:15 +0000[diff] [blame]511// Call, Return and "Jump and link". Operand (2) for JMPL is marked as
512// a "result" because JMPL stores the return address for the call in it.
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]513// Latency includes the delay slot.
Brian Gaeke186e3d102004-07-02 04:57:37 +0000[diff] [blame]514I(CALL, "call", 1, -1, B29, true , 1, 2, SPARC_CTI, M_CALL_FLAG)
515I(JMPLCALLr, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, M_CALL_FLAG)
516I(JMPLCALLi, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, M_CALL_FLAG)
517I(JMPLRETr, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, RETFLAGS)
518I(JMPLRETi, "jmpl", 3, 2, B12, true , 1, 2, SPARC_CTI, RETFLAGS)
Vikram S. Adveea5d1f52001-11-04 19:34:49 +0000[diff] [blame]519
Vikram S. Adve6b492dd2001-10-22 13:32:55 +0000[diff] [blame]520// SAVE and restore instructions
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]521I(SAVEr, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
522I(SAVEi, "save", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
523I(RESTOREr, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
524I(RESTOREi, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, 0)
Vikram S. Adve6b492dd2001-10-22 13:32:55 +0000[diff] [blame]525
Ruchira Sasanka9d8950d2001-11-03 19:59:59 +0000[diff] [blame]526// Read and Write CCR register from/to an int reg
Chris Lattner71a899d2004-02-29 05:58:30 +0000[diff] [blame]527I(RDCCR, "rd", 2, 1, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
528I(WRCCRr, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
529I(WRCCRi, "wr", 3, 2, 0, false, 0, 1, SPARC_SINGLE, M_CC_FLAG)
Ruchira Sasanka9d8950d2001-11-03 19:59:59 +0000[diff] [blame]530
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]531// Synthetic phi operation for near-SSA form of machine code
532// Number of operands is variable, indicated by -1. Result is the first op.
Brian Gaeke1936ce72004-08-18 20:04:28 +0000[diff] [blame]533I(PHI, "<phi>", -1, 0, 0, false, 0, 0, SPARC_NONE, 0)
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]534
535#undef B5
536#undef B6
537#undef B12
538#undef B15
539#undef B18
540#undef B21
541#undef B22
542#undef B29
543
Brian Gaeke186e3d102004-07-02 04:57:37 +0000[diff] [blame]544#undef BRANCHFLAGS
545#undef RETFLAGS
546
Chris Lattnere86a0232001-09-19 15:56:23 +0000[diff] [blame]547#undef I