| Hal Finkel | 2b655bb | 2013-11-30 19:39:27 +0000 | [diff] [blame] | 1 | ; RUN: llc -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s |
| 2 | ; RUN: llc -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s |
| Roman Divacky | 32143e2 | 2013-12-20 18:08:54 +0000 | [diff] [blame] | 3 | ; RUN: llc -O0 < %s -march=ppc32 -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s |
| Roman Divacky | e3f15c98 | 2012-06-04 17:36:38 +0000 | [diff] [blame] | 4 | |
| Tim Northover | 444eba2 | 2013-12-12 11:51:23 +0000 | [diff] [blame] | 5 | target triple = "powerpc64-unknown-linux-gnu" |
| 6 | |
| Roman Divacky | e3f15c98 | 2012-06-04 17:36:38 +0000 | [diff] [blame] | 7 | @a = thread_local global i32 0, align 4 |
| 8 | |
| Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 9 | ;OPT0-LABEL: localexec: |
| 10 | ;OPT1-LABEL: localexec: |
| Roman Divacky | e3f15c98 | 2012-06-04 17:36:38 +0000 | [diff] [blame] | 11 | define i32 @localexec() nounwind { |
| 12 | entry: |
| Bill Schmidt | b454829 | 2013-02-25 16:44:35 +0000 | [diff] [blame] | 13 | ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha |
| 14 | ;OPT0-NEXT: li [[REG2:[0-9]+]], 42 |
| 15 | ;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l |
| Bill Schmidt | a1b72d0 | 2013-03-27 02:40:14 +0000 | [diff] [blame] | 16 | ;OPT0: stw [[REG2]], 0([[REG1]]) |
| Bill Schmidt | b454829 | 2013-02-25 16:44:35 +0000 | [diff] [blame] | 17 | ;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha |
| 18 | ;OPT1-NEXT: li [[REG2:[0-9]+]], 42 |
| 19 | ;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]]) |
| Roman Divacky | e3f15c98 | 2012-06-04 17:36:38 +0000 | [diff] [blame] | 20 | store i32 42, i32* @a, align 4 |
| 21 | ret i32 0 |
| 22 | } |
| Roman Divacky | 1bab705 | 2013-12-11 22:25:39 +0000 | [diff] [blame] | 23 | |
| 24 | ; Test correct assembly code generation for thread-local storage |
| 25 | ; using the initial-exec model. |
| 26 | |
| 27 | @a2 = external thread_local global i32 |
| 28 | |
| 29 | define signext i32 @main2() nounwind { |
| 30 | entry: |
| 31 | %retval = alloca i32, align 4 |
| 32 | store i32 0, i32* %retval |
| 33 | %0 = load i32* @a2, align 4 |
| 34 | ret i32 %0 |
| 35 | } |
| 36 | |
| 37 | ; OPT1-LABEL: main2: |
| 38 | ; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha |
| 39 | ; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]]) |
| 40 | ; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls |
| 41 | |
| Roman Divacky | 32143e2 | 2013-12-20 18:08:54 +0000 | [diff] [blame] | 42 | ;OPT0-PPC32-LABEL: main2: |
| 43 | ;OPT0-PPC32: li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_@l |
| 44 | ;OPT0-PPC32: addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_@ha |
| 45 | ;OPT0-PPC32: lwz [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]]) |
| 46 | ;OPT0-PPC32: add 3, [[REG2]], a2@tls |