Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 1 | //===--------------------- SIFrameLowering.h --------------------*- C++ -*-===// |
| 2 | // |
Chandler Carruth | 2946cd7 | 2019-01-19 08:50:56 +0000 | [diff] [blame] | 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | |
| 9 | #ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H |
| 10 | #define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H |
| 11 | |
| 12 | #include "AMDGPUFrameLowering.h" |
| 13 | |
| 14 | namespace llvm { |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 15 | |
Matt Arsenault | 57bc432 | 2016-08-31 21:52:21 +0000 | [diff] [blame] | 16 | class SIInstrInfo; |
| 17 | class SIMachineFunctionInfo; |
| 18 | class SIRegisterInfo; |
Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame] | 19 | class GCNSubtarget; |
Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 20 | |
| 21 | class SIFrameLowering final : public AMDGPUFrameLowering { |
| 22 | public: |
| 23 | SIFrameLowering(StackDirection D, unsigned StackAl, int LAO, |
| 24 | unsigned TransAl = 1) : |
| 25 | AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {} |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 26 | ~SIFrameLowering() override = default; |
Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 27 | |
Matt Arsenault | 2b1f9aa | 2017-05-17 21:56:25 +0000 | [diff] [blame] | 28 | void emitEntryFunctionPrologue(MachineFunction &MF, |
| 29 | MachineBasicBlock &MBB) const; |
Matt Arsenault | 0e3d389 | 2015-11-30 21:15:53 +0000 | [diff] [blame] | 30 | void emitPrologue(MachineFunction &MF, |
| 31 | MachineBasicBlock &MBB) const override; |
Matt Arsenault | 43e92fe | 2016-06-24 06:30:11 +0000 | [diff] [blame] | 32 | void emitEpilogue(MachineFunction &MF, |
| 33 | MachineBasicBlock &MBB) const override; |
Konstantin Zhuravlyov | ffdb00e | 2017-03-10 19:39:07 +0000 | [diff] [blame] | 34 | int getFrameIndexReference(const MachineFunction &MF, int FI, |
| 35 | unsigned &FrameReg) const override; |
Matt Arsenault | 0e3d389 | 2015-11-30 21:15:53 +0000 | [diff] [blame] | 36 | |
Matt Arsenault | ecb43ef | 2017-09-13 23:47:01 +0000 | [diff] [blame] | 37 | void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, |
| 38 | RegScavenger *RS = nullptr) const override; |
| 39 | |
Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 40 | void processFunctionBeforeFrameFinalized( |
| 41 | MachineFunction &MF, |
| 42 | RegScavenger *RS = nullptr) const override; |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 43 | |
Matt Arsenault | b62a4eb | 2017-08-01 19:54:18 +0000 | [diff] [blame] | 44 | MachineBasicBlock::iterator |
| 45 | eliminateCallFramePseudoInstr(MachineFunction &MF, |
| 46 | MachineBasicBlock &MBB, |
| 47 | MachineBasicBlock::iterator MI) const override; |
| 48 | |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 49 | private: |
Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame] | 50 | void emitFlatScratchInit(const GCNSubtarget &ST, |
Matt Arsenault | 57bc432 | 2016-08-31 21:52:21 +0000 | [diff] [blame] | 51 | MachineFunction &MF, |
| 52 | MachineBasicBlock &MBB) const; |
| 53 | |
| 54 | unsigned getReservedPrivateSegmentBufferReg( |
Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame] | 55 | const GCNSubtarget &ST, |
Matt Arsenault | 57bc432 | 2016-08-31 21:52:21 +0000 | [diff] [blame] | 56 | const SIInstrInfo *TII, |
| 57 | const SIRegisterInfo *TRI, |
| 58 | SIMachineFunctionInfo *MFI, |
| 59 | MachineFunction &MF) const; |
| 60 | |
Matt Arsenault | 36c3122 | 2017-04-25 23:40:57 +0000 | [diff] [blame] | 61 | std::pair<unsigned, unsigned> getReservedPrivateSegmentWaveByteOffsetReg( |
Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame] | 62 | const GCNSubtarget &ST, |
Matt Arsenault | 57bc432 | 2016-08-31 21:52:21 +0000 | [diff] [blame] | 63 | const SIInstrInfo *TII, |
| 64 | const SIRegisterInfo *TRI, |
| 65 | SIMachineFunctionInfo *MFI, |
| 66 | MachineFunction &MF) const; |
| 67 | |
Adrian Prantl | 5f8f34e4 | 2018-05-01 15:54:18 +0000 | [diff] [blame] | 68 | /// Emits debugger prologue. |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 69 | void emitDebuggerPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const; |
Matt Arsenault | f28683c | 2017-06-26 17:53:59 +0000 | [diff] [blame] | 70 | |
Tim Renouf | 1322915 | 2017-09-29 09:49:35 +0000 | [diff] [blame] | 71 | // Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set. |
Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame] | 72 | void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF, |
Tim Renouf | 1322915 | 2017-09-29 09:49:35 +0000 | [diff] [blame] | 73 | MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI, |
| 74 | MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg, |
| 75 | unsigned ScratchRsrcReg) const; |
| 76 | |
Matt Arsenault | f28683c | 2017-06-26 17:53:59 +0000 | [diff] [blame] | 77 | public: |
| 78 | bool hasFP(const MachineFunction &MF) const override; |
| 79 | bool hasSP(const MachineFunction &MF) const; |
Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 80 | }; |
| 81 | |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 82 | } // end namespace llvm |
Matt Arsenault | 0c90e95 | 2015-11-06 18:17:45 +0000 | [diff] [blame] | 83 | |
Eugene Zelenko | 2bc2f33 | 2016-12-09 22:06:55 +0000 | [diff] [blame] | 84 | #endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H |