Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / d97d35e1500d98f4f50938c5ecae98a1301a9a10 / . / llvm / test / CodeGen / Mips / llvm-ir / udiv.ll
blob: 122d1385353b3ec0e91bbe6e48e4af353ed76853 [file] [log] [blame]
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]1; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]2; RUN: -check-prefixes=ALL,NOT-R6,GP32
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]3; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]4; RUN: -check-prefixes=ALL,NOT-R6,GP32
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]5; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]6; RUN: -check-prefixes=ALL,NOT-R6,GP32
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]7; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]8; RUN: -check-prefixes=ALL,NOT-R6,GP32
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]9; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]10; RUN: -check-prefixes=ALL,NOT-R6,GP32
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]11; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]12; RUN: -check-prefixes=ALL,R6,GP32
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame]13
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]14; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]15; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]16; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]17; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]18; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]19; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]20; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]21; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]22; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]23; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]24; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]25; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6
Petar Jovanovice578e972016-04-11 15:24:23 +0000[diff] [blame]26; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]27; RUN: -check-prefixes=ALL,R6,64R6
Vasileios Kalintirisd10ce392016-04-14 09:13:13 +0000[diff] [blame]28
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]29; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]30; RUN: -check-prefixes=ALL,MMR3,MM32
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]31; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]32; RUN: -check-prefixes=ALL,MMR6,MM32
Daniel Sandersde393322016-06-23 12:42:53 +0000[diff] [blame]33; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
Daniel Sanders0d972702016-06-24 12:23:17 +0000[diff] [blame]34; RUN: -check-prefixes=ALL,MMR6,MM64
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]35
36define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
37entry:
38; ALL-LABEL: udiv_i1:
39
40 ; NOT-R6: divu $zero, $4, $5
41 ; NOT-R6: teq $5, $zero, 7
42 ; NOT-R6: mflo $2
43
44 ; R6: divu $2, $4, $5
45 ; R6: teq $5, $zero, 7
46
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]47 ; MMR3: divu $zero, $4, $5
48 ; MMR3: teq $5, $zero, 7
49 ; MMR3: mflo $2
50
51 ; MMR6: divu $2, $4, $5
52 ; MMR6: teq $5, $zero, 7
53
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]54 %r = udiv i1 %a, %b
55 ret i1 %r
56}
57
58define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
59entry:
60; ALL-LABEL: udiv_i8:
61
62 ; NOT-R6: divu $zero, $4, $5
63 ; NOT-R6: teq $5, $zero, 7
64 ; NOT-R6: mflo $2
65
66 ; R6: divu $2, $4, $5
67 ; R6: teq $5, $zero, 7
68
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]69 ; MMR3: divu $zero, $4, $5
70 ; MMR3: teq $5, $zero, 7
71 ; MMR3: mflo $2
72
73 ; MMR6: divu $2, $4, $5
74 ; MMR6: teq $5, $zero, 7
75
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]76 %r = udiv i8 %a, %b
77 ret i8 %r
78}
79
80define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
81entry:
82; ALL-LABEL: udiv_i16:
83
84 ; NOT-R6: divu $zero, $4, $5
85 ; NOT-R6: teq $5, $zero, 7
86 ; NOT-R6: mflo $2
87
88 ; R6: divu $2, $4, $5
89 ; R6: teq $5, $zero, 7
90
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]91 ; MMR3: divu $zero, $4, $5
92 ; MMR3: teq $5, $zero, 7
93 ; MMR3: mflo $2
94
95 ; MMR6: divu $2, $4, $5
96 ; MMR6: teq $5, $zero, 7
97
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]98 %r = udiv i16 %a, %b
99 ret i16 %r
100}
101
102define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
103entry:
104; ALL-LABEL: udiv_i32:
105
106 ; NOT-R6: divu $zero, $4, $5
107 ; NOT-R6: teq $5, $zero, 7
108 ; NOT-R6: mflo $2
109
110 ; R6: divu $2, $4, $5
111 ; R6: teq $5, $zero, 7
112
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]113 ; MMR3: divu $zero, $4, $5
114 ; MMR3: teq $5, $zero, 7
115 ; MMR3: mflo $2
116
117 ; MMR6: divu $2, $4, $5
118 ; MMR6: teq $5, $zero, 7
119
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]120 %r = udiv i32 %a, %b
121 ret i32 %r
122}
123
124define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
125entry:
126; ALL-LABEL: udiv_i64:
127
128 ; GP32: lw $25, %call16(__udivdi3)($gp)
129
130 ; GP64-NOT-R6: ddivu $zero, $4, $5
131 ; GP64-NOT-R6: teq $5, $zero, 7
132 ; GP64-NOT-R6: mflo $2
133
134 ; 64R6: ddivu $2, $4, $5
135 ; 64R6: teq $5, $zero, 7
136
Simon Dardis7c96ba12017-06-07 11:21:37 +0000[diff] [blame]137 ; MM32: lw $25, %call16(__udivdi3)($2)
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]138
139 ; MM64: ddivu $2, $4, $5
140 ; MM64: teq $5, $zero, 7
141
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]142 %r = udiv i64 %a, %b
143 ret i64 %r
144}
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]145
146define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
147entry:
148; ALL-LABEL: udiv_i128:
149
Simon Dardis7c96ba12017-06-07 11:21:37 +0000[diff] [blame]150 ; GP32: lw $25, %call16(__udivti3)($gp)
151
152 ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
153 ; 64-R6: ld $25, %call16(__udivti3)($gp)
154
Aleksandar Beserminji29341b82017-09-29 11:05:02 +0000[diff] [blame]155 ; MM32: lw $25, %call16(__udivti3)
Simon Dardis7c96ba12017-06-07 11:21:37 +0000[diff] [blame]156
157 ; MM64: ld $25, %call16(__udivti3)($2)
Zlatko Buljan58d6a952016-04-13 08:02:26 +0000[diff] [blame]158
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]159 %r = udiv i128 %a, %b
160 ret i128 %r
161}