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gerrit-public.fairphone.software / toolchain / llvm-project / db2860f49e32bffd2c9159f0b7f6bd22050d4804 / . / llvm / test / CodeGen / AArch64 / directcond.ll
blob: b0c9f940b50a262415fe7330815e92d38d122e73 [file] [log] [blame]
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
Tim Northoverdb2860f42014-04-14 13:18:48 +0000[diff] [blame^]2; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]3; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]4
5define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]6; CHECK-LABEL: test_select_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]7 %val = select i1 %bit, i32 %a, i32 %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]8; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
9; CHECK-AARCH64: tst w0, [[ONE]]
10; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]11; CHECK-NEXT: csel w0, w1, w2, ne
12
13 ret i32 %val
14}
15
16define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]17; CHECK-LABEL: test_select_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]18 %val = select i1 %bit, i64 %a, i64 %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]19; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
20; CHECK-AARCH64: tst w0, [[ONE]]
21; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]22; CHECK-NEXT: csel x0, x1, x2, ne
23
24 ret i64 %val
25}
26
27define float @test_select_float(i1 %bit, float %a, float %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]28; CHECK-LABEL: test_select_float:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]29 %val = select i1 %bit, float %a, float %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]30; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
31; CHECK-AARCH64: tst w0, [[ONE]]
32; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]33; CHECK-NEXT: fcsel s0, s0, s1, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]34; CHECK-NOFP-NOT: fcsel
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]35 ret float %val
36}
37
38define double @test_select_double(i1 %bit, double %a, double %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]39; CHECK-LABEL: test_select_double:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]40 %val = select i1 %bit, double %a, double %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]41; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
42; CHECK-AARCH64: tst w0, [[ONE]]
43; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]44; CHECK-NEXT: fcsel d0, d0, d1, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]45; CHECK-NOFP-NOT: fcsel
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]46
47 ret double %val
48}
49
50define i32 @test_brcond(i1 %bit) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]51; CHECK-LABEL: test_brcond:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]52 br i1 %bit, label %true, label %false
Tim Northoverdb2860f42014-04-14 13:18:48 +0000[diff] [blame^]53; CHECK: tbz {{w[0-9]+}}, #0, {{.?LBB}}
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]54
55true:
56 ret i32 0
57false:
58 ret i32 42
59}
60
61define i1 @test_setcc_float(float %lhs, float %rhs) {
62; CHECK: test_setcc_float
63 %val = fcmp oeq float %lhs, %rhs
64; CHECK: fcmp s0, s1
65; CHECK: csinc w0, wzr, wzr, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]66; CHECK-NOFP-NOT: fcmp
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]67 ret i1 %val
68}
69
70define i1 @test_setcc_double(double %lhs, double %rhs) {
71; CHECK: test_setcc_double
72 %val = fcmp oeq double %lhs, %rhs
73; CHECK: fcmp d0, d1
74; CHECK: csinc w0, wzr, wzr, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]75; CHECK-NOFP-NOT: fcmp
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]76 ret i1 %val
77}
78
79define i1 @test_setcc_i32(i32 %lhs, i32 %rhs) {
80; CHECK: test_setcc_i32
81 %val = icmp ugt i32 %lhs, %rhs
82; CHECK: cmp w0, w1
83; CHECK: csinc w0, wzr, wzr, ls
84 ret i1 %val
85}
86
87define i1 @test_setcc_i64(i64 %lhs, i64 %rhs) {
88; CHECK: test_setcc_i64
89 %val = icmp ne i64 %lhs, %rhs
90; CHECK: cmp x0, x1
91; CHECK: csinc w0, wzr, wzr, eq
92 ret i1 %val
93}