| Nemanja Ivanovic | e22ebea | 2017-09-26 20:42:47 +0000 | [diff] [blame] | 1 | ; XFAIL: * |
| Nemanja Ivanovic | d6f93f5 | 2017-09-22 11:50:25 +0000 | [diff] [blame] | 2 | ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ |
| 3 | ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ |
| 4 | ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl |
| 5 | ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ |
| 6 | ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ |
| 7 | ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl |
| 8 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 9 | @glob = common local_unnamed_addr global i32 0, align 4 |
| 10 | |
| 11 | define i64 @test_llgesi(i32 signext %a, i32 signext %b) { |
| 12 | ; CHECK-LABEL: test_llgesi: |
| 13 | ; CHECK: # BB#0: # %entry |
| 14 | ; CHECK-NEXT: sub r3, r3, r4 |
| 15 | ; CHECK-NEXT: rldicl r3, r3, 1, 63 |
| 16 | ; CHECK-NEXT: xori r3, r3, 1 |
| 17 | ; CHECK-NEXT: blr |
| 18 | entry: |
| 19 | %cmp = icmp sge i32 %a, %b |
| 20 | %conv1 = zext i1 %cmp to i64 |
| 21 | ret i64 %conv1 |
| 22 | } |
| 23 | |
| 24 | define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) { |
| 25 | ; CHECK-LABEL: test_llgesi_sext: |
| 26 | ; CHECK: # BB#0: # %entry |
| 27 | ; CHECK-NEXT: sub r3, r3, r4 |
| 28 | ; CHECK-NEXT: rldicl r3, r3, 1, 63 |
| 29 | ; CHECK-NEXT: addi r3, r3, -1 |
| 30 | ; CHECK-NEXT: blr |
| 31 | entry: |
| 32 | %cmp = icmp sge i32 %a, %b |
| 33 | %conv1 = sext i1 %cmp to i64 |
| 34 | ret i64 %conv1 |
| 35 | } |
| 36 | |
| 37 | define void @test_llgesi_store(i32 signext %a, i32 signext %b) { |
| 38 | ; CHECK-LABEL: test_llgesi_store: |
| 39 | ; CHECK: # BB#0: # %entry |
| 40 | ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha |
| 41 | ; CHECK-NEXT: sub r3, r3, r4 |
| 42 | ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) |
| 43 | ; CHECK-NEXT: rldicl r3, r3, 1, 63 |
| 44 | ; CHECK-NEXT: xori r3, r3, 1 |
| 45 | ; CHECK-NEXT: stw r3, 0(r12) |
| 46 | ; CHECK-NEXT: blr |
| 47 | entry: |
| 48 | %cmp = icmp sge i32 %a, %b |
| 49 | %conv = zext i1 %cmp to i32 |
| 50 | store i32 %conv, i32* @glob, align 4 |
| 51 | ret void |
| 52 | } |
| 53 | |
| 54 | define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { |
| 55 | ; CHECK-LABEL: test_llgesi_sext_store: |
| 56 | ; CHECK: # BB#0: # %entry |
| 57 | ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha |
| 58 | ; CHECK-NEXT: sub r3, r3, r4 |
| 59 | ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) |
| 60 | ; CHECK-NEXT: rldicl r3, r3, 1, 63 |
| 61 | ; CHECK-NEXT: addi r3, r3, -1 |
| 62 | ; CHECK-NEXT: stw r3, 0(r12) |
| 63 | ; CHECK-NEXT: blr |
| 64 | entry: |
| 65 | %cmp = icmp sge i32 %a, %b |
| 66 | %sub = sext i1 %cmp to i32 |
| 67 | store i32 %sub, i32* @glob, align 4 |
| 68 | ret void |
| 69 | } |