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gerrit-public.fairphone.software / toolchain / llvm-project / dc31c61b18f01b21e18ccea4de0a010569e81887 / . / llvm / test / CodeGen / RISCV / calls.ll
blob: 4299d46f55e043e0ba6dc722a79178aad2a78902 [file] [log] [blame]
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck -check-prefix=RV32I %s
4
5declare i32 @external_function(i32)
6
7define i32 @test_call_external(i32 %a) nounwind {
8; RV32I-LABEL: test_call_external:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]10; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]11; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]12; RV32I-NEXT: sw s0, 8(sp)
13; RV32I-NEXT: addi s0, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]14; RV32I-NEXT: lui a1, %hi(external_function)
15; RV32I-NEXT: addi a1, a1, %lo(external_function)
16; RV32I-NEXT: jalr ra, a1, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]17; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]18; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]19; RV32I-NEXT: addi sp, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]20; RV32I-NEXT: jalr zero, ra, 0
21 %1 = call i32 @external_function(i32 %a)
22 ret i32 %1
23}
24
25define i32 @defined_function(i32 %a) nounwind {
26; RV32I-LABEL: defined_function:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]27; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]28; RV32I-NEXT: addi sp, sp, -16
29; RV32I-NEXT: sw ra, 12(sp)
30; RV32I-NEXT: sw s0, 8(sp)
31; RV32I-NEXT: addi s0, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]32; RV32I-NEXT: addi a0, a0, 1
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]33; RV32I-NEXT: lw s0, 8(sp)
34; RV32I-NEXT: lw ra, 12(sp)
35; RV32I-NEXT: addi sp, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]36; RV32I-NEXT: jalr zero, ra, 0
37 %1 = add i32 %a, 1
38 ret i32 %1
39}
40
41define i32 @test_call_defined(i32 %a) nounwind {
42; RV32I-LABEL: test_call_defined:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]43; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]44; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]45; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]46; RV32I-NEXT: sw s0, 8(sp)
47; RV32I-NEXT: addi s0, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]48; RV32I-NEXT: lui a1, %hi(defined_function)
49; RV32I-NEXT: addi a1, a1, %lo(defined_function)
50; RV32I-NEXT: jalr ra, a1, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]51; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]52; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]53; RV32I-NEXT: addi sp, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]54; RV32I-NEXT: jalr zero, ra, 0
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame^]55 %1 = call i32 @defined_function(i32 %a)
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]56 ret i32 %1
57}
58
59define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
60; RV32I-LABEL: test_call_indirect:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]61; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]62; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]63; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]64; RV32I-NEXT: sw s0, 8(sp)
65; RV32I-NEXT: addi s0, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]66; RV32I-NEXT: addi a2, a0, 0
67; RV32I-NEXT: addi a0, a1, 0
68; RV32I-NEXT: jalr ra, a2, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]69; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]70; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]71; RV32I-NEXT: addi sp, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]72; RV32I-NEXT: jalr zero, ra, 0
73 %1 = call i32 %a(i32 %b)
74 ret i32 %1
75}
76
77; Ensure that calls to fastcc functions aren't rejected. Such calls may be
78; introduced when compiling with optimisation.
79
80define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
81; RV32I-LABEL: fastcc_function:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]82; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]83; RV32I-NEXT: addi sp, sp, -16
84; RV32I-NEXT: sw ra, 12(sp)
85; RV32I-NEXT: sw s0, 8(sp)
86; RV32I-NEXT: addi s0, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]87; RV32I-NEXT: add a0, a0, a1
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]88; RV32I-NEXT: lw s0, 8(sp)
89; RV32I-NEXT: lw ra, 12(sp)
90; RV32I-NEXT: addi sp, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]91; RV32I-NEXT: jalr zero, ra, 0
92 %1 = add i32 %a, %b
93 ret i32 %1
94}
95
96define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
97; RV32I-LABEL: test_call_fastcc:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]98; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]99; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]100; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]101; RV32I-NEXT: sw s0, 8(sp)
102; RV32I-NEXT: sw s1, 4(sp)
103; RV32I-NEXT: addi s0, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]104; RV32I-NEXT: addi s1, a0, 0
105; RV32I-NEXT: lui a0, %hi(fastcc_function)
106; RV32I-NEXT: addi a2, a0, %lo(fastcc_function)
107; RV32I-NEXT: addi a0, s1, 0
108; RV32I-NEXT: jalr ra, a2, 0
109; RV32I-NEXT: addi a0, s1, 0
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]110; RV32I-NEXT: lw s1, 4(sp)
111; RV32I-NEXT: lw s0, 8(sp)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]112; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]113; RV32I-NEXT: addi sp, sp, 16
Alex Bradburya3376752017-11-08 13:41:21 +0000[diff] [blame]114; RV32I-NEXT: jalr zero, ra, 0
115 %1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b)
116 ret i32 %a
117}
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame^]118
119declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
120
121define i32 @test_call_external_many_args(i32 %a) nounwind {
122; RV32I-LABEL: test_call_external_many_args:
123; RV32I: # %bb.0:
124; RV32I-NEXT: addi sp, sp, -32
125; RV32I-NEXT: sw ra, 28(sp)
126; RV32I-NEXT: sw s0, 24(sp)
127; RV32I-NEXT: sw s1, 20(sp)
128; RV32I-NEXT: addi s0, sp, 32
129; RV32I-NEXT: addi s1, a0, 0
130; RV32I-NEXT: sw s1, 4(sp)
131; RV32I-NEXT: sw s1, 0(sp)
132; RV32I-NEXT: lui a0, %hi(external_many_args)
133; RV32I-NEXT: addi t0, a0, %lo(external_many_args)
134; RV32I-NEXT: addi a0, s1, 0
135; RV32I-NEXT: addi a1, s1, 0
136; RV32I-NEXT: addi a2, s1, 0
137; RV32I-NEXT: addi a3, s1, 0
138; RV32I-NEXT: addi a4, s1, 0
139; RV32I-NEXT: addi a5, s1, 0
140; RV32I-NEXT: addi a6, s1, 0
141; RV32I-NEXT: addi a7, s1, 0
142; RV32I-NEXT: jalr ra, t0, 0
143; RV32I-NEXT: addi a0, s1, 0
144; RV32I-NEXT: lw s1, 20(sp)
145; RV32I-NEXT: lw s0, 24(sp)
146; RV32I-NEXT: lw ra, 28(sp)
147; RV32I-NEXT: addi sp, sp, 32
148; RV32I-NEXT: jalr zero, ra, 0
149 %1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
150 i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
151 ret i32 %a
152}
153
154define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %j) nounwind {
155; RV32I-LABEL: defined_many_args:
156; RV32I: # %bb.0:
157; RV32I-NEXT: addi sp, sp, -16
158; RV32I-NEXT: sw ra, 12(sp)
159; RV32I-NEXT: sw s0, 8(sp)
160; RV32I-NEXT: addi s0, sp, 16
161; RV32I-NEXT: lw a0, 4(s0)
162; RV32I-NEXT: addi a0, a0, 1
163; RV32I-NEXT: lw s0, 8(sp)
164; RV32I-NEXT: lw ra, 12(sp)
165; RV32I-NEXT: addi sp, sp, 16
166; RV32I-NEXT: jalr zero, ra, 0
167 %added = add i32 %j, 1
168 ret i32 %added
169}
170
171define i32 @test_call_defined_many_args(i32 %a) nounwind {
172; RV32I-LABEL: test_call_defined_many_args:
173; RV32I: # %bb.0:
174; RV32I-NEXT: addi sp, sp, -32
175; RV32I-NEXT: sw ra, 28(sp)
176; RV32I-NEXT: sw s0, 24(sp)
177; RV32I-NEXT: addi s0, sp, 32
178; RV32I-NEXT: sw a0, 4(sp)
179; RV32I-NEXT: sw a0, 0(sp)
180; RV32I-NEXT: lui a1, %hi(defined_many_args)
181; RV32I-NEXT: addi t0, a1, %lo(defined_many_args)
182; RV32I-NEXT: addi a1, a0, 0
183; RV32I-NEXT: addi a2, a0, 0
184; RV32I-NEXT: addi a3, a0, 0
185; RV32I-NEXT: addi a4, a0, 0
186; RV32I-NEXT: addi a5, a0, 0
187; RV32I-NEXT: addi a6, a0, 0
188; RV32I-NEXT: addi a7, a0, 0
189; RV32I-NEXT: jalr ra, t0, 0
190; RV32I-NEXT: lw s0, 24(sp)
191; RV32I-NEXT: lw ra, 28(sp)
192; RV32I-NEXT: addi sp, sp, 32
193; RV32I-NEXT: jalr zero, ra, 0
194 %1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
195 i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
196 ret i32 %1
197}