blob: 4096ca4ddb0cecc644e8b7b44a7c3bbe0842273a [file] [log] [blame]
Sanjay Patel43f71ea2018-03-15 14:48:39 +00001; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instsimplify -S | FileCheck %s
3
Sanjay Patel5a5c33d2018-03-16 20:55:55 +00004; Default NaN constant
5
6define double @fadd_nan_op0(double %x) {
Sanjay Patel43f71ea2018-03-15 14:48:39 +00007; CHECK-LABEL: @fadd_nan_op0(
Sanjay Patele2359422018-03-21 19:31:53 +00008; CHECK-NEXT: ret double 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +00009;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000010 %r = fadd double 0x7FF8000000000000, %x
11 ret double %r
Sanjay Patel43f71ea2018-03-15 14:48:39 +000012}
13
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000014; Sign bit is set
15
16define double @fadd_nan_op1(double %x) {
Sanjay Patel43f71ea2018-03-15 14:48:39 +000017; CHECK-LABEL: @fadd_nan_op1(
Sanjay Patele2359422018-03-21 19:31:53 +000018; CHECK-NEXT: ret double 0xFFF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +000019;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000020 %r = fadd double %x, 0xFFF8000000000000
21 ret double %r
Sanjay Patel43f71ea2018-03-15 14:48:39 +000022}
23
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000024; Non-zero payload
25
Sanjay Patel43f71ea2018-03-15 14:48:39 +000026define float @fsub_nan_op0(float %x) {
27; CHECK-LABEL: @fsub_nan_op0(
Sanjay Patele2359422018-03-21 19:31:53 +000028; CHECK-NEXT: ret float 0x7FFFFF0000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +000029;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000030 %r = fsub float 0x7FFFFF0000000000, %x
Sanjay Patel43f71ea2018-03-15 14:48:39 +000031 ret float %r
32}
33
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000034; Signaling
35
Sanjay Patel43f71ea2018-03-15 14:48:39 +000036define float @fsub_nan_op1(float %x) {
37; CHECK-LABEL: @fsub_nan_op1(
Sanjay Patele2359422018-03-21 19:31:53 +000038; CHECK-NEXT: ret float 0x7FF1000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +000039;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000040 %r = fsub float %x, 0x7FF1000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +000041 ret float %r
42}
43
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000044; Signaling and signed
45
46define double @fmul_nan_op0(double %x) {
Sanjay Patel43f71ea2018-03-15 14:48:39 +000047; CHECK-LABEL: @fmul_nan_op0(
Sanjay Patele2359422018-03-21 19:31:53 +000048; CHECK-NEXT: ret double 0xFFF0000000000001
Sanjay Patel43f71ea2018-03-15 14:48:39 +000049;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000050 %r = fmul double 0xFFF0000000000001, %x
51 ret double %r
Sanjay Patel43f71ea2018-03-15 14:48:39 +000052}
53
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000054; Vector type
55
56define <2 x float> @fmul_nan_op1(<2 x float> %x) {
Sanjay Patel43f71ea2018-03-15 14:48:39 +000057; CHECK-LABEL: @fmul_nan_op1(
Sanjay Patele2359422018-03-21 19:31:53 +000058; CHECK-NEXT: ret <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>
Sanjay Patel43f71ea2018-03-15 14:48:39 +000059;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000060 %r = fmul <2 x float> %x, <float 0x7FF8000000000000, float 0x7FF8000000000000>
61 ret <2 x float> %r
Sanjay Patel43f71ea2018-03-15 14:48:39 +000062}
63
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000064; Vector signed and non-zero payload
65
66define <2 x double> @fdiv_nan_op0(<2 x double> %x) {
Sanjay Patel43f71ea2018-03-15 14:48:39 +000067; CHECK-LABEL: @fdiv_nan_op0(
Sanjay Patele2359422018-03-21 19:31:53 +000068; CHECK-NEXT: ret <2 x double> <double 0xFFF800000000000F, double 0xFFF800000000000F>
Sanjay Patel43f71ea2018-03-15 14:48:39 +000069;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000070 %r = fdiv <2 x double> <double 0xFFF800000000000F, double 0xFFF800000000000F>, %x
71 ret <2 x double> %r
Sanjay Patel43f71ea2018-03-15 14:48:39 +000072}
73
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000074; Vector with different NaN constant elements
75
76define <2 x half> @fdiv_nan_op1(<2 x half> %x) {
Sanjay Patel43f71ea2018-03-15 14:48:39 +000077; CHECK-LABEL: @fdiv_nan_op1(
Sanjay Patele2359422018-03-21 19:31:53 +000078; CHECK-NEXT: ret <2 x half> <half 0xH7FFF, half 0xHFF00>
Sanjay Patel43f71ea2018-03-15 14:48:39 +000079;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000080 %r = fdiv <2 x half> %x, <half 0xH7FFF, half 0xHFF00>
81 ret <2 x half> %r
Sanjay Patel43f71ea2018-03-15 14:48:39 +000082}
83
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000084; Vector with undef element
85
86define <2 x double> @frem_nan_op0(<2 x double> %x) {
Sanjay Patel43f71ea2018-03-15 14:48:39 +000087; CHECK-LABEL: @frem_nan_op0(
Sanjay Patele2359422018-03-21 19:31:53 +000088; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>
Sanjay Patel43f71ea2018-03-15 14:48:39 +000089;
Sanjay Patel5a5c33d2018-03-16 20:55:55 +000090 %r = frem <2 x double> <double 0xFFFF000000000000, double undef>, %x
91 ret <2 x double> %r
Sanjay Patel43f71ea2018-03-15 14:48:39 +000092}
93
94define float @frem_nan_op1(float %x) {
95; CHECK-LABEL: @frem_nan_op1(
Sanjay Patele2359422018-03-21 19:31:53 +000096; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +000097;
98 %r = frem float %x, 0x7FF8000000000000
99 ret float %r
100}
101
Sanjay Patel5a5c33d2018-03-16 20:55:55 +0000102; Special-case: fneg must only change the sign bit (this is handled by constant folding).
103
104define double @fneg_nan_1(double %x) {
105; CHECK-LABEL: @fneg_nan_1(
106; CHECK-NEXT: ret double 0xFFFABCDEF0123456
107;
108 %r = fsub double -0.0, 0x7FFABCDEF0123456
109 ret double %r
110}
111
112define <2 x double> @fneg_nan_2(<2 x double> %x) {
113; CHECK-LABEL: @fneg_nan_2(
114; CHECK-NEXT: ret <2 x double> <double 0x7FF1234567890ABC, double 0xFFF0000000000001>
115;
116 %r = fsub <2 x double> <double -0.0, double -0.0>, <double 0xFFF1234567890ABC, double 0x7FF0000000000001>
117 ret <2 x double> %r
118}
119
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000120; Repeat all tests with fast-math-flags. Alternate 'nnan' and 'fast' for more coverage.
121
122define float @fadd_nan_op0_nnan(float %x) {
123; CHECK-LABEL: @fadd_nan_op0_nnan(
Sanjay Patele2359422018-03-21 19:31:53 +0000124; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000125;
126 %r = fadd nnan float 0x7FF8000000000000, %x
127 ret float %r
128}
129
130define float @fadd_nan_op1_fast(float %x) {
131; CHECK-LABEL: @fadd_nan_op1_fast(
Sanjay Patele2359422018-03-21 19:31:53 +0000132; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000133;
134 %r = fadd fast float %x, 0x7FF8000000000000
135 ret float %r
136}
137
138define float @fsub_nan_op0_fast(float %x) {
139; CHECK-LABEL: @fsub_nan_op0_fast(
Sanjay Patele2359422018-03-21 19:31:53 +0000140; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000141;
142 %r = fsub fast float 0x7FF8000000000000, %x
143 ret float %r
144}
145
146define float @fsub_nan_op1_nnan(float %x) {
147; CHECK-LABEL: @fsub_nan_op1_nnan(
Sanjay Patele2359422018-03-21 19:31:53 +0000148; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000149;
150 %r = fsub nnan float %x, 0x7FF8000000000000
151 ret float %r
152}
153
154define float @fmul_nan_op0_nnan(float %x) {
155; CHECK-LABEL: @fmul_nan_op0_nnan(
Sanjay Patele2359422018-03-21 19:31:53 +0000156; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000157;
158 %r = fmul nnan float 0x7FF8000000000000, %x
159 ret float %r
160}
161
162define float @fmul_nan_op1_fast(float %x) {
163; CHECK-LABEL: @fmul_nan_op1_fast(
Sanjay Patele2359422018-03-21 19:31:53 +0000164; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000165;
166 %r = fmul fast float %x, 0x7FF8000000000000
167 ret float %r
168}
169
170define float @fdiv_nan_op0_fast(float %x) {
171; CHECK-LABEL: @fdiv_nan_op0_fast(
Sanjay Patele2359422018-03-21 19:31:53 +0000172; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000173;
174 %r = fdiv fast float 0x7FF8000000000000, %x
175 ret float %r
176}
177
178define float @fdiv_nan_op1_nnan(float %x) {
179; CHECK-LABEL: @fdiv_nan_op1_nnan(
Sanjay Patele2359422018-03-21 19:31:53 +0000180; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000181;
182 %r = fdiv nnan float %x, 0x7FF8000000000000
183 ret float %r
184}
185
186define float @frem_nan_op0_nnan(float %x) {
187; CHECK-LABEL: @frem_nan_op0_nnan(
Sanjay Patele2359422018-03-21 19:31:53 +0000188; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000189;
190 %r = frem nnan float 0x7FF8000000000000, %x
191 ret float %r
192}
193
194define float @frem_nan_op1_fast(float %x) {
195; CHECK-LABEL: @frem_nan_op1_fast(
Sanjay Patele2359422018-03-21 19:31:53 +0000196; CHECK-NEXT: ret float 0x7FF8000000000000
Sanjay Patel43f71ea2018-03-15 14:48:39 +0000197;
198 %r = frem fast float %x, 0x7FF8000000000000
199 ret float %r
200}
201