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gerrit-public.fairphone.software / toolchain / llvm-project / 551862d66b1bd24c3f4f8cff043dc9d5802f9d2d / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 8cf5bb437177a88ba026f60347b55d3c2bcd1baa [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
394multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
404}
405
406defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
408 VEX_W;
409
410def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
412
413def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
415
416def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
420
421multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
422 X86MemOperand x86memop, PatFrag ld_frag,
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
424 RegisterClass KRC> {
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
427 [(set DstRC:$dst,
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
430 VR128X:$src),
431 !strconcat(OpcodeStr,
432 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
433 [(set DstRC:$dst,
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
435 EVEX, EVEX_KZ;
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
438 [(set DstRC:$dst,
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
441 x86memop:$src),
442 !strconcat(OpcodeStr,
443 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
446}
447
448defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
451defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
453 EVEX_CD8<64, CD8VT1>;
454
455def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
456 (VBROADCASTSSZrr VR128X:$src)>;
457def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
458 (VBROADCASTSDZrr VR128X:$src)>;
459
460// Provide fallback in case the load node that is used in the patterns above
461// is used by additional users, which prevents the pattern selection.
462def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
464def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
466
467
468let Predicates = [HasAVX512] in {
469def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
470 (EXTRACT_SUBREG
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
472 addr:$src)), sub_ymm)>;
473}
474//===----------------------------------------------------------------------===//
475// AVX-512 BROADCAST MASK TO VECTOR REGISTER
476//---
477
478multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
479 RegisterClass DstRC, RegisterClass KRC,
480 ValueType OpVT, ValueType SrcVT> {
481def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
483 []>, EVEX;
484}
485
486defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
487 VK16, v16i32, v16i1>, EVEX_V512;
488defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
490
491//===----------------------------------------------------------------------===//
492// AVX-512 - VPERM
493//
494// -- immediate form --
495multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
496 SDNode OpNode, PatFrag mem_frag,
497 X86MemOperand x86memop, ValueType OpVT> {
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
499 (ins RC:$src1, i8imm:$src2),
500 !strconcat(OpcodeStr,
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
502 [(set RC:$dst,
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
504 EVEX;
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
506 (ins x86memop:$src1, i8imm:$src2),
507 !strconcat(OpcodeStr,
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
509 [(set RC:$dst,
510 (OpVT (OpNode (mem_frag addr:$src1),
511 (i8 imm:$src2))))]>, EVEX;
512}
513
514defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
516let ExeDomain = SSEPackedDouble in
517defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
519
520// -- VPERM - register form --
521multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
523
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, RC:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
528 [(set RC:$dst,
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
530
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
532 (ins RC:$src1, x86memop:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
535 [(set RC:$dst,
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
537 EVEX_4V;
538}
539
540defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
542defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
544let ExeDomain = SSEPackedSingle in
545defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
547let ExeDomain = SSEPackedDouble in
548defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550
551// -- VPERM2I - 3 source operands form --
552multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
553 PatFrag mem_frag, X86MemOperand x86memop,
554 ValueType OpVT> {
555let Constraints = "$src1 = $dst" in {
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, RC:$src2, RC:$src3),
558 !strconcat(OpcodeStr,
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
560 [(set RC:$dst,
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
562 EVEX_4V;
563
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
566 !strconcat(OpcodeStr,
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
568 [(set RC:$dst,
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
570 (mem_frag addr:$src3))))]>, EVEX_4V;
571 }
572}
573defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
581
582//===----------------------------------------------------------------------===//
583// AVX-512 - BLEND using mask
584//
585multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
586 RegisterClass KRC, RegisterClass RC,
587 X86MemOperand x86memop, PatFrag mem_frag,
588 SDNode OpNode, ValueType vt> {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins KRC:$mask, RC:$src1, RC:$src2),
591 !strconcat(OpcodeStr,
592 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
595
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
598 !strconcat(OpcodeStr,
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
600 []>,
601 EVEX_4V, EVEX_K;
602}
603
604let ExeDomain = SSEPackedSingle in
605defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
606 memopv16f32, vselect, v16f32>,
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
608let ExeDomain = SSEPackedDouble in
609defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
610 memopv8f64, vselect, v8f64>,
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
612
613defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
614 memopv8i64, vselect, v16i32>,
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
616
617defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
618 memopv8i64, vselect, v8i64>, VEX_W,
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
620
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]621let Predicates = [HasAVX512] in {
622def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
623 (v8f32 VR256X:$src2))),
624 (EXTRACT_SUBREG
625 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
626 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
628
629def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
630 (v8i32 VR256X:$src2))),
631 (EXTRACT_SUBREG
632 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
633 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
635}
636
637multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
638 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
639 SDNode OpNode, ValueType vt> {
640 def rr : AVX512BI<opc, MRMSrcReg,
641 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
643 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
644 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
645 def rm : AVX512BI<opc, MRMSrcMem,
646 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
648 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
649 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
650}
651
652defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
653 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
654defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
655 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
656
657defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
658 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
659defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
660 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
661
662def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
663 (COPY_TO_REGCLASS (VPCMPGTDZrr
664 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
666
667def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
668 (COPY_TO_REGCLASS (VPCMPEQDZrr
669 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
671
672multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
673 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
674 SDNode OpNode, ValueType vt, Operand CC, string asm,
675 string asm_alt> {
676 def rri : AVX512AIi8<opc, MRMSrcReg,
677 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
678 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
679 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
680 def rmi : AVX512AIi8<opc, MRMSrcMem,
681 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
682 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
683 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
684 // Accept explicit immediate argument form instead of comparison code.
685 let neverHasSideEffects = 1 in {
686 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
687 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
688 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
689 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
690 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
691 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
692 }
693}
694
695defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
696 X86cmpm, v16i32, AVXCC,
697 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
699 EVEX_V512, EVEX_CD8<32, CD8VF>;
700defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
701 X86cmpmu, v16i32, AVXCC,
702 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
703 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
704 EVEX_V512, EVEX_CD8<32, CD8VF>;
705
706defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
707 X86cmpm, v8i64, AVXCC,
708 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
709 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
710 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
711defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
712 X86cmpmu, v8i64, AVXCC,
713 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
714 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
715 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
716
717// avx512_cmp_packed - sse 1 & 2 compare packed instructions
718multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
719 X86MemOperand x86memop, Operand CC,
720 SDNode OpNode, ValueType vt, string asm,
721 string asm_alt, Domain d> {
722 def rri : AVX512PIi8<0xC2, MRMSrcReg,
723 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
724 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
725 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
726 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
727 [(set KRC:$dst,
728 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
729
730 // Accept explicit immediate argument form instead of comparison code.
731 let neverHasSideEffects = 1 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]732 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]733 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]734 asm_alt, [], d>;
735 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]736 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]737 asm_alt, [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]738 }
739}
740
741defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
742 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
743 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]744 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]745defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
746 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
747 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]748 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]749 EVEX_CD8<64, CD8VF>;
750
751def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
752 (COPY_TO_REGCLASS (VCMPPSZrri
753 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
755 imm:$cc), VK8)>;
756def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
757 (COPY_TO_REGCLASS (VPCMPDZrri
758 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
760 imm:$cc), VK8)>;
761def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
762 (COPY_TO_REGCLASS (VPCMPUDZrri
763 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
765 imm:$cc), VK8)>;
766
767// Mask register copy, including
768// - copy between mask registers
769// - load/store mask registers
770// - copy from GPR to mask register and vice versa
771//
772multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
773 string OpcodeStr, RegisterClass KRC,
774 ValueType vt, X86MemOperand x86memop> {
775 let neverHasSideEffects = 1 in {
776 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
777 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
778 let mayLoad = 1 in
779 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
780 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
781 [(set KRC:$dst, (vt (load addr:$src)))]>;
782 let mayStore = 1 in
783 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
785 }
786}
787
788multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
789 string OpcodeStr,
790 RegisterClass KRC, RegisterClass GRC> {
791 let neverHasSideEffects = 1 in {
792 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
793 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
794 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
796 }
797}
798
799let Predicates = [HasAVX512] in {
800 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
801 VEX, TB;
802 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
803 VEX, TB;
804}
805
806let Predicates = [HasAVX512] in {
807 // GR16 from/to 16-bit mask
808 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
809 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
810 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
811 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
812
813 // Store kreg in memory
814 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
815 (KMOVWmk addr:$dst, VK16:$src)>;
816
817 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
818 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
819}
820// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
821let Predicates = [HasAVX512] in {
822 // GR from/to 8-bit mask without native support
823 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
824 (COPY_TO_REGCLASS
825 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
826 VK8)>;
827 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
828 (EXTRACT_SUBREG
829 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
830 sub_8bit)>;
831}
832
833// Mask unary operation
834// - KNOT
835multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
836 RegisterClass KRC, SDPatternOperator OpNode> {
837 let Predicates = [HasAVX512] in
838 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
840 [(set KRC:$dst, (OpNode KRC:$src))]>;
841}
842
843multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
844 SDPatternOperator OpNode> {
845 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
846 VEX, TB;
847}
848
849defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
850
851def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
852def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
853 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
854
855// With AVX-512, 8-bit mask is promoted to 16-bit mask.
856def : Pat<(not VK8:$src),
857 (COPY_TO_REGCLASS
858 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
859
860// Mask binary operation
861// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
862multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
863 RegisterClass KRC, SDPatternOperator OpNode> {
864 let Predicates = [HasAVX512] in
865 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
866 !strconcat(OpcodeStr,
867 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
868 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
869}
870
871multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
872 SDPatternOperator OpNode> {
873 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
874 VEX_4V, VEX_L, TB;
875}
876
877def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
878def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
879
880let isCommutable = 1 in {
881 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
882 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
883 let isCommutable = 0 in
884 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
885 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
886 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
887 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
888}
889
890multiclass avx512_mask_binop_int<string IntName, string InstName> {
891 let Predicates = [HasAVX512] in
892 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
893 VK16:$src1, VK16:$src2),
894 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
895}
896
897defm : avx512_mask_binop_int<"kadd", "KADD">;
898defm : avx512_mask_binop_int<"kand", "KAND">;
899defm : avx512_mask_binop_int<"kandn", "KANDN">;
900defm : avx512_mask_binop_int<"kor", "KOR">;
901defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
902defm : avx512_mask_binop_int<"kxor", "KXOR">;
903// With AVX-512, 8-bit mask is promoted to 16-bit mask.
904multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
905 let Predicates = [HasAVX512] in
906 def : Pat<(OpNode VK8:$src1, VK8:$src2),
907 (COPY_TO_REGCLASS
908 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
909 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
910}
911
912defm : avx512_binop_pat<and, KANDWrr>;
913defm : avx512_binop_pat<andn, KANDNWrr>;
914defm : avx512_binop_pat<or, KORWrr>;
915defm : avx512_binop_pat<xnor, KXNORWrr>;
916defm : avx512_binop_pat<xor, KXORWrr>;
917
918// Mask unpacking
919multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
920 RegisterClass KRC1, RegisterClass KRC2> {
921 let Predicates = [HasAVX512] in
922 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
923 !strconcat(OpcodeStr,
924 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
925}
926
927multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
928 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
929 VEX_4V, VEX_L, OpSize, TB;
930}
931
932defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
933
934multiclass avx512_mask_unpck_int<string IntName, string InstName> {
935 let Predicates = [HasAVX512] in
936 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
937 VK8:$src1, VK8:$src2),
938 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
939}
940
941defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
942// Mask bit testing
943multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
944 SDNode OpNode> {
945 let Predicates = [HasAVX512], Defs = [EFLAGS] in
946 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
947 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
948 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
949}
950
951multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
952 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
953 VEX, TB;
954}
955
956defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
957defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
958
959// Mask shift
960multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
961 SDNode OpNode> {
962 let Predicates = [HasAVX512] in
963 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
964 !strconcat(OpcodeStr,
965 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
966 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
967}
968
969multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
970 SDNode OpNode> {
971 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
972 VEX, OpSize, TA, VEX_W;
973}
974
975defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
976defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
977
978// Mask setting all 0s or 1s
979multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
980 let Predicates = [HasAVX512] in
981 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
982 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
983 [(set KRC:$dst, (VT Val))]>;
984}
985
986multiclass avx512_mask_setop_w<PatFrag Val> {
987 defm B : avx512_mask_setop<VK8, v8i1, Val>;
988 defm W : avx512_mask_setop<VK16, v16i1, Val>;
989}
990
991defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
992defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
993
994// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
995let Predicates = [HasAVX512] in {
996 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
997 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
998}
999def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1000 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1001
1002def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1003 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1004
1005def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1006 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1007
1008//===----------------------------------------------------------------------===//
1009// AVX-512 - Aligned and unaligned load and store
1010//
1011
1012multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1013 X86MemOperand x86memop, PatFrag ld_frag,
1014 string asm, Domain d> {
1015let neverHasSideEffects = 1 in
1016 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1017 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1018 EVEX;
1019let canFoldAsLoad = 1 in
1020 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1021 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1022 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1023let Constraints = "$src1 = $dst" in {
1024 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1025 (ins RC:$src1, KRC:$mask, RC:$src2),
1026 !strconcat(asm,
1027 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1028 EVEX, EVEX_K;
1029 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1031 !strconcat(asm,
1032 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1033 [], d>, EVEX, EVEX_K;
1034}
1035}
1036
1037defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1038 "vmovaps", SSEPackedSingle>,
1039 EVEX_V512, EVEX_CD8<32, CD8VF>;
1040defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1041 "vmovapd", SSEPackedDouble>,
1042 OpSize, EVEX_V512, VEX_W,
1043 EVEX_CD8<64, CD8VF>;
1044defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1045 "vmovups", SSEPackedSingle>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1046 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1047defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1048 "vmovupd", SSEPackedDouble>,
1049 OpSize, EVEX_V512, VEX_W,
1050 EVEX_CD8<64, CD8VF>;
1051def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1052 "vmovaps\t{$src, $dst|$dst, $src}",
1053 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1054 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1055def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1056 "vmovapd\t{$src, $dst|$dst, $src}",
1057 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1058 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1059 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1060def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1061 "vmovups\t{$src, $dst|$dst, $src}",
1062 [(store (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1063 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1064def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1065 "vmovupd\t{$src, $dst|$dst, $src}",
1066 [(store (v8f64 VR512:$src), addr:$dst)],
1067 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1068 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1069
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1070let neverHasSideEffects = 1 in {
1071 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1072 (ins VR512:$src),
1073 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1074 EVEX, EVEX_V512;
1075 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1076 (ins VR512:$src),
1077 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1078 EVEX, EVEX_V512, VEX_W;
1079let mayStore = 1 in {
1080 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1081 (ins i512mem:$dst, VR512:$src),
1082 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1083 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1084 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1085 (ins i512mem:$dst, VR512:$src),
1086 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1087 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1088}
1089let mayLoad = 1 in {
1090def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1091 (ins i512mem:$src),
1092 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1093 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1094def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1095 (ins i512mem:$src),
1096 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1097 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1098}
1099}
1100
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1101// 512-bit aligned load/store
1102def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1103def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1104
1105def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1106 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1107def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1108 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1109
1110multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1111 RegisterClass RC, RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1112 PatFrag ld_frag, X86MemOperand x86memop> {
1113let neverHasSideEffects = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1114 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1115 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1116let canFoldAsLoad = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1117 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1118 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1119 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1120let mayStore = 1 in
1121 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1122 (ins x86memop:$dst, VR512:$src),
1123 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1124let Constraints = "$src1 = $dst" in {
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1125 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1126 (ins RC:$src1, KRC:$mask, RC:$src2),
1127 !strconcat(asm,
1128 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1129 EVEX, EVEX_K;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1130 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1131 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1132 !strconcat(asm,
1133 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1134 []>, EVEX, EVEX_K;
1135}
1136}
1137
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1138defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1139 memopv16i32, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1140 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1141defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1142 memopv8i64, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1143 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1144
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1145// 512-bit unaligned load/store
1146def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1147def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1148
1149def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1150 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1151def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1152 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1153
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1154let AddedComplexity = 20 in {
1155def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1156 (v16f32 VR512:$src2))),
1157 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1158def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1159 (v8f64 VR512:$src2))),
1160 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1161def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1162 (v16i32 VR512:$src2))),
1163 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1164def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1165 (v8i64 VR512:$src2))),
1166 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1167}
1168// Move Int Doubleword to Packed Double Int
1169//
1170def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1171 "vmovd{z}\t{$src, $dst|$dst, $src}",
1172 [(set VR128X:$dst,
1173 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1174 EVEX, VEX_LIG;
1175def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1176 "vmovd{z}\t{$src, $dst|$dst, $src}",
1177 [(set VR128X:$dst,
1178 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1179 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1180def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1181 "vmovq{z}\t{$src, $dst|$dst, $src}",
1182 [(set VR128X:$dst,
1183 (v2i64 (scalar_to_vector GR64:$src)))],
1184 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1185let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1186def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1187 "vmovq{z}\t{$src, $dst|$dst, $src}",
1188 [(set FR64:$dst, (bitconvert GR64:$src))],
1189 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1190def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1191 "vmovq{z}\t{$src, $dst|$dst, $src}",
1192 [(set GR64:$dst, (bitconvert FR64:$src))],
1193 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1194}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1195def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1196 "vmovq{z}\t{$src, $dst|$dst, $src}",
1197 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1198 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1199 EVEX_CD8<64, CD8VT1>;
1200
1201// Move Int Doubleword to Single Scalar
1202//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1203let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1204def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1205 "vmovd{z}\t{$src, $dst|$dst, $src}",
1206 [(set FR32X:$dst, (bitconvert GR32:$src))],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1208
1209def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1210 "vmovd{z}\t{$src, $dst|$dst, $src}",
1211 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1212 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1213}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1214
1215// Move Packed Doubleword Int to Packed Double Int
1216//
1217def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1218 "vmovd{z}\t{$src, $dst|$dst, $src}",
1219 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1220 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1221 EVEX, VEX_LIG;
1222def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1223 (ins i32mem:$dst, VR128X:$src),
1224 "vmovd{z}\t{$src, $dst|$dst, $src}",
1225 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1226 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1227 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1228
1229// Move Packed Doubleword Int first element to Doubleword Int
1230//
1231def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1232 "vmovq{z}\t{$src, $dst|$dst, $src}",
1233 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1234 (iPTR 0)))],
1235 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1236 Requires<[HasAVX512, In64BitMode]>;
1237
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1238def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1239 (ins i64mem:$dst, VR128X:$src),
1240 "vmovq{z}\t{$src, $dst|$dst, $src}",
1241 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1242 addr:$dst)], IIC_SSE_MOVDQ>,
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1243 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1244 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1245
1246// Move Scalar Single to Double Int
1247//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1248let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1249def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1250 (ins FR32X:$src),
1251 "vmovd{z}\t{$src, $dst|$dst, $src}",
1252 [(set GR32:$dst, (bitconvert FR32X:$src))],
1253 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1254def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1255 (ins i32mem:$dst, FR32X:$src),
1256 "vmovd{z}\t{$src, $dst|$dst, $src}",
1257 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1258 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1259}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1260
1261// Move Quadword Int to Packed Quadword Int
1262//
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1263def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1264 (ins i64mem:$src),
1265 "vmovq{z}\t{$src, $dst|$dst, $src}",
1266 [(set VR128X:$dst,
1267 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1268 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1269
1270//===----------------------------------------------------------------------===//
1271// AVX-512 MOVSS, MOVSD
1272//===----------------------------------------------------------------------===//
1273
1274multiclass avx512_move_scalar <string asm, RegisterClass RC,
1275 SDNode OpNode, ValueType vt,
1276 X86MemOperand x86memop, PatFrag mem_pat> {
1277 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1279 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1280 (scalar_to_vector RC:$src2))))],
1281 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1282 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1283 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1284 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1285 EVEX, VEX_LIG;
1286 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1287 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1288 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1289 EVEX, VEX_LIG;
1290}
1291
1292let ExeDomain = SSEPackedSingle in
1293defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1294 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1295
1296let ExeDomain = SSEPackedDouble in
1297defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1298 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1299
1300
1301// For the disassembler
1302let isCodeGenOnly = 1 in {
1303 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1304 (ins VR128X:$src1, FR32X:$src2),
1305 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1306 IIC_SSE_MOV_S_RR>,
1307 XS, EVEX_4V, VEX_LIG;
1308 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1309 (ins VR128X:$src1, FR64X:$src2),
1310 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1311 IIC_SSE_MOV_S_RR>,
1312 XD, EVEX_4V, VEX_LIG, VEX_W;
1313}
1314
1315let Predicates = [HasAVX512] in {
1316 let AddedComplexity = 15 in {
1317 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1318 // MOVS{S,D} to the lower bits.
1319 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1320 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1321 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1322 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1323 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1324 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1325 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1326 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1327
1328 // Move low f32 and clear high bits.
1329 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1330 (SUBREG_TO_REG (i32 0),
1331 (VMOVSSZrr (v4f32 (V_SET0)),
1332 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1333 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1334 (SUBREG_TO_REG (i32 0),
1335 (VMOVSSZrr (v4i32 (V_SET0)),
1336 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1337 }
1338
1339 let AddedComplexity = 20 in {
1340 // MOVSSrm zeros the high parts of the register; represent this
1341 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1342 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1343 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1344 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1345 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1346 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1347 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1348
1349 // MOVSDrm zeros the high parts of the register; represent this
1350 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1351 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1352 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1353 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1354 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1355 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1356 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1357 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1358 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1359 def : Pat<(v2f64 (X86vzload addr:$src)),
1360 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1361
1362 // Represent the same patterns above but in the form they appear for
1363 // 256-bit types
1364 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1365 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1366 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1367 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1368 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1369 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1370 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1371 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1372 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1373 }
1374 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1375 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1376 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1377 FR32X:$src)), sub_xmm)>;
1378 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1379 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1380 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1381 FR64X:$src)), sub_xmm)>;
1382 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1383 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1384 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1385
1386 // Move low f64 and clear high bits.
1387 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1388 (SUBREG_TO_REG (i32 0),
1389 (VMOVSDZrr (v2f64 (V_SET0)),
1390 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1391
1392 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1393 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1394 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1395
1396 // Extract and store.
1397 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1398 addr:$dst),
1399 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1400 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1401 addr:$dst),
1402 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1403
1404 // Shuffle with VMOVSS
1405 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1406 (VMOVSSZrr (v4i32 VR128X:$src1),
1407 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1408 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1409 (VMOVSSZrr (v4f32 VR128X:$src1),
1410 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1411
1412 // 256-bit variants
1413 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1414 (SUBREG_TO_REG (i32 0),
1415 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1416 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1417 sub_xmm)>;
1418 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1419 (SUBREG_TO_REG (i32 0),
1420 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1421 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1422 sub_xmm)>;
1423
1424 // Shuffle with VMOVSD
1425 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1426 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1427 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1428 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1429 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1430 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1431 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1432 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1433
1434 // 256-bit variants
1435 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1436 (SUBREG_TO_REG (i32 0),
1437 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1438 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1439 sub_xmm)>;
1440 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1441 (SUBREG_TO_REG (i32 0),
1442 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1443 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1444 sub_xmm)>;
1445
1446 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1447 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1448 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1449 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1450 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1451 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1452 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1453 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1454}
1455
1456let AddedComplexity = 15 in
1457def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1458 (ins VR128X:$src),
1459 "vmovq{z}\t{$src, $dst|$dst, $src}",
1460 [(set VR128X:$dst, (v2i64 (X86vzmovl
1461 (v2i64 VR128X:$src))))],
1462 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1463
1464let AddedComplexity = 20 in
1465def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1466 (ins i128mem:$src),
1467 "vmovq{z}\t{$src, $dst|$dst, $src}",
1468 [(set VR128X:$dst, (v2i64 (X86vzmovl
1469 (loadv2i64 addr:$src))))],
1470 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1471 EVEX_CD8<8, CD8VT8>;
1472
1473let Predicates = [HasAVX512] in {
1474 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1475 let AddedComplexity = 20 in {
1476 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1477 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1478 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1479 (VMOV64toPQIZrr GR64:$src)>;
1480 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1481 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1482
1483 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1484 (VMOVDI2PDIZrm addr:$src)>;
1485 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1486 (VMOVDI2PDIZrm addr:$src)>;
1487 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1488 (VMOVZPQILo2PQIZrm addr:$src)>;
1489 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1490 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1491 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1492
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1493 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1494 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1495 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1496 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1497 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1498 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1499 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1500}
1501
1502def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1503 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1504
1505def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1506 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1507
1508def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1509 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1510
1511def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1512 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1513
1514//===----------------------------------------------------------------------===//
1515// AVX-512 - Integer arithmetic
1516//
1517multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1518 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1519 X86MemOperand x86memop, PatFrag scalar_mfrag,
1520 X86MemOperand x86scalar_mop, string BrdcstStr,
1521 OpndItins itins, bit IsCommutable = 0> {
1522 let isCommutable = IsCommutable in
1523 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1524 (ins RC:$src1, RC:$src2),
1525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1526 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1527 itins.rr>, EVEX_4V;
1528 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1529 (ins RC:$src1, x86memop:$src2),
1530 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1531 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1532 itins.rm>, EVEX_4V;
1533 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1534 (ins RC:$src1, x86scalar_mop:$src2),
1535 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1536 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1537 [(set RC:$dst, (OpNode RC:$src1,
1538 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1539 itins.rm>, EVEX_4V, EVEX_B;
1540}
1541multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1542 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1543 PatFrag memop_frag, X86MemOperand x86memop,
1544 OpndItins itins,
1545 bit IsCommutable = 0> {
1546 let isCommutable = IsCommutable in
1547 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1548 (ins RC:$src1, RC:$src2),
1549 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1550 []>, EVEX_4V, VEX_W;
1551 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1552 (ins RC:$src1, x86memop:$src2),
1553 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1554 []>, EVEX_4V, VEX_W;
1555}
1556
1557defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1558 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1559 EVEX_V512, EVEX_CD8<32, CD8VF>;
1560
1561defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1562 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1563 EVEX_V512, EVEX_CD8<32, CD8VF>;
1564
1565defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1566 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1567 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1568
1569defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1570 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1571 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1572
1573defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1574 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1575 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1576
1577defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1578 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1579 EVEX_V512, EVEX_CD8<64, CD8VF>;
1580
1581defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1582 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1583 EVEX_CD8<64, CD8VF>;
1584
1585def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1586 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1587
1588//===----------------------------------------------------------------------===//
1589// AVX-512 - Unpack Instructions
1590//===----------------------------------------------------------------------===//
1591
1592multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1593 PatFrag mem_frag, RegisterClass RC,
1594 X86MemOperand x86memop, string asm,
1595 Domain d> {
1596 def rr : AVX512PI<opc, MRMSrcReg,
1597 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1598 asm, [(set RC:$dst,
1599 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1600 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1601 def rm : AVX512PI<opc, MRMSrcMem,
1602 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1603 asm, [(set RC:$dst,
1604 (vt (OpNode RC:$src1,
1605 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1606 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1607}
1608
1609defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1610 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1611 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1612defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1613 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1614 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1615defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1616 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1617 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1618defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1619 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1620 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1621
1622multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1623 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1624 X86MemOperand x86memop> {
1625 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1626 (ins RC:$src1, RC:$src2),
1627 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1628 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1629 IIC_SSE_UNPCK>, EVEX_4V;
1630 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1631 (ins RC:$src1, x86memop:$src2),
1632 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1633 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1634 (bitconvert (memop_frag addr:$src2)))))],
1635 IIC_SSE_UNPCK>, EVEX_4V;
1636}
1637defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1638 VR512, memopv16i32, i512mem>, EVEX_V512,
1639 EVEX_CD8<32, CD8VF>;
1640defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1641 VR512, memopv8i64, i512mem>, EVEX_V512,
1642 VEX_W, EVEX_CD8<64, CD8VF>;
1643defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1644 VR512, memopv16i32, i512mem>, EVEX_V512,
1645 EVEX_CD8<32, CD8VF>;
1646defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1647 VR512, memopv8i64, i512mem>, EVEX_V512,
1648 VEX_W, EVEX_CD8<64, CD8VF>;
1649//===----------------------------------------------------------------------===//
1650// AVX-512 - PSHUFD
1651//
1652
1653multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1654 SDNode OpNode, PatFrag mem_frag,
1655 X86MemOperand x86memop, ValueType OpVT> {
1656 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1657 (ins RC:$src1, i8imm:$src2),
1658 !strconcat(OpcodeStr,
1659 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1660 [(set RC:$dst,
1661 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1662 EVEX;
1663 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1664 (ins x86memop:$src1, i8imm:$src2),
1665 !strconcat(OpcodeStr,
1666 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1667 [(set RC:$dst,
1668 (OpVT (OpNode (mem_frag addr:$src1),
1669 (i8 imm:$src2))))]>, EVEX;
1670}
1671
1672defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1673 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1674
1675let ExeDomain = SSEPackedSingle in
1676defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1677 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1678 EVEX_CD8<32, CD8VF>;
1679let ExeDomain = SSEPackedDouble in
1680defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1681 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1682 VEX_W, EVEX_CD8<32, CD8VF>;
1683
1684def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1685 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1686def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1687 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1688
1689//===----------------------------------------------------------------------===//
1690// AVX-512 Logical Instructions
1691//===----------------------------------------------------------------------===//
1692
1693defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1694 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1695 EVEX_V512, EVEX_CD8<32, CD8VF>;
1696defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1697 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1698 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1699defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1700 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1701 EVEX_V512, EVEX_CD8<32, CD8VF>;
1702defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1703 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1704 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1705defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1706 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1707 EVEX_V512, EVEX_CD8<32, CD8VF>;
1708defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1709 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1710 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1711defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1712 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1713 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1714defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1715 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1716 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1717
1718//===----------------------------------------------------------------------===//
1719// AVX-512 FP arithmetic
1720//===----------------------------------------------------------------------===//
1721
1722multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1723 SizeItins itins> {
1724 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1725 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1726 EVEX_CD8<32, CD8VT1>;
1727 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1728 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1729 EVEX_CD8<64, CD8VT1>;
1730}
1731
1732let isCommutable = 1 in {
1733defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1734defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1735defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1736defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1737}
1738let isCommutable = 0 in {
1739defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1740defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1741}
1742
1743multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1744 RegisterClass RC, ValueType vt,
1745 X86MemOperand x86memop, PatFrag mem_frag,
1746 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1747 string BrdcstStr,
1748 Domain d, OpndItins itins, bit commutable> {
1749 let isCommutable = commutable in
1750 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1751 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1752 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1753 EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1754 let mayLoad = 1 in {
1755 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1756 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1757 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1758 itins.rm, d>, EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1759 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1760 (ins RC:$src1, x86scalar_mop:$src2),
1761 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1762 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1763 [(set RC:$dst, (OpNode RC:$src1,
1764 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1765 itins.rm, d>, EVEX_4V, EVEX_B, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1766 }
1767}
1768
1769defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1770 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1771 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1772
1773defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1774 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1775 SSE_ALU_ITINS_P.d, 1>,
1776 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1777
1778defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1779 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1780 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1781defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1782 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1783 SSE_ALU_ITINS_P.d, 1>,
1784 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1785
1786defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1787 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1788 SSE_ALU_ITINS_P.s, 1>,
1789 EVEX_V512, EVEX_CD8<32, CD8VF>;
1790defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1791 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1792 SSE_ALU_ITINS_P.s, 1>,
1793 EVEX_V512, EVEX_CD8<32, CD8VF>;
1794
1795defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1796 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1797 SSE_ALU_ITINS_P.d, 1>,
1798 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1799defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1800 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1801 SSE_ALU_ITINS_P.d, 1>,
1802 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1803
1804defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1805 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1806 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1807defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1808 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1809 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1810
1811defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1812 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1813 SSE_ALU_ITINS_P.d, 0>,
1814 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1815defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1816 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1817 SSE_ALU_ITINS_P.d, 0>,
1818 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1819
1820//===----------------------------------------------------------------------===//
1821// AVX-512 VPTESTM instructions
1822//===----------------------------------------------------------------------===//
1823
1824multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1825 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1826 SDNode OpNode, ValueType vt> {
1827 def rr : AVX5128I<opc, MRMSrcReg,
1828 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1829 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1830 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1831 def rm : AVX5128I<opc, MRMSrcMem,
1832 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1834 [(set KRC:$dst, (OpNode (vt RC:$src1),
1835 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1836}
1837
1838defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1839 memopv16i32, X86testm, v16i32>, EVEX_V512,
1840 EVEX_CD8<32, CD8VF>;
1841defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1842 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1843 EVEX_CD8<64, CD8VF>;
1844
1845//===----------------------------------------------------------------------===//
1846// AVX-512 Shift instructions
1847//===----------------------------------------------------------------------===//
1848multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1849 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1850 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1851 RegisterClass KRC> {
1852 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1853 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1854 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1855 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1856 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1857 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1858 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1859 !strconcat(OpcodeStr,
1860 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1861 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1862 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1863 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1864 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1865 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1866 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1867 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1868 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1869 !strconcat(OpcodeStr,
1870 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1871 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1872}
1873
1874multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1875 RegisterClass RC, ValueType vt, ValueType SrcVT,
1876 PatFrag bc_frag, RegisterClass KRC> {
1877 // src2 is always 128-bit
1878 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1879 (ins RC:$src1, VR128X:$src2),
1880 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1881 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1882 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1883 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1884 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1885 !strconcat(OpcodeStr,
1886 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1887 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1888 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1889 (ins RC:$src1, i128mem:$src2),
1890 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1891 [(set RC:$dst, (vt (OpNode RC:$src1,
1892 (bc_frag (memopv2i64 addr:$src2)))))],
1893 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1894 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1895 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1896 !strconcat(OpcodeStr,
1897 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1898 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1899}
1900
1901defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1902 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1903 EVEX_V512, EVEX_CD8<32, CD8VF>;
1904defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1905 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1906 EVEX_CD8<32, CD8VQ>;
1907
1908defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1909 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1910 EVEX_CD8<64, CD8VF>, VEX_W;
1911defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1912 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1913 EVEX_CD8<64, CD8VQ>, VEX_W;
1914
1915defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1916 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1917 EVEX_CD8<32, CD8VF>;
1918defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1919 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1920 EVEX_CD8<32, CD8VQ>;
1921
1922defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1923 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1924 EVEX_CD8<64, CD8VF>, VEX_W;
1925defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1926 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1927 EVEX_CD8<64, CD8VQ>, VEX_W;
1928
1929defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1930 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1931 EVEX_V512, EVEX_CD8<32, CD8VF>;
1932defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1933 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1934 EVEX_CD8<32, CD8VQ>;
1935
1936defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1937 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1938 EVEX_CD8<64, CD8VF>, VEX_W;
1939defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1940 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1941 EVEX_CD8<64, CD8VQ>, VEX_W;
1942
1943//===-------------------------------------------------------------------===//
1944// Variable Bit Shifts
1945//===-------------------------------------------------------------------===//
1946multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1947 RegisterClass RC, ValueType vt,
1948 X86MemOperand x86memop, PatFrag mem_frag> {
1949 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1950 (ins RC:$src1, RC:$src2),
1951 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1952 [(set RC:$dst,
1953 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1954 EVEX_4V;
1955 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1956 (ins RC:$src1, x86memop:$src2),
1957 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1958 [(set RC:$dst,
1959 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1960 EVEX_4V;
1961}
1962
1963defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1964 i512mem, memopv16i32>, EVEX_V512,
1965 EVEX_CD8<32, CD8VF>;
1966defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1967 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1968 EVEX_CD8<64, CD8VF>;
1969defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1970 i512mem, memopv16i32>, EVEX_V512,
1971 EVEX_CD8<32, CD8VF>;
1972defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1973 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1974 EVEX_CD8<64, CD8VF>;
1975defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1976 i512mem, memopv16i32>, EVEX_V512,
1977 EVEX_CD8<32, CD8VF>;
1978defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1979 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1980 EVEX_CD8<64, CD8VF>;
1981
1982//===----------------------------------------------------------------------===//
1983// AVX-512 - MOVDDUP
1984//===----------------------------------------------------------------------===//
1985
1986multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1987 X86MemOperand x86memop, PatFrag memop_frag> {
1988def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1990 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
1991def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1992 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1993 [(set RC:$dst,
1994 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
1995}
1996
1997defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
1998 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1999def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2000 (VMOVDDUPZrm addr:$src)>;
2001
2002def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2003 (ins VR128X:$src1, VR128X:$src2),
2004 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2005 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2006 IIC_SSE_MOV_LH>, EVEX_4V;
2007def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2008 (ins VR128X:$src1, VR128X:$src2),
2009 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2010 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2011 IIC_SSE_MOV_LH>, EVEX_4V;
2012
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2013let Predicates = [HasAVX512] in {
2014 // MOVLHPS patterns
2015 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2016 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2017 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2018 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2019
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2020 // MOVHLPS patterns
2021 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2022 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2023}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2024
2025//===----------------------------------------------------------------------===//
2026// FMA - Fused Multiply Operations
2027//
2028let Constraints = "$src1 = $dst" in {
2029multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2030 RegisterClass RC, X86MemOperand x86memop,
2031 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2032 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2033 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2034 (ins RC:$src1, RC:$src2, RC:$src3),
2035 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2036 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2037
2038 let mayLoad = 1 in
2039 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2040 (ins RC:$src1, RC:$src2, x86memop:$src3),
2041 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2042 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2043 (mem_frag addr:$src3))))]>;
2044 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2045 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2046 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2047 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2048 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2049 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2050}
2051} // Constraints = "$src1 = $dst"
2052
2053let ExeDomain = SSEPackedSingle in {
2054 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2055 memopv16f32, f32mem, loadf32, "{1to16}",
2056 X86Fmadd, v16f32>, EVEX_V512,
2057 EVEX_CD8<32, CD8VF>;
2058 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2059 memopv16f32, f32mem, loadf32, "{1to16}",
2060 X86Fmsub, v16f32>, EVEX_V512,
2061 EVEX_CD8<32, CD8VF>;
2062 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2063 memopv16f32, f32mem, loadf32, "{1to16}",
2064 X86Fmaddsub, v16f32>,
2065 EVEX_V512, EVEX_CD8<32, CD8VF>;
2066 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2067 memopv16f32, f32mem, loadf32, "{1to16}",
2068 X86Fmsubadd, v16f32>,
2069 EVEX_V512, EVEX_CD8<32, CD8VF>;
2070 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2071 memopv16f32, f32mem, loadf32, "{1to16}",
2072 X86Fnmadd, v16f32>, EVEX_V512,
2073 EVEX_CD8<32, CD8VF>;
2074 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2075 memopv16f32, f32mem, loadf32, "{1to16}",
2076 X86Fnmsub, v16f32>, EVEX_V512,
2077 EVEX_CD8<32, CD8VF>;
2078}
2079let ExeDomain = SSEPackedDouble in {
2080 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2081 memopv8f64, f64mem, loadf64, "{1to8}",
2082 X86Fmadd, v8f64>, EVEX_V512,
2083 VEX_W, EVEX_CD8<64, CD8VF>;
2084 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2085 memopv8f64, f64mem, loadf64, "{1to8}",
2086 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2087 EVEX_CD8<64, CD8VF>;
2088 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2089 memopv8f64, f64mem, loadf64, "{1to8}",
2090 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2091 EVEX_CD8<64, CD8VF>;
2092 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2093 memopv8f64, f64mem, loadf64, "{1to8}",
2094 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2095 EVEX_CD8<64, CD8VF>;
2096 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2097 memopv8f64, f64mem, loadf64, "{1to8}",
2098 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2099 EVEX_CD8<64, CD8VF>;
2100 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2101 memopv8f64, f64mem, loadf64, "{1to8}",
2102 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2103 EVEX_CD8<64, CD8VF>;
2104}
2105
2106let Constraints = "$src1 = $dst" in {
2107multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2108 RegisterClass RC, X86MemOperand x86memop,
2109 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2110 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2111 let mayLoad = 1 in
2112 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2113 (ins RC:$src1, RC:$src3, x86memop:$src2),
2114 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2115 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2116 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2117 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2118 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2119 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2120 [(set RC:$dst, (OpNode RC:$src1,
2121 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2122}
2123} // Constraints = "$src1 = $dst"
2124
2125
2126let ExeDomain = SSEPackedSingle in {
2127 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2128 memopv16f32, f32mem, loadf32, "{1to16}",
2129 X86Fmadd, v16f32>, EVEX_V512,
2130 EVEX_CD8<32, CD8VF>;
2131 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2132 memopv16f32, f32mem, loadf32, "{1to16}",
2133 X86Fmsub, v16f32>, EVEX_V512,
2134 EVEX_CD8<32, CD8VF>;
2135 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2136 memopv16f32, f32mem, loadf32, "{1to16}",
2137 X86Fmaddsub, v16f32>,
2138 EVEX_V512, EVEX_CD8<32, CD8VF>;
2139 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2140 memopv16f32, f32mem, loadf32, "{1to16}",
2141 X86Fmsubadd, v16f32>,
2142 EVEX_V512, EVEX_CD8<32, CD8VF>;
2143 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2144 memopv16f32, f32mem, loadf32, "{1to16}",
2145 X86Fnmadd, v16f32>, EVEX_V512,
2146 EVEX_CD8<32, CD8VF>;
2147 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2148 memopv16f32, f32mem, loadf32, "{1to16}",
2149 X86Fnmsub, v16f32>, EVEX_V512,
2150 EVEX_CD8<32, CD8VF>;
2151}
2152let ExeDomain = SSEPackedDouble in {
2153 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2154 memopv8f64, f64mem, loadf64, "{1to8}",
2155 X86Fmadd, v8f64>, EVEX_V512,
2156 VEX_W, EVEX_CD8<64, CD8VF>;
2157 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2158 memopv8f64, f64mem, loadf64, "{1to8}",
2159 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2160 EVEX_CD8<64, CD8VF>;
2161 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2162 memopv8f64, f64mem, loadf64, "{1to8}",
2163 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2164 EVEX_CD8<64, CD8VF>;
2165 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2166 memopv8f64, f64mem, loadf64, "{1to8}",
2167 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2168 EVEX_CD8<64, CD8VF>;
2169 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2170 memopv8f64, f64mem, loadf64, "{1to8}",
2171 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2172 EVEX_CD8<64, CD8VF>;
2173 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2174 memopv8f64, f64mem, loadf64, "{1to8}",
2175 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2176 EVEX_CD8<64, CD8VF>;
2177}
2178
2179// Scalar FMA
2180let Constraints = "$src1 = $dst" in {
2181multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2182 RegisterClass RC, ValueType OpVT,
2183 X86MemOperand x86memop, Operand memop,
2184 PatFrag mem_frag> {
2185 let isCommutable = 1 in
2186 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2187 (ins RC:$src1, RC:$src2, RC:$src3),
2188 !strconcat(OpcodeStr,
2189 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2190 [(set RC:$dst,
2191 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2192 let mayLoad = 1 in
2193 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2194 (ins RC:$src1, RC:$src2, f128mem:$src3),
2195 !strconcat(OpcodeStr,
2196 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2197 [(set RC:$dst,
2198 (OpVT (OpNode RC:$src2, RC:$src1,
2199 (mem_frag addr:$src3))))]>;
2200}
2201
2202} // Constraints = "$src1 = $dst"
2203
2204defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2205 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2206defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2207 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2208defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2209 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2210defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2211 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2212defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2213 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2214defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2215 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2216defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2217 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2218defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2219 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2220
2221//===----------------------------------------------------------------------===//
2222// AVX-512 Scalar convert from sign integer to float/double
2223//===----------------------------------------------------------------------===//
2224
2225multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2226 X86MemOperand x86memop, string asm> {
2227let neverHasSideEffects = 1 in {
2228 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2229 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2230 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2231 let mayLoad = 1 in
2232 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2233 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2234 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2235 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2236} // neverHasSideEffects = 1
2237}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2238let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2239defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2240 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2241defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2242 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2243defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2244 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2245defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2246 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2247
2248def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2249 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2250def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2251 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2252def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2253 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2254def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2255 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2256
2257def : Pat<(f32 (sint_to_fp GR32:$src)),
2258 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2259def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2260 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2261def : Pat<(f64 (sint_to_fp GR32:$src)),
2262 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2263def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2264 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2265
2266defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2267 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2268defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2269 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2270defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2271 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2272defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2273 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2274
2275def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2276 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2277def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2278 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2279def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2280 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2281def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2282 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2283
2284def : Pat<(f32 (uint_to_fp GR32:$src)),
2285 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2286def : Pat<(f32 (uint_to_fp GR64:$src)),
2287 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2288def : Pat<(f64 (uint_to_fp GR32:$src)),
2289 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2290def : Pat<(f64 (uint_to_fp GR64:$src)),
2291 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2292}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2293
2294//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2295// AVX-512 Scalar convert from float/double to integer
2296//===----------------------------------------------------------------------===//
2297multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2298 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2299 string asm> {
2300let neverHasSideEffects = 1 in {
2301 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2302 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2303 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2304 let mayLoad = 1 in
2305 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2306 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2307} // neverHasSideEffects = 1
2308}
2309let Predicates = [HasAVX512] in {
2310// Convert float/double to signed/unsigned int 32/64
2311defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2312 ssmem, sse_load_f32, "cvtss2si{z}">,
2313 XS, EVEX_CD8<32, CD8VT1>;
2314defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2315 ssmem, sse_load_f32, "cvtss2si{z}">,
2316 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2317defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2318 ssmem, sse_load_f32, "cvtss2usi{z}">,
2319 XS, EVEX_CD8<32, CD8VT1>;
2320defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2321 int_x86_avx512_cvtss2usi64, ssmem,
2322 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2323 EVEX_CD8<32, CD8VT1>;
2324defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2325 sdmem, sse_load_f64, "cvtsd2si{z}">,
2326 XD, EVEX_CD8<64, CD8VT1>;
2327defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2328 sdmem, sse_load_f64, "cvtsd2si{z}">,
2329 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2330defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2331 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2332 XD, EVEX_CD8<64, CD8VT1>;
2333defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2334 int_x86_avx512_cvtsd2usi64, sdmem,
2335 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2336 EVEX_CD8<64, CD8VT1>;
2337
2338defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2339 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2340 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2341defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2342 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2343 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2344defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2345 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2346 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2347defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2348 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2349 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2350
2351defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2352 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2353 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2354defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2355 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2356 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2357defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2358 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2359 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2360defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2361 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2362 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2363
2364// Convert float/double to signed/unsigned int 32/64 with truncation
2365defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2366 ssmem, sse_load_f32, "cvttss2si{z}">,
2367 XS, EVEX_CD8<32, CD8VT1>;
2368defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2369 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2370 "cvttss2si{z}">, XS, VEX_W,
2371 EVEX_CD8<32, CD8VT1>;
2372defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2373 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2374 EVEX_CD8<64, CD8VT1>;
2375defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2376 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2377 "cvttsd2si{z}">, XD, VEX_W,
2378 EVEX_CD8<64, CD8VT1>;
2379defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2380 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2381 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2382defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2383 int_x86_avx512_cvttss2usi64, ssmem,
2384 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2385 EVEX_CD8<32, CD8VT1>;
2386defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2387 int_x86_avx512_cvttsd2usi,
2388 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2389 EVEX_CD8<64, CD8VT1>;
2390defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2391 int_x86_avx512_cvttsd2usi64, sdmem,
2392 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2393 EVEX_CD8<64, CD8VT1>;
2394}
2395
2396multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2397 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2398 string asm> {
2399 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2400 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2401 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2402 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2403 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2404 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2405}
2406
2407defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2408 loadf32, "cvttss2si{z}">, XS,
2409 EVEX_CD8<32, CD8VT1>;
2410defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2411 loadf32, "cvttss2usi{z}">, XS,
2412 EVEX_CD8<32, CD8VT1>;
2413defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2414 loadf32, "cvttss2si{z}">, XS, VEX_W,
2415 EVEX_CD8<32, CD8VT1>;
2416defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2417 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2418 EVEX_CD8<32, CD8VT1>;
2419defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2420 loadf64, "cvttsd2si{z}">, XD,
2421 EVEX_CD8<64, CD8VT1>;
2422defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2423 loadf64, "cvttsd2usi{z}">, XD,
2424 EVEX_CD8<64, CD8VT1>;
2425defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2426 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2427 EVEX_CD8<64, CD8VT1>;
2428defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2429 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2430 EVEX_CD8<64, CD8VT1>;
2431//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2432// AVX-512 Convert form float to double and back
2433//===----------------------------------------------------------------------===//
2434let neverHasSideEffects = 1 in {
2435def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2436 (ins FR32X:$src1, FR32X:$src2),
2437 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2438 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2439let mayLoad = 1 in
2440def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2441 (ins FR32X:$src1, f32mem:$src2),
2442 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2443 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2444 EVEX_CD8<32, CD8VT1>;
2445
2446// Convert scalar double to scalar single
2447def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2448 (ins FR64X:$src1, FR64X:$src2),
2449 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2450 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2451let mayLoad = 1 in
2452def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2453 (ins FR64X:$src1, f64mem:$src2),
2454 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2455 []>, EVEX_4V, VEX_LIG, VEX_W,
2456 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2457}
2458
2459def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2460 Requires<[HasAVX512]>;
2461def : Pat<(fextend (loadf32 addr:$src)),
2462 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2463
2464def : Pat<(extloadf32 addr:$src),
2465 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2466 Requires<[HasAVX512, OptForSize]>;
2467
2468def : Pat<(extloadf32 addr:$src),
2469 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2470 Requires<[HasAVX512, OptForSpeed]>;
2471
2472def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2473 Requires<[HasAVX512]>;
2474
2475multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2476 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2477 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2478 Domain d> {
2479let neverHasSideEffects = 1 in {
2480 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2481 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2482 [(set DstRC:$dst,
2483 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2484 let mayLoad = 1 in
2485 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2486 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2487 [(set DstRC:$dst,
2488 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2489} // neverHasSideEffects = 1
2490}
2491
2492defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2493 memopv8f64, f512mem, v8f32, v8f64,
2494 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2495 EVEX_CD8<64, CD8VF>;
2496
2497defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2498 memopv4f64, f256mem, v8f64, v8f32,
2499 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2500def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2501 (VCVTPS2PDZrm addr:$src)>;
2502
2503//===----------------------------------------------------------------------===//
2504// AVX-512 Vector convert from sign integer to float/double
2505//===----------------------------------------------------------------------===//
2506
2507defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2508 memopv8i64, i512mem, v16f32, v16i32,
2509 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2510
2511defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2512 memopv4i64, i256mem, v8f64, v8i32,
2513 SSEPackedDouble>, EVEX_V512, XS,
2514 EVEX_CD8<32, CD8VH>;
2515
2516defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2517 memopv16f32, f512mem, v16i32, v16f32,
2518 SSEPackedSingle>, EVEX_V512, XS,
2519 EVEX_CD8<32, CD8VF>;
2520
2521defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2522 memopv8f64, f512mem, v8i32, v8f64,
2523 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2524 EVEX_CD8<64, CD8VF>;
2525
2526defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2527 memopv16f32, f512mem, v16i32, v16f32,
2528 SSEPackedSingle>, EVEX_V512,
2529 EVEX_CD8<32, CD8VF>;
2530
2531defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2532 memopv8f64, f512mem, v8i32, v8f64,
2533 SSEPackedDouble>, EVEX_V512, VEX_W,
2534 EVEX_CD8<64, CD8VF>;
2535
2536defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2537 memopv4i64, f256mem, v8f64, v8i32,
2538 SSEPackedDouble>, EVEX_V512, XS,
2539 EVEX_CD8<32, CD8VH>;
2540
2541defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2542 memopv16i32, f512mem, v16f32, v16i32,
2543 SSEPackedSingle>, EVEX_V512, XD,
2544 EVEX_CD8<32, CD8VF>;
2545
2546def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2547 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2548 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2549
2550
2551def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2552 (VCVTDQ2PSZrr VR512:$src)>;
2553def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2554 (VCVTDQ2PSZrm addr:$src)>;
2555
2556def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2557 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2558 [(set VR512:$dst,
2559 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2560 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2561def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2562 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2563 [(set VR512:$dst,
2564 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2565 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2566
2567
2568let Predicates = [HasAVX512] in {
2569 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2570 (VCVTPD2PSZrm addr:$src)>;
2571 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2572 (VCVTPS2PDZrm addr:$src)>;
2573}
2574
2575let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2576 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2577 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2578 EVEX_CD8<32, CD8VT1>;
2579 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2580 "ucomisd{z}">, TB, OpSize, EVEX,
2581 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2582 let Pattern = []<dag> in {
2583 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2584 "comiss{z}">, TB, EVEX, VEX_LIG,
2585 EVEX_CD8<32, CD8VT1>;
2586 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2587 "comisd{z}">, TB, OpSize, EVEX,
2588 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2589 }
2590 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2591 load, "ucomiss">, TB, EVEX, VEX_LIG,
2592 EVEX_CD8<32, CD8VT1>;
2593 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2594 load, "ucomisd">, TB, OpSize, EVEX,
2595 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2596
2597 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2598 load, "comiss">, TB, EVEX, VEX_LIG,
2599 EVEX_CD8<32, CD8VT1>;
2600 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2601 load, "comisd">, TB, OpSize, EVEX,
2602 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2603}
2604
2605/// avx512_unop_p - AVX-512 unops in packed form.
2606multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2607 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2608 !strconcat(OpcodeStr,
2609 "ps\t{$src, $dst|$dst, $src}"),
2610 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2611 EVEX, EVEX_V512;
2612 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2613 !strconcat(OpcodeStr,
2614 "ps\t{$src, $dst|$dst, $src}"),
2615 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2616 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2617 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2618 !strconcat(OpcodeStr,
2619 "pd\t{$src, $dst|$dst, $src}"),
2620 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2621 EVEX, EVEX_V512, VEX_W;
2622 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2623 !strconcat(OpcodeStr,
2624 "pd\t{$src, $dst|$dst, $src}"),
2625 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2626 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2627}
2628
2629/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2630multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2631 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2632 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2633 !strconcat(OpcodeStr,
2634 "ps\t{$src, $dst|$dst, $src}"),
2635 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2636 EVEX, EVEX_V512;
2637 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2638 !strconcat(OpcodeStr,
2639 "ps\t{$src, $dst|$dst, $src}"),
2640 [(set VR512:$dst,
2641 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2642 EVEX_V512, EVEX_CD8<32, CD8VF>;
2643 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2644 !strconcat(OpcodeStr,
2645 "pd\t{$src, $dst|$dst, $src}"),
2646 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2647 EVEX, EVEX_V512, VEX_W;
2648 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2649 !strconcat(OpcodeStr,
2650 "pd\t{$src, $dst|$dst, $src}"),
2651 [(set VR512:$dst,
2652 (V8F64Int (memopv8f64 addr:$src)))]>,
2653 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2654}
2655
2656/// avx512_fp_unop_s - AVX-512 unops in scalar form.
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2657multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2658 let hasSideEffects = 0 in {
2659 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2660 (ins FR32X:$src1, FR32X:$src2),
2661 !strconcat(OpcodeStr,
2662 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2663 []>, EVEX_4V;
2664 let mayLoad = 1 in {
2665 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2666 (ins FR32X:$src1, f32mem:$src2),
2667 !strconcat(OpcodeStr,
2668 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2669 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2670 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2671 (ins VR128X:$src1, ssmem:$src2),
2672 !strconcat(OpcodeStr,
2673 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2674 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2675 }
2676 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2677 (ins FR64X:$src1, FR64X:$src2),
2678 !strconcat(OpcodeStr,
2679 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2680 EVEX_4V, VEX_W;
2681 let mayLoad = 1 in {
2682 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2683 (ins FR64X:$src1, f64mem:$src2),
2684 !strconcat(OpcodeStr,
2685 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2686 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2687 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2688 (ins VR128X:$src1, sdmem:$src2),
2689 !strconcat(OpcodeStr,
2690 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2691 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2692 }
2693}
2694}
2695
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2696defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2697 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2698 avx512_fp_unop_p_int<0x4C, "vrcp14",
2699 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2700
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2701defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2702 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2703 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2704 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2705
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2706def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2707 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2708 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2709 VR128X)>;
2710def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2711 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2712
2713def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2714 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2715 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2716 VR128X)>;
2717def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2718 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2719
2720let AddedComplexity = 20, Predicates = [HasERI] in {
2721defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2722 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2723 avx512_fp_unop_p_int<0xCA, "vrcp28",
2724 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2725
2726defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2727 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2728 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2729 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2730}
2731
2732let Predicates = [HasERI] in {
2733 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2734 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2735 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2736 VR128X)>;
2737 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2738 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2739
2740 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2741 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2742 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2743 VR128X)>;
2744 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2745 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2746}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2747multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2748 Intrinsic V16F32Int, Intrinsic V8F64Int,
2749 OpndItins itins_s, OpndItins itins_d> {
2750 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2752 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2753 EVEX, EVEX_V512;
2754
2755 let mayLoad = 1 in
2756 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2757 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2758 [(set VR512:$dst,
2759 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2760 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2761
2762 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2763 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2764 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2765 EVEX, EVEX_V512;
2766
2767 let mayLoad = 1 in
2768 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2769 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2770 [(set VR512:$dst, (OpNode
2771 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2772 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2773
2774 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2775 !strconcat(OpcodeStr,
2776 "ps\t{$src, $dst|$dst, $src}"),
2777 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2778 EVEX, EVEX_V512;
2779 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2780 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2781 [(set VR512:$dst,
2782 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2783 EVEX_V512, EVEX_CD8<32, CD8VF>;
2784 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2785 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2786 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2787 EVEX, EVEX_V512, VEX_W;
2788 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2789 !strconcat(OpcodeStr,
2790 "pd\t{$src, $dst|$dst, $src}"),
2791 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2792 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2793}
2794
2795multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2796 Intrinsic F32Int, Intrinsic F64Int,
2797 OpndItins itins_s, OpndItins itins_d> {
2798 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2799 (ins FR32X:$src1, FR32X:$src2),
2800 !strconcat(OpcodeStr,
2801 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2802 [], itins_s.rr>, XS, EVEX_4V;
2803 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2804 (ins VR128X:$src1, VR128X:$src2),
2805 !strconcat(OpcodeStr,
2806 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2807 [(set VR128X:$dst,
2808 (F32Int VR128X:$src1, VR128X:$src2))],
2809 itins_s.rr>, XS, EVEX_4V;
2810 let mayLoad = 1 in {
2811 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2812 (ins FR32X:$src1, f32mem:$src2),
2813 !strconcat(OpcodeStr,
2814 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2815 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2816 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2817 (ins VR128X:$src1, ssmem:$src2),
2818 !strconcat(OpcodeStr,
2819 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2820 [(set VR128X:$dst,
2821 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2822 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2823 }
2824 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2825 (ins FR64X:$src1, FR64X:$src2),
2826 !strconcat(OpcodeStr,
2827 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2828 XD, EVEX_4V, VEX_W;
2829 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2830 (ins VR128X:$src1, VR128X:$src2),
2831 !strconcat(OpcodeStr,
2832 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2833 [(set VR128X:$dst,
2834 (F64Int VR128X:$src1, VR128X:$src2))],
2835 itins_s.rr>, XD, EVEX_4V, VEX_W;
2836 let mayLoad = 1 in {
2837 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2838 (ins FR64X:$src1, f64mem:$src2),
2839 !strconcat(OpcodeStr,
2840 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2841 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2842 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2843 (ins VR128X:$src1, sdmem:$src2),
2844 !strconcat(OpcodeStr,
2845 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2846 [(set VR128X:$dst,
2847 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2848 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2849 }
2850}
2851
2852
2853defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2854 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2855 SSE_SQRTSS, SSE_SQRTSD>,
2856 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2857 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2858 SSE_SQRTPS, SSE_SQRTPD>;
2859
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2860let Predicates = [HasAVX512] in {
2861 def : Pat<(f32 (fsqrt FR32X:$src)),
2862 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2863 def : Pat<(f32 (fsqrt (load addr:$src))),
2864 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2865 Requires<[OptForSize]>;
2866 def : Pat<(f64 (fsqrt FR64X:$src)),
2867 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2868 def : Pat<(f64 (fsqrt (load addr:$src))),
2869 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2870 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2871
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2872 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2873 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2874 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2875 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2876 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2877
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2878 def : Pat<(f32 (X86frcp FR32X:$src)),
2879 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2880 def : Pat<(f32 (X86frcp (load addr:$src))),
2881 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2882 Requires<[OptForSize]>;
2883
2884 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2885 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2886 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2887 VR128X)>;
2888 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2889 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2890
2891 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
2892 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
2893 (COPY_TO_REGCLASS VR128X:$src, FR64)),
2894 VR128X)>;
2895 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2896 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2897}
2898
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2899
2900multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2901 X86MemOperand x86memop, RegisterClass RC,
2902 PatFrag mem_frag32, PatFrag mem_frag64,
2903 Intrinsic V4F32Int, Intrinsic V2F64Int,
2904 CD8VForm VForm> {
2905let ExeDomain = SSEPackedSingle in {
2906 // Intrinsic operation, reg.
2907 // Vector intrinsic operation, reg
2908 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2909 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2910 !strconcat(OpcodeStr,
2911 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2912 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2913
2914 // Vector intrinsic operation, mem
2915 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2916 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2917 !strconcat(OpcodeStr,
2918 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2919 [(set RC:$dst,
2920 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2921 EVEX_CD8<32, VForm>;
2922} // ExeDomain = SSEPackedSingle
2923
2924let ExeDomain = SSEPackedDouble in {
2925 // Vector intrinsic operation, reg
2926 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2927 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2928 !strconcat(OpcodeStr,
2929 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2930 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2931
2932 // Vector intrinsic operation, mem
2933 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2934 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2935 !strconcat(OpcodeStr,
2936 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2937 [(set RC:$dst,
2938 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2939 EVEX_CD8<64, VForm>;
2940} // ExeDomain = SSEPackedDouble
2941}
2942
2943multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2944 string OpcodeStr,
2945 Intrinsic F32Int,
2946 Intrinsic F64Int> {
2947let ExeDomain = GenericDomain in {
2948 // Operation, reg.
2949 let hasSideEffects = 0 in
2950 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2951 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2952 !strconcat(OpcodeStr,
2953 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2954 []>;
2955
2956 // Intrinsic operation, reg.
2957 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2958 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2959 !strconcat(OpcodeStr,
2960 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2961 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
2962
2963 // Intrinsic operation, mem.
2964 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
2965 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
2966 !strconcat(OpcodeStr,
2967 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2968 [(set VR128X:$dst, (F32Int VR128X:$src1,
2969 sse_load_f32:$src2, imm:$src3))]>,
2970 EVEX_CD8<32, CD8VT1>;
2971
2972 // Operation, reg.
2973 let hasSideEffects = 0 in
2974 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
2975 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
2976 !strconcat(OpcodeStr,
2977 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2978 []>, VEX_W;
2979
2980 // Intrinsic operation, reg.
2981 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
2982 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2983 !strconcat(OpcodeStr,
2984 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2985 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
2986 VEX_W;
2987
2988 // Intrinsic operation, mem.
2989 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
2990 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
2991 !strconcat(OpcodeStr,
2992 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2993 [(set VR128X:$dst,
2994 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
2995 VEX_W, EVEX_CD8<64, CD8VT1>;
2996} // ExeDomain = GenericDomain
2997}
2998
2999let Predicates = [HasAVX512] in {
3000 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3001 int_x86_avx512_rndscale_ss,
3002 int_x86_avx512_rndscale_sd>, EVEX_4V;
3003
3004 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3005 memopv16f32, memopv8f64,
3006 int_x86_avx512_rndscale_ps_512,
3007 int_x86_avx512_rndscale_pd_512, CD8VF>,
3008 EVEX, EVEX_V512;
3009}
3010
3011def : Pat<(ffloor FR32X:$src),
3012 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3013def : Pat<(f64 (ffloor FR64X:$src)),
3014 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3015def : Pat<(f32 (fnearbyint FR32X:$src)),
3016 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3017def : Pat<(f64 (fnearbyint FR64X:$src)),
3018 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3019def : Pat<(f32 (fceil FR32X:$src)),
3020 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3021def : Pat<(f64 (fceil FR64X:$src)),
3022 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3023def : Pat<(f32 (frint FR32X:$src)),
3024 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3025def : Pat<(f64 (frint FR64X:$src)),
3026 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3027def : Pat<(f32 (ftrunc FR32X:$src)),
3028 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3029def : Pat<(f64 (ftrunc FR64X:$src)),
3030 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3031
3032def : Pat<(v16f32 (ffloor VR512:$src)),
3033 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3034def : Pat<(v16f32 (fnearbyint VR512:$src)),
3035 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3036def : Pat<(v16f32 (fceil VR512:$src)),
3037 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3038def : Pat<(v16f32 (frint VR512:$src)),
3039 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3040def : Pat<(v16f32 (ftrunc VR512:$src)),
3041 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3042
3043def : Pat<(v8f64 (ffloor VR512:$src)),
3044 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3045def : Pat<(v8f64 (fnearbyint VR512:$src)),
3046 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3047def : Pat<(v8f64 (fceil VR512:$src)),
3048 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3049def : Pat<(v8f64 (frint VR512:$src)),
3050 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3051def : Pat<(v8f64 (ftrunc VR512:$src)),
3052 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3053
3054//-------------------------------------------------
3055// Integer truncate and extend operations
3056//-------------------------------------------------
3057
3058multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3059 RegisterClass dstRC, RegisterClass srcRC,
3060 RegisterClass KRC, X86MemOperand x86memop> {
3061 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3062 (ins srcRC:$src),
3063 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3064 []>, EVEX;
3065
3066 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3067 (ins KRC:$mask, srcRC:$src),
3068 !strconcat(OpcodeStr,
3069 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3070 []>, EVEX, EVEX_KZ;
3071
3072 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3073 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3074 []>, EVEX;
3075}
3076defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3077 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3078defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3079 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3080defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3081 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3082defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3083 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3084defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3085 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3086defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3087 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3088defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3089 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3090defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3091 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3092defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3093 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3094defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3095 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3096defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3097 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3098defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3099 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3100defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3101 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3102defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3103 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3104defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3105 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3106
3107def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3108def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3109def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3110def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3111def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3112
3113def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3114 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3115def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3116 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3117def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3118 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3119def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3120 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3121
3122
3123multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3124 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3125 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3126
3127 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3128 (ins SrcRC:$src),
3129 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3130 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3131 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3132 (ins x86memop:$src),
3133 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3134 [(set DstRC:$dst,
3135 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3136 EVEX;
3137}
3138
3139defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3140 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3141 EVEX_CD8<8, CD8VQ>;
3142defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3143 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3144 EVEX_CD8<8, CD8VO>;
3145defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3146 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3147 EVEX_CD8<16, CD8VH>;
3148defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3149 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3150 EVEX_CD8<16, CD8VQ>;
3151defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3152 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3153 EVEX_CD8<32, CD8VH>;
3154
3155defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3156 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3157 EVEX_CD8<8, CD8VQ>;
3158defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3159 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3160 EVEX_CD8<8, CD8VO>;
3161defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3162 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3163 EVEX_CD8<16, CD8VH>;
3164defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3165 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3166 EVEX_CD8<16, CD8VQ>;
3167defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3168 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3169 EVEX_CD8<32, CD8VH>;
3170
3171//===----------------------------------------------------------------------===//
3172// GATHER - SCATTER Operations
3173
3174multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3175 RegisterClass RC, X86MemOperand memop> {
3176let mayLoad = 1,
3177 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3178 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3179 (ins RC:$src1, KRC:$mask, memop:$src2),
3180 !strconcat(OpcodeStr,
3181 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3182 []>, EVEX, EVEX_K;
3183}
3184defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3185 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3186defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3187 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3188
3189defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3190 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3191defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3192 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3193
3194defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3195 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3196defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3197 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3198
3199defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3200 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3201defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3202 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3203
3204multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3205 RegisterClass RC, X86MemOperand memop> {
3206let mayStore = 1, Constraints = "$mask = $mask_wb" in
3207 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3208 (ins memop:$dst, KRC:$mask, RC:$src2),
3209 !strconcat(OpcodeStr,
3210 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3211 []>, EVEX, EVEX_K;
3212}
3213
3214defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3215 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3216defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3217 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3218
3219defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3220 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3221defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3222 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3223
3224defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3225 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3226defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3227 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3228
3229defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3230 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3231defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3232 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3233
3234//===----------------------------------------------------------------------===//
3235// VSHUFPS - VSHUFPD Operations
3236
3237multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3238 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3239 Domain d> {
3240 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3241 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3242 !strconcat(OpcodeStr,
3243 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3244 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3245 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3246 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3247 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3248 (ins RC:$src1, RC:$src2, i8imm:$src3),
3249 !strconcat(OpcodeStr,
3250 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3251 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3252 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3253 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3254}
3255
3256defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3257 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3258defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3259 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3260
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]3261def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3262 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3263def : Pat<(v16i32 (X86Shufp VR512:$src1,
3264 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3265 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3266
3267def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3268 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3269def : Pat<(v8i64 (X86Shufp VR512:$src1,
3270 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3271 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3272
3273multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3274 X86MemOperand x86memop> {
3275 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3276 (ins RC:$src1, RC:$src2, i8imm:$src3),
3277 !strconcat(OpcodeStr,
3278 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3279 []>, EVEX_4V;
3280 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3281 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3282 !strconcat(OpcodeStr,
3283 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3284 []>, EVEX_4V;
3285}
3286defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3287 EVEX_V512, EVEX_CD8<32, CD8VF>;
3288defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3289 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3290
3291def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3292 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3293def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3294 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3295def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3296 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3297def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3298 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3299
3300multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3301 X86MemOperand x86memop> {
3302 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3303 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3304 EVEX;
3305 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3306 (ins x86memop:$src),
3307 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3308 EVEX;
3309}
3310
3311defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3312 EVEX_CD8<32, CD8VF>;
3313defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3314 EVEX_CD8<64, CD8VF>;
3315