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gerrit-public.fairphone.software / toolchain / llvm-project / dede81ea72a786cdbd88fe8e3ff74865a03d464c / . / llvm / lib / Target / PowerPC / PPCScheduleG4.td
blob: 340773ef787685982cc8c21d07a80e7be2da8db2 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===//
2//
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]7//
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G4 (7400) processor.
11//
12//===----------------------------------------------------------------------===//
13
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]14def G4_BPU : FuncUnit; // Branch unit
15def G4_SLU : FuncUnit; // Store/load unit
16def G4_SRU : FuncUnit; // special register unit
17def G4_IU1 : FuncUnit; // integer unit 1 (simple)
18def G4_IU2 : FuncUnit; // integer unit 2 (complex)
19def G4_FPU1 : FuncUnit; // floating point unit 1
20def G4_VPU : FuncUnit; // vector permutation unit
21def G4_VIU1 : FuncUnit; // vector integer unit 1 (simple)
22def G4_VIU2 : FuncUnit; // vector integer unit 2 (complex)
23def G4_VFPU : FuncUnit; // vector floating point unit
24
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]25def G4Itineraries : ProcessorItineraries<
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]26 [G4_IU1, G4_IU2, G4_SLU, G4_SRU, G4_BPU, G4_FPU1,
27 G4_VIU1, G4_VIU2, G4_VPU, G4_VFPU], [], [
28 InstrItinData<IIC_IntSimple , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
29 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
30 InstrItinData<IIC_IntCompare , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
31 InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>,
32 InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>,
33 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>,
34 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>,
35 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>,
36 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>,
37 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>,
38 InstrItinData<IIC_IntRotate , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
39 InstrItinData<IIC_IntShift , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
40 InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4_IU1, G4_IU2]>]>,
41 InstrItinData<IIC_BrB , [InstrStage<1, [G4_BPU]>]>,
42 InstrItinData<IIC_BrCR , [InstrStage<1, [G4_SRU]>]>,
43 InstrItinData<IIC_BrMCR , [InstrStage<1, [G4_SRU]>]>,
44 InstrItinData<IIC_BrMCRX , [InstrStage<1, [G4_SRU]>]>,
45 InstrItinData<IIC_LdStDCBF , [InstrStage<2, [G4_SLU]>]>,
46 InstrItinData<IIC_LdStDCBI , [InstrStage<2, [G4_SLU]>]>,
47 InstrItinData<IIC_LdStLoad , [InstrStage<2, [G4_SLU]>]>,
48 InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame]49 InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G4_SLU]>]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]50 InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>,
51 InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G4_SLU]>]>,
52 InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>,
53 InstrItinData<IIC_LdStICBI , [InstrStage<2, [G4_SLU]>]>,
54 InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G4_SLU]>]>,
55 InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G4_SLU]>]>,
56 InstrItinData<IIC_LdStLFD , [InstrStage<2, [G4_SLU]>]>,
57 InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G4_SLU]>]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame]58 InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G4_SLU]>]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]59 InstrItinData<IIC_LdStLHA , [InstrStage<2, [G4_SLU]>]>,
60 InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G4_SLU]>]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame]61 InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G4_SLU]>]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]62 InstrItinData<IIC_LdStLMW , [InstrStage<34, [G4_SLU]>]>,
63 InstrItinData<IIC_LdStLVecX , [InstrStage<2, [G4_SLU]>]>,
64 InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4_SLU]>]>,
65 InstrItinData<IIC_LdStSTVEBX , [InstrStage<2, [G4_SLU]>]>,
66 InstrItinData<IIC_LdStSTWCX , [InstrStage<5, [G4_SLU]>]>,
67 InstrItinData<IIC_LdStSync , [InstrStage<8, [G4_SLU]>]>,
68 InstrItinData<IIC_SprISYNC , [InstrStage<2, [G4_SRU]>]>,
69 InstrItinData<IIC_SprMFSR , [InstrStage<3, [G4_SRU]>]>,
70 InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G4_SRU]>]>,
71 InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4_SRU]>]>,
72 InstrItinData<IIC_SprTLBSYNC , [InstrStage<8, [G4_SRU]>]>,
73 InstrItinData<IIC_SprMFCR , [InstrStage<1, [G4_SRU]>]>,
74 InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G4_SRU]>]>,
75 InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G4_SRU]>]>,
76 InstrItinData<IIC_SprMFTB , [InstrStage<1, [G4_SRU]>]>,
77 InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4_SRU]>]>,
78 InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4_SRU]>]>,
79 InstrItinData<IIC_SprRFI , [InstrStage<2, [G4_SRU]>]>,
80 InstrItinData<IIC_SprSC , [InstrStage<2, [G4_SRU]>]>,
81 InstrItinData<IIC_FPGeneral , [InstrStage<1, [G4_FPU1]>]>,
82 InstrItinData<IIC_FPAddSub , [InstrStage<1, [G4_FPU1]>]>,
83 InstrItinData<IIC_FPCompare , [InstrStage<1, [G4_FPU1]>]>,
84 InstrItinData<IIC_FPDivD , [InstrStage<31, [G4_FPU1]>]>,
85 InstrItinData<IIC_FPDivS , [InstrStage<17, [G4_FPU1]>]>,
86 InstrItinData<IIC_FPFused , [InstrStage<1, [G4_FPU1]>]>,
87 InstrItinData<IIC_FPRes , [InstrStage<10, [G4_FPU1]>]>,
88 InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4_VIU1]>]>,
89 InstrItinData<IIC_VecFP , [InstrStage<4, [G4_VFPU]>]>,
90 InstrItinData<IIC_VecFPCompare, [InstrStage<1, [G4_VIU1]>]>,
91 InstrItinData<IIC_VecComplex , [InstrStage<3, [G4_VIU2]>]>,
92 InstrItinData<IIC_VecPerm , [InstrStage<1, [G4_VPU]>]>,
93 InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4_VFPU]>]>,
94 InstrItinData<IIC_VecVSL , [InstrStage<1, [G4_VIU1]>]>,
95 InstrItinData<IIC_VecVSR , [InstrStage<1, [G4_VIU1]>]>
Jim Laskeyc6533002005-10-18 16:23:40 +0000[diff] [blame]96]>;