Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 1 | ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s |
| 2 | |
Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 3 | ; CHECK-LABEL: {{^}}main: |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 4 | ; CHECK: ADD * |
| 5 | |
Nicolai Haehnle | df3a20c | 2016-04-06 19:40:20 +0000 | [diff] [blame^] | 6 | define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) { |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 7 | main_body: |
Vincent Lejeune | f143af3 | 2013-11-11 22:10:24 +0000 | [diff] [blame] | 8 | %0 = extractelement <4 x float> %reg1, i32 0 |
| 9 | %1 = extractelement <4 x float> %reg1, i32 1 |
| 10 | %2 = extractelement <4 x float> %reg1, i32 2 |
| 11 | %3 = extractelement <4 x float> %reg1, i32 3 |
| 12 | %4 = extractelement <4 x float> %reg2, i32 0 |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 13 | %5 = fadd float %0, 2.0 |
| 14 | %6 = fadd float %1, 3.0 |
| 15 | %7 = fadd float %2, 4.0 |
| 16 | %8 = fadd float %3, 5.0 |
| 17 | %9 = bitcast float %4 to i32 |
| 18 | %10 = mul i32 %9, 6 |
| 19 | %11 = bitcast i32 %10 to float |
| 20 | %12 = insertelement <4 x float> undef, float %5, i32 0 |
| 21 | %13 = insertelement <4 x float> %12, float %6, i32 1 |
| 22 | %14 = insertelement <4 x float> %13, float %7, i32 2 |
| 23 | %15 = insertelement <4 x float> %14, float %8, i32 3 |
| 24 | %16 = insertelement <4 x float> %15, float %11, i32 3 |
| 25 | |
| 26 | %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16) |
| 27 | %18 = insertelement <4 x float> undef, float %17, i32 0 |
| 28 | call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) |
| 29 | ret void |
| 30 | } |
| 31 | |
Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 32 | ; CHECK-LABEL: {{^}}main2: |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 33 | ; CHECK-NOT: ADD * |
| 34 | |
Nicolai Haehnle | df3a20c | 2016-04-06 19:40:20 +0000 | [diff] [blame^] | 35 | define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) { |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 36 | main_body: |
Vincent Lejeune | f143af3 | 2013-11-11 22:10:24 +0000 | [diff] [blame] | 37 | %0 = extractelement <4 x float> %reg1, i32 0 |
| 38 | %1 = extractelement <4 x float> %reg1, i32 1 |
| 39 | %2 = extractelement <4 x float> %reg1, i32 2 |
| 40 | %3 = extractelement <4 x float> %reg1, i32 3 |
| 41 | %4 = extractelement <4 x float> %reg2, i32 0 |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 42 | %5 = fadd float %0, 2.0 |
| 43 | %6 = fadd float %1, 3.0 |
| 44 | %7 = fadd float %2, 4.0 |
| 45 | %8 = fadd float %3, 2.0 |
| 46 | %9 = bitcast float %4 to i32 |
| 47 | %10 = mul i32 %9, 6 |
| 48 | %11 = bitcast i32 %10 to float |
| 49 | %12 = insertelement <4 x float> undef, float %5, i32 0 |
| 50 | %13 = insertelement <4 x float> %12, float %6, i32 1 |
| 51 | %14 = insertelement <4 x float> %13, float %7, i32 2 |
| 52 | %15 = insertelement <4 x float> %14, float %8, i32 3 |
| 53 | %16 = insertelement <4 x float> %15, float %11, i32 3 |
| 54 | |
| 55 | %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16) |
| 56 | %18 = insertelement <4 x float> undef, float %17, i32 0 |
| 57 | call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) |
| 58 | ret void |
| 59 | } |
| 60 | |
| 61 | ; Function Attrs: readnone |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 62 | declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 |
| 63 | |
| 64 | declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) |
| 65 | |
Vincent Lejeune | bb3f931 | 2013-07-31 19:32:07 +0000 | [diff] [blame] | 66 | attributes #1 = { readnone } |