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gerrit-public.fairphone.software / toolchain / llvm-project / e3dcce9700c6f7045774f46f66faa610081495a5 / . / llvm / lib / Target / NVPTX / NVPTXISelDAGToDAG.cpp
blob: 1d233c453b491389a1fab2c80c807fb9f3d5c56b [file] [log] [blame]
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1//===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the NVPTX target.
11//
12//===----------------------------------------------------------------------===//
13
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]14#include "NVPTXISelDAGToDAG.h"
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]15#include "llvm/Analysis/ValueTracking.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]16#include "llvm/IR/GlobalValue.h"
17#include "llvm/IR/Instructions.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]18#include "llvm/Support/CommandLine.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]19#include "llvm/Support/Debug.h"
20#include "llvm/Support/ErrorHandling.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/Support/raw_ostream.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]22#include "llvm/Target/TargetIntrinsicInfo.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]23
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]24using namespace llvm;
25
Chandler Carruth84e68b22014-04-22 02:41:26 +0000[diff] [blame]26#define DEBUG_TYPE "nvptx-isel"
27
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]28static cl::opt<int> UsePrecDivF32(
Nadav Rotem7f27e0b2013-10-18 23:38:13 +0000[diff] [blame]29 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]30 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
Sylvestre Ledru469de192014-08-11 18:04:46 +0000[diff] [blame]31 " IEEE Compliant F32 div.rnd if available."),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]32 cl::init(2));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]33
Justin Holewinski48f4ad32013-05-21 16:51:30 +0000[diff] [blame]34static cl::opt<bool>
Nadav Rotem7f27e0b2013-10-18 23:38:13 +0000[diff] [blame]35UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
Justin Holewinski48f4ad32013-05-21 16:51:30 +0000[diff] [blame]36 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
37 cl::init(true));
38
Justin Holewinskicd069e62013-07-22 12:18:04 +0000[diff] [blame]39static cl::opt<bool>
Nadav Rotem7f27e0b2013-10-18 23:38:13 +0000[diff] [blame]40FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
Justin Holewinskicd069e62013-07-22 12:18:04 +0000[diff] [blame]41 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
42 cl::init(false));
43
44
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]45/// createNVPTXISelDag - This pass converts a legalized DAG into a
46/// NVPTX-specific DAG, ready for instruction scheduling.
47FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
48 llvm::CodeGenOpt::Level OptLevel) {
49 return new NVPTXDAGToDAGISel(TM, OptLevel);
50}
51
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]52NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
53 CodeGenOpt::Level OptLevel)
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]54 : SelectionDAGISel(tm, OptLevel), TM(tm) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]55 doMulWide = (OptLevel > 0);
Justin Holewinskicd069e62013-07-22 12:18:04 +0000[diff] [blame]56}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]57
Eric Christopher147bba22015-01-30 01:40:59 +0000[diff] [blame]58bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
59 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
60 return SelectionDAGISel::runOnMachineFunction(MF);
61}
62
Justin Holewinskicd069e62013-07-22 12:18:04 +0000[diff] [blame]63int NVPTXDAGToDAGISel::getDivF32Level() const {
64 if (UsePrecDivF32.getNumOccurrences() > 0) {
65 // If nvptx-prec-div32=N is used on the command-line, always honor it
66 return UsePrecDivF32;
67 } else {
68 // Otherwise, use div.approx if fast math is enabled
69 if (TM.Options.UnsafeFPMath)
70 return 0;
71 else
72 return 2;
73 }
74}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]75
Justin Holewinskicd069e62013-07-22 12:18:04 +0000[diff] [blame]76bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
77 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
78 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
79 return UsePrecSqrtF32;
80 } else {
81 // Otherwise, use sqrt.approx if fast math is enabled
Eli Bendersky3e840192015-03-23 16:26:23 +0000[diff] [blame]82 return !TM.Options.UnsafeFPMath;
Justin Holewinskicd069e62013-07-22 12:18:04 +0000[diff] [blame]83 }
84}
85
86bool NVPTXDAGToDAGISel::useF32FTZ() const {
87 if (FtzEnabled.getNumOccurrences() > 0) {
88 // If nvptx-f32ftz is used on the command-line, always honor it
89 return FtzEnabled;
90 } else {
91 const Function *F = MF->getFunction();
92 // Otherwise, check for an nvptx-f32ftz attribute on the function
93 if (F->hasFnAttribute("nvptx-f32ftz"))
Duncan P. N. Exon Smithb5054332015-02-14 15:35:43 +0000[diff] [blame]94 return F->getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
Justin Holewinskicd069e62013-07-22 12:18:04 +0000[diff] [blame]95 else
96 return false;
97 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]98}
99
Justin Holewinski428cf0e2014-07-17 18:10:09 +0000[diff] [blame]100bool NVPTXDAGToDAGISel::allowFMA() const {
Eric Christopher147bba22015-01-30 01:40:59 +0000[diff] [blame]101 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
Justin Holewinski428cf0e2014-07-17 18:10:09 +0000[diff] [blame]102 return TL->allowFMA(*MF, OptLevel);
103}
104
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]105/// Select - Select instructions not customized! Used for
106/// expanded, promoted and normal instructions.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]107SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]108
Tim Northover31d093c2013-09-22 08:21:56 +0000[diff] [blame]109 if (N->isMachineOpcode()) {
110 N->setNodeId(-1);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]111 return nullptr; // Already selected.
Tim Northover31d093c2013-09-22 08:21:56 +0000[diff] [blame]112 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]113
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]114 SDNode *ResNode = nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]115 switch (N->getOpcode()) {
116 case ISD::LOAD:
117 ResNode = SelectLoad(N);
118 break;
119 case ISD::STORE:
120 ResNode = SelectStore(N);
121 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]122 case NVPTXISD::LoadV2:
123 case NVPTXISD::LoadV4:
124 ResNode = SelectLoadVector(N);
125 break;
126 case NVPTXISD::LDGV2:
127 case NVPTXISD::LDGV4:
128 case NVPTXISD::LDUV2:
129 case NVPTXISD::LDUV4:
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]130 ResNode = SelectLDGLDU(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]131 break;
132 case NVPTXISD::StoreV2:
133 case NVPTXISD::StoreV4:
134 ResNode = SelectStoreVector(N);
135 break;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]136 case NVPTXISD::LoadParam:
137 case NVPTXISD::LoadParamV2:
138 case NVPTXISD::LoadParamV4:
139 ResNode = SelectLoadParam(N);
140 break;
141 case NVPTXISD::StoreRetval:
142 case NVPTXISD::StoreRetvalV2:
143 case NVPTXISD::StoreRetvalV4:
144 ResNode = SelectStoreRetval(N);
145 break;
146 case NVPTXISD::StoreParam:
147 case NVPTXISD::StoreParamV2:
148 case NVPTXISD::StoreParamV4:
149 case NVPTXISD::StoreParamS32:
150 case NVPTXISD::StoreParamU32:
151 ResNode = SelectStoreParam(N);
152 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]153 case ISD::INTRINSIC_WO_CHAIN:
154 ResNode = SelectIntrinsicNoChain(N);
155 break;
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]156 case ISD::INTRINSIC_W_CHAIN:
157 ResNode = SelectIntrinsicChain(N);
158 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]159 case NVPTXISD::Tex1DFloatS32:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]160 case NVPTXISD::Tex1DFloatFloat:
161 case NVPTXISD::Tex1DFloatFloatLevel:
162 case NVPTXISD::Tex1DFloatFloatGrad:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]163 case NVPTXISD::Tex1DS32S32:
164 case NVPTXISD::Tex1DS32Float:
165 case NVPTXISD::Tex1DS32FloatLevel:
166 case NVPTXISD::Tex1DS32FloatGrad:
167 case NVPTXISD::Tex1DU32S32:
168 case NVPTXISD::Tex1DU32Float:
169 case NVPTXISD::Tex1DU32FloatLevel:
170 case NVPTXISD::Tex1DU32FloatGrad:
171 case NVPTXISD::Tex1DArrayFloatS32:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]172 case NVPTXISD::Tex1DArrayFloatFloat:
173 case NVPTXISD::Tex1DArrayFloatFloatLevel:
174 case NVPTXISD::Tex1DArrayFloatFloatGrad:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]175 case NVPTXISD::Tex1DArrayS32S32:
176 case NVPTXISD::Tex1DArrayS32Float:
177 case NVPTXISD::Tex1DArrayS32FloatLevel:
178 case NVPTXISD::Tex1DArrayS32FloatGrad:
179 case NVPTXISD::Tex1DArrayU32S32:
180 case NVPTXISD::Tex1DArrayU32Float:
181 case NVPTXISD::Tex1DArrayU32FloatLevel:
182 case NVPTXISD::Tex1DArrayU32FloatGrad:
183 case NVPTXISD::Tex2DFloatS32:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]184 case NVPTXISD::Tex2DFloatFloat:
185 case NVPTXISD::Tex2DFloatFloatLevel:
186 case NVPTXISD::Tex2DFloatFloatGrad:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]187 case NVPTXISD::Tex2DS32S32:
188 case NVPTXISD::Tex2DS32Float:
189 case NVPTXISD::Tex2DS32FloatLevel:
190 case NVPTXISD::Tex2DS32FloatGrad:
191 case NVPTXISD::Tex2DU32S32:
192 case NVPTXISD::Tex2DU32Float:
193 case NVPTXISD::Tex2DU32FloatLevel:
194 case NVPTXISD::Tex2DU32FloatGrad:
195 case NVPTXISD::Tex2DArrayFloatS32:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]196 case NVPTXISD::Tex2DArrayFloatFloat:
197 case NVPTXISD::Tex2DArrayFloatFloatLevel:
198 case NVPTXISD::Tex2DArrayFloatFloatGrad:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]199 case NVPTXISD::Tex2DArrayS32S32:
200 case NVPTXISD::Tex2DArrayS32Float:
201 case NVPTXISD::Tex2DArrayS32FloatLevel:
202 case NVPTXISD::Tex2DArrayS32FloatGrad:
203 case NVPTXISD::Tex2DArrayU32S32:
204 case NVPTXISD::Tex2DArrayU32Float:
205 case NVPTXISD::Tex2DArrayU32FloatLevel:
206 case NVPTXISD::Tex2DArrayU32FloatGrad:
207 case NVPTXISD::Tex3DFloatS32:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]208 case NVPTXISD::Tex3DFloatFloat:
209 case NVPTXISD::Tex3DFloatFloatLevel:
210 case NVPTXISD::Tex3DFloatFloatGrad:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]211 case NVPTXISD::Tex3DS32S32:
212 case NVPTXISD::Tex3DS32Float:
213 case NVPTXISD::Tex3DS32FloatLevel:
214 case NVPTXISD::Tex3DS32FloatGrad:
215 case NVPTXISD::Tex3DU32S32:
216 case NVPTXISD::Tex3DU32Float:
217 case NVPTXISD::Tex3DU32FloatLevel:
218 case NVPTXISD::Tex3DU32FloatGrad:
219 case NVPTXISD::TexCubeFloatFloat:
220 case NVPTXISD::TexCubeFloatFloatLevel:
221 case NVPTXISD::TexCubeS32Float:
222 case NVPTXISD::TexCubeS32FloatLevel:
223 case NVPTXISD::TexCubeU32Float:
224 case NVPTXISD::TexCubeU32FloatLevel:
225 case NVPTXISD::TexCubeArrayFloatFloat:
226 case NVPTXISD::TexCubeArrayFloatFloatLevel:
227 case NVPTXISD::TexCubeArrayS32Float:
228 case NVPTXISD::TexCubeArrayS32FloatLevel:
229 case NVPTXISD::TexCubeArrayU32Float:
230 case NVPTXISD::TexCubeArrayU32FloatLevel:
231 case NVPTXISD::Tld4R2DFloatFloat:
232 case NVPTXISD::Tld4G2DFloatFloat:
233 case NVPTXISD::Tld4B2DFloatFloat:
234 case NVPTXISD::Tld4A2DFloatFloat:
235 case NVPTXISD::Tld4R2DS64Float:
236 case NVPTXISD::Tld4G2DS64Float:
237 case NVPTXISD::Tld4B2DS64Float:
238 case NVPTXISD::Tld4A2DS64Float:
239 case NVPTXISD::Tld4R2DU64Float:
240 case NVPTXISD::Tld4G2DU64Float:
241 case NVPTXISD::Tld4B2DU64Float:
242 case NVPTXISD::Tld4A2DU64Float:
243 case NVPTXISD::TexUnified1DFloatS32:
244 case NVPTXISD::TexUnified1DFloatFloat:
245 case NVPTXISD::TexUnified1DFloatFloatLevel:
246 case NVPTXISD::TexUnified1DFloatFloatGrad:
247 case NVPTXISD::TexUnified1DS32S32:
248 case NVPTXISD::TexUnified1DS32Float:
249 case NVPTXISD::TexUnified1DS32FloatLevel:
250 case NVPTXISD::TexUnified1DS32FloatGrad:
251 case NVPTXISD::TexUnified1DU32S32:
252 case NVPTXISD::TexUnified1DU32Float:
253 case NVPTXISD::TexUnified1DU32FloatLevel:
254 case NVPTXISD::TexUnified1DU32FloatGrad:
255 case NVPTXISD::TexUnified1DArrayFloatS32:
256 case NVPTXISD::TexUnified1DArrayFloatFloat:
257 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
258 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
259 case NVPTXISD::TexUnified1DArrayS32S32:
260 case NVPTXISD::TexUnified1DArrayS32Float:
261 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
262 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
263 case NVPTXISD::TexUnified1DArrayU32S32:
264 case NVPTXISD::TexUnified1DArrayU32Float:
265 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
266 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
267 case NVPTXISD::TexUnified2DFloatS32:
268 case NVPTXISD::TexUnified2DFloatFloat:
269 case NVPTXISD::TexUnified2DFloatFloatLevel:
270 case NVPTXISD::TexUnified2DFloatFloatGrad:
271 case NVPTXISD::TexUnified2DS32S32:
272 case NVPTXISD::TexUnified2DS32Float:
273 case NVPTXISD::TexUnified2DS32FloatLevel:
274 case NVPTXISD::TexUnified2DS32FloatGrad:
275 case NVPTXISD::TexUnified2DU32S32:
276 case NVPTXISD::TexUnified2DU32Float:
277 case NVPTXISD::TexUnified2DU32FloatLevel:
278 case NVPTXISD::TexUnified2DU32FloatGrad:
279 case NVPTXISD::TexUnified2DArrayFloatS32:
280 case NVPTXISD::TexUnified2DArrayFloatFloat:
281 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
282 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
283 case NVPTXISD::TexUnified2DArrayS32S32:
284 case NVPTXISD::TexUnified2DArrayS32Float:
285 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
286 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
287 case NVPTXISD::TexUnified2DArrayU32S32:
288 case NVPTXISD::TexUnified2DArrayU32Float:
289 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
290 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
291 case NVPTXISD::TexUnified3DFloatS32:
292 case NVPTXISD::TexUnified3DFloatFloat:
293 case NVPTXISD::TexUnified3DFloatFloatLevel:
294 case NVPTXISD::TexUnified3DFloatFloatGrad:
295 case NVPTXISD::TexUnified3DS32S32:
296 case NVPTXISD::TexUnified3DS32Float:
297 case NVPTXISD::TexUnified3DS32FloatLevel:
298 case NVPTXISD::TexUnified3DS32FloatGrad:
299 case NVPTXISD::TexUnified3DU32S32:
300 case NVPTXISD::TexUnified3DU32Float:
301 case NVPTXISD::TexUnified3DU32FloatLevel:
302 case NVPTXISD::TexUnified3DU32FloatGrad:
303 case NVPTXISD::TexUnifiedCubeFloatFloat:
304 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
305 case NVPTXISD::TexUnifiedCubeS32Float:
306 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
307 case NVPTXISD::TexUnifiedCubeU32Float:
308 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
309 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
310 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
311 case NVPTXISD::TexUnifiedCubeArrayS32Float:
312 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
313 case NVPTXISD::TexUnifiedCubeArrayU32Float:
314 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
315 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
316 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
317 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
318 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
319 case NVPTXISD::Tld4UnifiedR2DS64Float:
320 case NVPTXISD::Tld4UnifiedG2DS64Float:
321 case NVPTXISD::Tld4UnifiedB2DS64Float:
322 case NVPTXISD::Tld4UnifiedA2DS64Float:
323 case NVPTXISD::Tld4UnifiedR2DU64Float:
324 case NVPTXISD::Tld4UnifiedG2DU64Float:
325 case NVPTXISD::Tld4UnifiedB2DU64Float:
326 case NVPTXISD::Tld4UnifiedA2DU64Float:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]327 ResNode = SelectTextureIntrinsic(N);
328 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]329 case NVPTXISD::Suld1DI8Clamp:
330 case NVPTXISD::Suld1DI16Clamp:
331 case NVPTXISD::Suld1DI32Clamp:
332 case NVPTXISD::Suld1DI64Clamp:
333 case NVPTXISD::Suld1DV2I8Clamp:
334 case NVPTXISD::Suld1DV2I16Clamp:
335 case NVPTXISD::Suld1DV2I32Clamp:
336 case NVPTXISD::Suld1DV2I64Clamp:
337 case NVPTXISD::Suld1DV4I8Clamp:
338 case NVPTXISD::Suld1DV4I16Clamp:
339 case NVPTXISD::Suld1DV4I32Clamp:
340 case NVPTXISD::Suld1DArrayI8Clamp:
341 case NVPTXISD::Suld1DArrayI16Clamp:
342 case NVPTXISD::Suld1DArrayI32Clamp:
343 case NVPTXISD::Suld1DArrayI64Clamp:
344 case NVPTXISD::Suld1DArrayV2I8Clamp:
345 case NVPTXISD::Suld1DArrayV2I16Clamp:
346 case NVPTXISD::Suld1DArrayV2I32Clamp:
347 case NVPTXISD::Suld1DArrayV2I64Clamp:
348 case NVPTXISD::Suld1DArrayV4I8Clamp:
349 case NVPTXISD::Suld1DArrayV4I16Clamp:
350 case NVPTXISD::Suld1DArrayV4I32Clamp:
351 case NVPTXISD::Suld2DI8Clamp:
352 case NVPTXISD::Suld2DI16Clamp:
353 case NVPTXISD::Suld2DI32Clamp:
354 case NVPTXISD::Suld2DI64Clamp:
355 case NVPTXISD::Suld2DV2I8Clamp:
356 case NVPTXISD::Suld2DV2I16Clamp:
357 case NVPTXISD::Suld2DV2I32Clamp:
358 case NVPTXISD::Suld2DV2I64Clamp:
359 case NVPTXISD::Suld2DV4I8Clamp:
360 case NVPTXISD::Suld2DV4I16Clamp:
361 case NVPTXISD::Suld2DV4I32Clamp:
362 case NVPTXISD::Suld2DArrayI8Clamp:
363 case NVPTXISD::Suld2DArrayI16Clamp:
364 case NVPTXISD::Suld2DArrayI32Clamp:
365 case NVPTXISD::Suld2DArrayI64Clamp:
366 case NVPTXISD::Suld2DArrayV2I8Clamp:
367 case NVPTXISD::Suld2DArrayV2I16Clamp:
368 case NVPTXISD::Suld2DArrayV2I32Clamp:
369 case NVPTXISD::Suld2DArrayV2I64Clamp:
370 case NVPTXISD::Suld2DArrayV4I8Clamp:
371 case NVPTXISD::Suld2DArrayV4I16Clamp:
372 case NVPTXISD::Suld2DArrayV4I32Clamp:
373 case NVPTXISD::Suld3DI8Clamp:
374 case NVPTXISD::Suld3DI16Clamp:
375 case NVPTXISD::Suld3DI32Clamp:
376 case NVPTXISD::Suld3DI64Clamp:
377 case NVPTXISD::Suld3DV2I8Clamp:
378 case NVPTXISD::Suld3DV2I16Clamp:
379 case NVPTXISD::Suld3DV2I32Clamp:
380 case NVPTXISD::Suld3DV2I64Clamp:
381 case NVPTXISD::Suld3DV4I8Clamp:
382 case NVPTXISD::Suld3DV4I16Clamp:
383 case NVPTXISD::Suld3DV4I32Clamp:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]384 case NVPTXISD::Suld1DI8Trap:
385 case NVPTXISD::Suld1DI16Trap:
386 case NVPTXISD::Suld1DI32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]387 case NVPTXISD::Suld1DI64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]388 case NVPTXISD::Suld1DV2I8Trap:
389 case NVPTXISD::Suld1DV2I16Trap:
390 case NVPTXISD::Suld1DV2I32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]391 case NVPTXISD::Suld1DV2I64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]392 case NVPTXISD::Suld1DV4I8Trap:
393 case NVPTXISD::Suld1DV4I16Trap:
394 case NVPTXISD::Suld1DV4I32Trap:
395 case NVPTXISD::Suld1DArrayI8Trap:
396 case NVPTXISD::Suld1DArrayI16Trap:
397 case NVPTXISD::Suld1DArrayI32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]398 case NVPTXISD::Suld1DArrayI64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]399 case NVPTXISD::Suld1DArrayV2I8Trap:
400 case NVPTXISD::Suld1DArrayV2I16Trap:
401 case NVPTXISD::Suld1DArrayV2I32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]402 case NVPTXISD::Suld1DArrayV2I64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]403 case NVPTXISD::Suld1DArrayV4I8Trap:
404 case NVPTXISD::Suld1DArrayV4I16Trap:
405 case NVPTXISD::Suld1DArrayV4I32Trap:
406 case NVPTXISD::Suld2DI8Trap:
407 case NVPTXISD::Suld2DI16Trap:
408 case NVPTXISD::Suld2DI32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]409 case NVPTXISD::Suld2DI64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]410 case NVPTXISD::Suld2DV2I8Trap:
411 case NVPTXISD::Suld2DV2I16Trap:
412 case NVPTXISD::Suld2DV2I32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]413 case NVPTXISD::Suld2DV2I64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]414 case NVPTXISD::Suld2DV4I8Trap:
415 case NVPTXISD::Suld2DV4I16Trap:
416 case NVPTXISD::Suld2DV4I32Trap:
417 case NVPTXISD::Suld2DArrayI8Trap:
418 case NVPTXISD::Suld2DArrayI16Trap:
419 case NVPTXISD::Suld2DArrayI32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]420 case NVPTXISD::Suld2DArrayI64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]421 case NVPTXISD::Suld2DArrayV2I8Trap:
422 case NVPTXISD::Suld2DArrayV2I16Trap:
423 case NVPTXISD::Suld2DArrayV2I32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]424 case NVPTXISD::Suld2DArrayV2I64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]425 case NVPTXISD::Suld2DArrayV4I8Trap:
426 case NVPTXISD::Suld2DArrayV4I16Trap:
427 case NVPTXISD::Suld2DArrayV4I32Trap:
428 case NVPTXISD::Suld3DI8Trap:
429 case NVPTXISD::Suld3DI16Trap:
430 case NVPTXISD::Suld3DI32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]431 case NVPTXISD::Suld3DI64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]432 case NVPTXISD::Suld3DV2I8Trap:
433 case NVPTXISD::Suld3DV2I16Trap:
434 case NVPTXISD::Suld3DV2I32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]435 case NVPTXISD::Suld3DV2I64Trap:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]436 case NVPTXISD::Suld3DV4I8Trap:
437 case NVPTXISD::Suld3DV4I16Trap:
438 case NVPTXISD::Suld3DV4I32Trap:
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]439 case NVPTXISD::Suld1DI8Zero:
440 case NVPTXISD::Suld1DI16Zero:
441 case NVPTXISD::Suld1DI32Zero:
442 case NVPTXISD::Suld1DI64Zero:
443 case NVPTXISD::Suld1DV2I8Zero:
444 case NVPTXISD::Suld1DV2I16Zero:
445 case NVPTXISD::Suld1DV2I32Zero:
446 case NVPTXISD::Suld1DV2I64Zero:
447 case NVPTXISD::Suld1DV4I8Zero:
448 case NVPTXISD::Suld1DV4I16Zero:
449 case NVPTXISD::Suld1DV4I32Zero:
450 case NVPTXISD::Suld1DArrayI8Zero:
451 case NVPTXISD::Suld1DArrayI16Zero:
452 case NVPTXISD::Suld1DArrayI32Zero:
453 case NVPTXISD::Suld1DArrayI64Zero:
454 case NVPTXISD::Suld1DArrayV2I8Zero:
455 case NVPTXISD::Suld1DArrayV2I16Zero:
456 case NVPTXISD::Suld1DArrayV2I32Zero:
457 case NVPTXISD::Suld1DArrayV2I64Zero:
458 case NVPTXISD::Suld1DArrayV4I8Zero:
459 case NVPTXISD::Suld1DArrayV4I16Zero:
460 case NVPTXISD::Suld1DArrayV4I32Zero:
461 case NVPTXISD::Suld2DI8Zero:
462 case NVPTXISD::Suld2DI16Zero:
463 case NVPTXISD::Suld2DI32Zero:
464 case NVPTXISD::Suld2DI64Zero:
465 case NVPTXISD::Suld2DV2I8Zero:
466 case NVPTXISD::Suld2DV2I16Zero:
467 case NVPTXISD::Suld2DV2I32Zero:
468 case NVPTXISD::Suld2DV2I64Zero:
469 case NVPTXISD::Suld2DV4I8Zero:
470 case NVPTXISD::Suld2DV4I16Zero:
471 case NVPTXISD::Suld2DV4I32Zero:
472 case NVPTXISD::Suld2DArrayI8Zero:
473 case NVPTXISD::Suld2DArrayI16Zero:
474 case NVPTXISD::Suld2DArrayI32Zero:
475 case NVPTXISD::Suld2DArrayI64Zero:
476 case NVPTXISD::Suld2DArrayV2I8Zero:
477 case NVPTXISD::Suld2DArrayV2I16Zero:
478 case NVPTXISD::Suld2DArrayV2I32Zero:
479 case NVPTXISD::Suld2DArrayV2I64Zero:
480 case NVPTXISD::Suld2DArrayV4I8Zero:
481 case NVPTXISD::Suld2DArrayV4I16Zero:
482 case NVPTXISD::Suld2DArrayV4I32Zero:
483 case NVPTXISD::Suld3DI8Zero:
484 case NVPTXISD::Suld3DI16Zero:
485 case NVPTXISD::Suld3DI32Zero:
486 case NVPTXISD::Suld3DI64Zero:
487 case NVPTXISD::Suld3DV2I8Zero:
488 case NVPTXISD::Suld3DV2I16Zero:
489 case NVPTXISD::Suld3DV2I32Zero:
490 case NVPTXISD::Suld3DV2I64Zero:
491 case NVPTXISD::Suld3DV4I8Zero:
492 case NVPTXISD::Suld3DV4I16Zero:
493 case NVPTXISD::Suld3DV4I32Zero:
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]494 ResNode = SelectSurfaceIntrinsic(N);
495 break;
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]496 case ISD::AND:
497 case ISD::SRA:
498 case ISD::SRL:
499 // Try to select BFE
500 ResNode = SelectBFE(N);
501 break;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]502 case ISD::ADDRSPACECAST:
503 ResNode = SelectAddrSpaceCast(N);
504 break;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]505 default:
506 break;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]507 }
508 if (ResNode)
509 return ResNode;
510 return SelectCode(N);
511}
512
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]513SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) {
514 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
515 switch (IID) {
516 default:
517 return NULL;
518 case Intrinsic::nvvm_ldg_global_f:
519 case Intrinsic::nvvm_ldg_global_i:
520 case Intrinsic::nvvm_ldg_global_p:
521 case Intrinsic::nvvm_ldu_global_f:
522 case Intrinsic::nvvm_ldu_global_i:
523 case Intrinsic::nvvm_ldu_global_p:
524 return SelectLDGLDU(N);
525 }
526}
527
Eric Christopher9745b3a2015-01-30 01:41:01 +0000[diff] [blame]528static unsigned int getCodeAddrSpace(MemSDNode *N) {
Nick Lewyckyaad475b2014-04-15 07:22:52 +0000[diff] [blame]529 const Value *Src = N->getMemOperand()->getValue();
Justin Holewinskib96d1392013-06-10 13:29:47 +0000[diff] [blame]530
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]531 if (!Src)
Justin Holewinskib96d1392013-06-10 13:29:47 +0000[diff] [blame]532 return NVPTX::PTXLdStInstCode::GENERIC;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]533
Craig Toppere3dcce92015-08-01 22:20:21 +0000[diff] [blame^]534 if (auto *PT = dyn_cast<PointerType>(Src->getType())) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]535 switch (PT->getAddressSpace()) {
Justin Holewinskib96d1392013-06-10 13:29:47 +0000[diff] [blame]536 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
537 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
538 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
539 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
540 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
541 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
542 default: break;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]543 }
544 }
Justin Holewinskib96d1392013-06-10 13:29:47 +0000[diff] [blame]545 return NVPTX::PTXLdStInstCode::GENERIC;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]546}
547
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]548static bool canLowerToLDG(MemSDNode *N, const NVPTXSubtarget &Subtarget,
549 unsigned codeAddrSpace, const DataLayout &DL) {
550 if (!Subtarget.hasLDG() || codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL) {
551 return false;
552 }
553
554 // Check whether load operates on a readonly argument.
555 bool canUseLDG = false;
556 if (const Argument *A = dyn_cast<const Argument>(
557 GetUnderlyingObject(N->getMemOperand()->getValue(), DL)))
558 canUseLDG = A->onlyReadsMemory() && A->hasNoAliasAttr();
559
560 return canUseLDG;
561}
562
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]563SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
564 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
565 switch (IID) {
566 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]567 return nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]568 case Intrinsic::nvvm_texsurf_handle_internal:
569 return SelectTexSurfHandle(N);
570 }
571}
572
573SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
574 // Op 0 is the intrinsic ID
575 SDValue Wrapper = N->getOperand(1);
576 SDValue GlobalVal = Wrapper.getOperand(0);
577 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
578 GlobalVal);
579}
580
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]581SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
582 SDValue Src = N->getOperand(0);
583 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
584 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
585 unsigned DstAddrSpace = CastN->getDestAddressSpace();
586
587 assert(SrcAddrSpace != DstAddrSpace &&
588 "addrspacecast must be between different address spaces");
589
590 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
591 // Specific to generic
592 unsigned Opc;
593 switch (SrcAddrSpace) {
594 default: report_fatal_error("Bad address space in addrspacecast");
595 case ADDRESS_SPACE_GLOBAL:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]596 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]597 break;
598 case ADDRESS_SPACE_SHARED:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]599 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]600 break;
601 case ADDRESS_SPACE_CONST:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]602 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]603 break;
604 case ADDRESS_SPACE_LOCAL:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]605 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]606 break;
607 }
608 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
609 } else {
610 // Generic to specific
611 if (SrcAddrSpace != 0)
612 report_fatal_error("Cannot cast between two non-generic address spaces");
613 unsigned Opc;
614 switch (DstAddrSpace) {
615 default: report_fatal_error("Bad address space in addrspacecast");
616 case ADDRESS_SPACE_GLOBAL:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]617 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
618 : NVPTX::cvta_to_global_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]619 break;
620 case ADDRESS_SPACE_SHARED:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]621 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
622 : NVPTX::cvta_to_shared_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]623 break;
624 case ADDRESS_SPACE_CONST:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]625 Opc =
626 TM.is64Bit() ? NVPTX::cvta_to_const_yes_64 : NVPTX::cvta_to_const_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]627 break;
628 case ADDRESS_SPACE_LOCAL:
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]629 Opc =
630 TM.is64Bit() ? NVPTX::cvta_to_local_yes_64 : NVPTX::cvta_to_local_yes;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]631 break;
Jingyue Wua2f60272015-06-04 21:28:26 +0000[diff] [blame]632 case ADDRESS_SPACE_PARAM:
633 Opc = TM.is64Bit() ? NVPTX::nvvm_ptr_gen_to_param_64
634 : NVPTX::nvvm_ptr_gen_to_param;
635 break;
Justin Holewinskiba2fa6d2014-03-24 11:17:53 +0000[diff] [blame]636 }
637 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
638 }
639}
640
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]641SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]642 SDLoc dl(N);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]643 LoadSDNode *LD = cast<LoadSDNode>(N);
644 EVT LoadedVT = LD->getMemoryVT();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]645 SDNode *NVPTXLD = nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]646
647 // do not support pre/post inc/dec
648 if (LD->isIndexed())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]649 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]650
651 if (!LoadedVT.isSimple())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]652 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]653
654 // Address Space Setting
Eric Christopher9745b3a2015-01-30 01:41:01 +0000[diff] [blame]655 unsigned int codeAddrSpace = getCodeAddrSpace(LD);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]656
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]657 if (canLowerToLDG(LD, *Subtarget, codeAddrSpace, CurDAG->getDataLayout())) {
658 return SelectLDGLDU(N);
659 }
660
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]661 // Volatile Setting
662 // - .volatile is only availalble for .global and .shared
663 bool isVolatile = LD->isVolatile();
664 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
665 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
666 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
667 isVolatile = false;
668
669 // Vector Setting
670 MVT SimpleVT = LoadedVT.getSimpleVT();
671 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
672 if (SimpleVT.isVector()) {
673 unsigned num = SimpleVT.getVectorNumElements();
674 if (num == 2)
675 vecType = NVPTX::PTXLdStInstCode::V2;
676 else if (num == 4)
677 vecType = NVPTX::PTXLdStInstCode::V4;
678 else
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]679 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]680 }
681
682 // Type Setting: fromType + fromTypeWidth
683 //
684 // Sign : ISD::SEXTLOAD
685 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
686 // type is integer
687 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
688 MVT ScalarVT = SimpleVT.getScalarType();
Justin Holewinski994d66a2013-05-30 12:22:39 +0000[diff] [blame]689 // Read at least 8 bits (predicates are stored as 8-bit values)
690 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]691 unsigned int fromType;
692 if ((LD->getExtensionType() == ISD::SEXTLOAD))
693 fromType = NVPTX::PTXLdStInstCode::Signed;
694 else if (ScalarVT.isFloatingPoint())
695 fromType = NVPTX::PTXLdStInstCode::Float;
696 else
697 fromType = NVPTX::PTXLdStInstCode::Unsigned;
698
699 // Create the machine instruction DAG
700 SDValue Chain = N->getOperand(0);
701 SDValue N1 = N->getOperand(1);
702 SDValue Addr;
703 SDValue Offset, Base;
704 unsigned Opcode;
Craig Topperd9c27832013-08-15 02:44:19 +0000[diff] [blame]705 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]706
707 if (SelectDirectAddr(N1, Addr)) {
708 switch (TargetVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]709 case MVT::i8:
710 Opcode = NVPTX::LD_i8_avar;
711 break;
712 case MVT::i16:
713 Opcode = NVPTX::LD_i16_avar;
714 break;
715 case MVT::i32:
716 Opcode = NVPTX::LD_i32_avar;
717 break;
718 case MVT::i64:
719 Opcode = NVPTX::LD_i64_avar;
720 break;
721 case MVT::f32:
722 Opcode = NVPTX::LD_f32_avar;
723 break;
724 case MVT::f64:
725 Opcode = NVPTX::LD_f64_avar;
726 break;
727 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]728 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]729 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]730 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
731 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
732 getI32Imm(fromTypeWidth, dl), Addr, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]733 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]734 } else if (TM.is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
735 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]736 switch (TargetVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]737 case MVT::i8:
738 Opcode = NVPTX::LD_i8_asi;
739 break;
740 case MVT::i16:
741 Opcode = NVPTX::LD_i16_asi;
742 break;
743 case MVT::i32:
744 Opcode = NVPTX::LD_i32_asi;
745 break;
746 case MVT::i64:
747 Opcode = NVPTX::LD_i64_asi;
748 break;
749 case MVT::f32:
750 Opcode = NVPTX::LD_f32_asi;
751 break;
752 case MVT::f64:
753 Opcode = NVPTX::LD_f64_asi;
754 break;
755 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]756 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]757 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]758 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
759 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
760 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]761 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]762 } else if (TM.is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
763 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
764 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]765 switch (TargetVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]766 case MVT::i8:
767 Opcode = NVPTX::LD_i8_ari_64;
768 break;
769 case MVT::i16:
770 Opcode = NVPTX::LD_i16_ari_64;
771 break;
772 case MVT::i32:
773 Opcode = NVPTX::LD_i32_ari_64;
774 break;
775 case MVT::i64:
776 Opcode = NVPTX::LD_i64_ari_64;
777 break;
778 case MVT::f32:
779 Opcode = NVPTX::LD_f32_ari_64;
780 break;
781 case MVT::f64:
782 Opcode = NVPTX::LD_f64_ari_64;
783 break;
784 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]785 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]786 }
787 } else {
788 switch (TargetVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]789 case MVT::i8:
790 Opcode = NVPTX::LD_i8_ari;
791 break;
792 case MVT::i16:
793 Opcode = NVPTX::LD_i16_ari;
794 break;
795 case MVT::i32:
796 Opcode = NVPTX::LD_i32_ari;
797 break;
798 case MVT::i64:
799 Opcode = NVPTX::LD_i64_ari;
800 break;
801 case MVT::f32:
802 Opcode = NVPTX::LD_f32_ari;
803 break;
804 case MVT::f64:
805 Opcode = NVPTX::LD_f64_ari;
806 break;
807 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]808 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]809 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]810 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]811 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
812 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
813 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]814 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]815 } else {
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]816 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]817 switch (TargetVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]818 case MVT::i8:
819 Opcode = NVPTX::LD_i8_areg_64;
820 break;
821 case MVT::i16:
822 Opcode = NVPTX::LD_i16_areg_64;
823 break;
824 case MVT::i32:
825 Opcode = NVPTX::LD_i32_areg_64;
826 break;
827 case MVT::i64:
828 Opcode = NVPTX::LD_i64_areg_64;
829 break;
830 case MVT::f32:
831 Opcode = NVPTX::LD_f32_areg_64;
832 break;
833 case MVT::f64:
834 Opcode = NVPTX::LD_f64_areg_64;
835 break;
836 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]837 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]838 }
839 } else {
840 switch (TargetVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]841 case MVT::i8:
842 Opcode = NVPTX::LD_i8_areg;
843 break;
844 case MVT::i16:
845 Opcode = NVPTX::LD_i16_areg;
846 break;
847 case MVT::i32:
848 Opcode = NVPTX::LD_i32_areg;
849 break;
850 case MVT::i64:
851 Opcode = NVPTX::LD_i64_areg;
852 break;
853 case MVT::f32:
854 Opcode = NVPTX::LD_f32_areg;
855 break;
856 case MVT::f64:
857 Opcode = NVPTX::LD_f64_areg;
858 break;
859 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]860 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]861 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]862 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]863 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
864 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
865 getI32Imm(fromTypeWidth, dl), N1, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]866 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]867 }
868
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]869 if (NVPTXLD) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]870 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
871 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
872 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
873 }
874
875 return NVPTXLD;
876}
877
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]878SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
879
880 SDValue Chain = N->getOperand(0);
881 SDValue Op1 = N->getOperand(1);
882 SDValue Addr, Offset, Base;
883 unsigned Opcode;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]884 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]885 SDNode *LD;
886 MemSDNode *MemSD = cast<MemSDNode>(N);
887 EVT LoadedVT = MemSD->getMemoryVT();
888
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]889 if (!LoadedVT.isSimple())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]890 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]891
892 // Address Space Setting
Eric Christopher9745b3a2015-01-30 01:41:01 +0000[diff] [blame]893 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]894
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]895 if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpace, CurDAG->getDataLayout())) {
896 return SelectLDGLDU(N);
897 }
898
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]899 // Volatile Setting
900 // - .volatile is only availalble for .global and .shared
901 bool IsVolatile = MemSD->isVolatile();
902 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
903 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
904 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
905 IsVolatile = false;
906
907 // Vector Setting
908 MVT SimpleVT = LoadedVT.getSimpleVT();
909
910 // Type Setting: fromType + fromTypeWidth
911 //
912 // Sign : ISD::SEXTLOAD
913 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
914 // type is integer
915 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
916 MVT ScalarVT = SimpleVT.getScalarType();
Justin Holewinski994d66a2013-05-30 12:22:39 +0000[diff] [blame]917 // Read at least 8 bits (predicates are stored as 8-bit values)
918 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]919 unsigned int FromType;
920 // The last operand holds the original LoadSDNode::getExtensionType() value
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]921 unsigned ExtensionType = cast<ConstantSDNode>(
922 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]923 if (ExtensionType == ISD::SEXTLOAD)
924 FromType = NVPTX::PTXLdStInstCode::Signed;
925 else if (ScalarVT.isFloatingPoint())
926 FromType = NVPTX::PTXLdStInstCode::Float;
927 else
928 FromType = NVPTX::PTXLdStInstCode::Unsigned;
929
930 unsigned VecType;
931
932 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]933 case NVPTXISD::LoadV2:
934 VecType = NVPTX::PTXLdStInstCode::V2;
935 break;
936 case NVPTXISD::LoadV4:
937 VecType = NVPTX::PTXLdStInstCode::V4;
938 break;
939 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]940 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]941 }
942
943 EVT EltVT = N->getValueType(0);
944
945 if (SelectDirectAddr(Op1, Addr)) {
946 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]947 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]948 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]949 case NVPTXISD::LoadV2:
950 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]951 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]952 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]953 case MVT::i8:
954 Opcode = NVPTX::LDV_i8_v2_avar;
955 break;
956 case MVT::i16:
957 Opcode = NVPTX::LDV_i16_v2_avar;
958 break;
959 case MVT::i32:
960 Opcode = NVPTX::LDV_i32_v2_avar;
961 break;
962 case MVT::i64:
963 Opcode = NVPTX::LDV_i64_v2_avar;
964 break;
965 case MVT::f32:
966 Opcode = NVPTX::LDV_f32_v2_avar;
967 break;
968 case MVT::f64:
969 Opcode = NVPTX::LDV_f64_v2_avar;
970 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]971 }
972 break;
973 case NVPTXISD::LoadV4:
974 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]975 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]976 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]977 case MVT::i8:
978 Opcode = NVPTX::LDV_i8_v4_avar;
979 break;
980 case MVT::i16:
981 Opcode = NVPTX::LDV_i16_v4_avar;
982 break;
983 case MVT::i32:
984 Opcode = NVPTX::LDV_i32_v4_avar;
985 break;
986 case MVT::f32:
987 Opcode = NVPTX::LDV_f32_v4_avar;
988 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]989 }
990 break;
991 }
992
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]993 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
994 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
995 getI32Imm(FromTypeWidth, DL), Addr, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]996 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]997 } else if (TM.is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
998 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]999 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1000 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1001 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1002 case NVPTXISD::LoadV2:
1003 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1004 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1005 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1006 case MVT::i8:
1007 Opcode = NVPTX::LDV_i8_v2_asi;
1008 break;
1009 case MVT::i16:
1010 Opcode = NVPTX::LDV_i16_v2_asi;
1011 break;
1012 case MVT::i32:
1013 Opcode = NVPTX::LDV_i32_v2_asi;
1014 break;
1015 case MVT::i64:
1016 Opcode = NVPTX::LDV_i64_v2_asi;
1017 break;
1018 case MVT::f32:
1019 Opcode = NVPTX::LDV_f32_v2_asi;
1020 break;
1021 case MVT::f64:
1022 Opcode = NVPTX::LDV_f64_v2_asi;
1023 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1024 }
1025 break;
1026 case NVPTXISD::LoadV4:
1027 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1028 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1029 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1030 case MVT::i8:
1031 Opcode = NVPTX::LDV_i8_v4_asi;
1032 break;
1033 case MVT::i16:
1034 Opcode = NVPTX::LDV_i16_v4_asi;
1035 break;
1036 case MVT::i32:
1037 Opcode = NVPTX::LDV_i32_v4_asi;
1038 break;
1039 case MVT::f32:
1040 Opcode = NVPTX::LDV_f32_v4_asi;
1041 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1042 }
1043 break;
1044 }
1045
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1046 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1047 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1048 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]1049 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]1050 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1051 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1052 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1053 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1054 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1055 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1056 case NVPTXISD::LoadV2:
1057 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1058 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1059 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1060 case MVT::i8:
1061 Opcode = NVPTX::LDV_i8_v2_ari_64;
1062 break;
1063 case MVT::i16:
1064 Opcode = NVPTX::LDV_i16_v2_ari_64;
1065 break;
1066 case MVT::i32:
1067 Opcode = NVPTX::LDV_i32_v2_ari_64;
1068 break;
1069 case MVT::i64:
1070 Opcode = NVPTX::LDV_i64_v2_ari_64;
1071 break;
1072 case MVT::f32:
1073 Opcode = NVPTX::LDV_f32_v2_ari_64;
1074 break;
1075 case MVT::f64:
1076 Opcode = NVPTX::LDV_f64_v2_ari_64;
1077 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1078 }
1079 break;
1080 case NVPTXISD::LoadV4:
1081 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1082 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1083 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1084 case MVT::i8:
1085 Opcode = NVPTX::LDV_i8_v4_ari_64;
1086 break;
1087 case MVT::i16:
1088 Opcode = NVPTX::LDV_i16_v4_ari_64;
1089 break;
1090 case MVT::i32:
1091 Opcode = NVPTX::LDV_i32_v4_ari_64;
1092 break;
1093 case MVT::f32:
1094 Opcode = NVPTX::LDV_f32_v4_ari_64;
1095 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1096 }
1097 break;
1098 }
1099 } else {
1100 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1101 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1102 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1103 case NVPTXISD::LoadV2:
1104 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1105 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1106 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1107 case MVT::i8:
1108 Opcode = NVPTX::LDV_i8_v2_ari;
1109 break;
1110 case MVT::i16:
1111 Opcode = NVPTX::LDV_i16_v2_ari;
1112 break;
1113 case MVT::i32:
1114 Opcode = NVPTX::LDV_i32_v2_ari;
1115 break;
1116 case MVT::i64:
1117 Opcode = NVPTX::LDV_i64_v2_ari;
1118 break;
1119 case MVT::f32:
1120 Opcode = NVPTX::LDV_f32_v2_ari;
1121 break;
1122 case MVT::f64:
1123 Opcode = NVPTX::LDV_f64_v2_ari;
1124 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1125 }
1126 break;
1127 case NVPTXISD::LoadV4:
1128 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1129 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1130 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1131 case MVT::i8:
1132 Opcode = NVPTX::LDV_i8_v4_ari;
1133 break;
1134 case MVT::i16:
1135 Opcode = NVPTX::LDV_i16_v4_ari;
1136 break;
1137 case MVT::i32:
1138 Opcode = NVPTX::LDV_i32_v4_ari;
1139 break;
1140 case MVT::f32:
1141 Opcode = NVPTX::LDV_f32_v4_ari;
1142 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1143 }
1144 break;
1145 }
1146 }
1147
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1148 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1149 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1150 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1151
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]1152 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1153 } else {
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]1154 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1155 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1156 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1157 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1158 case NVPTXISD::LoadV2:
1159 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1160 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1161 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1162 case MVT::i8:
1163 Opcode = NVPTX::LDV_i8_v2_areg_64;
1164 break;
1165 case MVT::i16:
1166 Opcode = NVPTX::LDV_i16_v2_areg_64;
1167 break;
1168 case MVT::i32:
1169 Opcode = NVPTX::LDV_i32_v2_areg_64;
1170 break;
1171 case MVT::i64:
1172 Opcode = NVPTX::LDV_i64_v2_areg_64;
1173 break;
1174 case MVT::f32:
1175 Opcode = NVPTX::LDV_f32_v2_areg_64;
1176 break;
1177 case MVT::f64:
1178 Opcode = NVPTX::LDV_f64_v2_areg_64;
1179 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1180 }
1181 break;
1182 case NVPTXISD::LoadV4:
1183 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1184 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1185 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1186 case MVT::i8:
1187 Opcode = NVPTX::LDV_i8_v4_areg_64;
1188 break;
1189 case MVT::i16:
1190 Opcode = NVPTX::LDV_i16_v4_areg_64;
1191 break;
1192 case MVT::i32:
1193 Opcode = NVPTX::LDV_i32_v4_areg_64;
1194 break;
1195 case MVT::f32:
1196 Opcode = NVPTX::LDV_f32_v4_areg_64;
1197 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1198 }
1199 break;
1200 }
1201 } else {
1202 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1203 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1204 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1205 case NVPTXISD::LoadV2:
1206 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1207 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1208 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1209 case MVT::i8:
1210 Opcode = NVPTX::LDV_i8_v2_areg;
1211 break;
1212 case MVT::i16:
1213 Opcode = NVPTX::LDV_i16_v2_areg;
1214 break;
1215 case MVT::i32:
1216 Opcode = NVPTX::LDV_i32_v2_areg;
1217 break;
1218 case MVT::i64:
1219 Opcode = NVPTX::LDV_i64_v2_areg;
1220 break;
1221 case MVT::f32:
1222 Opcode = NVPTX::LDV_f32_v2_areg;
1223 break;
1224 case MVT::f64:
1225 Opcode = NVPTX::LDV_f64_v2_areg;
1226 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1227 }
1228 break;
1229 case NVPTXISD::LoadV4:
1230 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1231 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1232 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1233 case MVT::i8:
1234 Opcode = NVPTX::LDV_i8_v4_areg;
1235 break;
1236 case MVT::i16:
1237 Opcode = NVPTX::LDV_i16_v4_areg;
1238 break;
1239 case MVT::i32:
1240 Opcode = NVPTX::LDV_i32_v4_areg;
1241 break;
1242 case MVT::f32:
1243 Opcode = NVPTX::LDV_f32_v4_areg;
1244 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1245 }
1246 break;
1247 }
1248 }
1249
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1250 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1251 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1252 getI32Imm(FromTypeWidth, DL), Op1, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]1253 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1254 }
1255
1256 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1257 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1258 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1259
1260 return LD;
1261}
1262
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1263SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1264
1265 SDValue Chain = N->getOperand(0);
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1266 SDValue Op1;
1267 MemSDNode *Mem;
1268 bool IsLDG = true;
1269
1270 // If this is an LDG intrinsic, the address is the third operand. Its its an
1271 // LDG/LDU SD node (from custom vector handling), then its the second operand
1272 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1273 Op1 = N->getOperand(2);
1274 Mem = cast<MemIntrinsicSDNode>(N);
1275 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1276 switch (IID) {
1277 default:
1278 return NULL;
1279 case Intrinsic::nvvm_ldg_global_f:
1280 case Intrinsic::nvvm_ldg_global_i:
1281 case Intrinsic::nvvm_ldg_global_p:
1282 IsLDG = true;
1283 break;
1284 case Intrinsic::nvvm_ldu_global_f:
1285 case Intrinsic::nvvm_ldu_global_i:
1286 case Intrinsic::nvvm_ldu_global_p:
1287 IsLDG = false;
1288 break;
1289 }
1290 } else {
1291 Op1 = N->getOperand(1);
1292 Mem = cast<MemSDNode>(N);
1293 }
1294
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1295 unsigned Opcode;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1296 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1297 SDNode *LD;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1298 SDValue Base, Offset, Addr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1299
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1300 EVT EltVT = Mem->getMemoryVT();
1301 if (EltVT.isVector()) {
1302 EltVT = EltVT.getVectorElementType();
1303 }
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1304
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1305 if (SelectDirectAddr(Op1, Addr)) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1306 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1307 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1308 return nullptr;
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1309 case ISD::INTRINSIC_W_CHAIN:
1310 if (IsLDG) {
1311 switch (EltVT.getSimpleVT().SimpleTy) {
1312 default:
1313 return nullptr;
1314 case MVT::i8:
1315 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1316 break;
1317 case MVT::i16:
1318 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1319 break;
1320 case MVT::i32:
1321 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1322 break;
1323 case MVT::i64:
1324 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1325 break;
1326 case MVT::f32:
1327 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1328 break;
1329 case MVT::f64:
1330 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1331 break;
1332 }
1333 } else {
1334 switch (EltVT.getSimpleVT().SimpleTy) {
1335 default:
1336 return nullptr;
1337 case MVT::i8:
1338 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1339 break;
1340 case MVT::i16:
1341 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1342 break;
1343 case MVT::i32:
1344 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1345 break;
1346 case MVT::i64:
1347 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1348 break;
1349 case MVT::f32:
1350 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1351 break;
1352 case MVT::f64:
1353 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1354 break;
1355 }
1356 }
1357 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1358 case NVPTXISD::LDGV2:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1359 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1360 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1361 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1362 case MVT::i8:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1363 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1364 break;
1365 case MVT::i16:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1366 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1367 break;
1368 case MVT::i32:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1369 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1370 break;
1371 case MVT::i64:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1372 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1373 break;
1374 case MVT::f32:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1375 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1376 break;
1377 case MVT::f64:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1378 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1379 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1380 }
1381 break;
1382 case NVPTXISD::LDUV2:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1383 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1384 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1385 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1386 case MVT::i8:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1387 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1388 break;
1389 case MVT::i16:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1390 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1391 break;
1392 case MVT::i32:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1393 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1394 break;
1395 case MVT::i64:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1396 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1397 break;
1398 case MVT::f32:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1399 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1400 break;
1401 case MVT::f64:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1402 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1403 break;
1404 }
1405 break;
1406 case NVPTXISD::LDGV4:
1407 switch (EltVT.getSimpleVT().SimpleTy) {
1408 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1409 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1410 case MVT::i8:
1411 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1412 break;
1413 case MVT::i16:
1414 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1415 break;
1416 case MVT::i32:
1417 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1418 break;
1419 case MVT::f32:
1420 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1421 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1422 }
1423 break;
1424 case NVPTXISD::LDUV4:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1425 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1426 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1427 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1428 case MVT::i8:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1429 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1430 break;
1431 case MVT::i16:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1432 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1433 break;
1434 case MVT::i32:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1435 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1436 break;
1437 case MVT::f32:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1438 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1439 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1440 }
1441 break;
1442 }
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1443
1444 SDValue Ops[] = { Addr, Chain };
Craig Topper2d2aa0c2014-04-30 07:17:30 +0000[diff] [blame]1445 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]1446 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1447 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1448 if (TM.is64Bit()) {
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1449 switch (N->getOpcode()) {
1450 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1451 return nullptr;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1452 case ISD::LOAD:
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1453 case ISD::INTRINSIC_W_CHAIN:
1454 if (IsLDG) {
1455 switch (EltVT.getSimpleVT().SimpleTy) {
1456 default:
1457 return nullptr;
1458 case MVT::i8:
1459 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1460 break;
1461 case MVT::i16:
1462 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1463 break;
1464 case MVT::i32:
1465 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1466 break;
1467 case MVT::i64:
1468 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1469 break;
1470 case MVT::f32:
1471 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1472 break;
1473 case MVT::f64:
1474 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1475 break;
1476 }
1477 } else {
1478 switch (EltVT.getSimpleVT().SimpleTy) {
1479 default:
1480 return nullptr;
1481 case MVT::i8:
1482 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1483 break;
1484 case MVT::i16:
1485 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1486 break;
1487 case MVT::i32:
1488 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1489 break;
1490 case MVT::i64:
1491 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1492 break;
1493 case MVT::f32:
1494 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1495 break;
1496 case MVT::f64:
1497 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1498 break;
1499 }
1500 }
1501 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1502 case NVPTXISD::LoadV2:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1503 case NVPTXISD::LDGV2:
1504 switch (EltVT.getSimpleVT().SimpleTy) {
1505 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1506 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1507 case MVT::i8:
1508 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1509 break;
1510 case MVT::i16:
1511 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1512 break;
1513 case MVT::i32:
1514 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1515 break;
1516 case MVT::i64:
1517 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1518 break;
1519 case MVT::f32:
1520 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1521 break;
1522 case MVT::f64:
1523 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1524 break;
1525 }
1526 break;
1527 case NVPTXISD::LDUV2:
1528 switch (EltVT.getSimpleVT().SimpleTy) {
1529 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1530 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1531 case MVT::i8:
1532 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1533 break;
1534 case MVT::i16:
1535 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1536 break;
1537 case MVT::i32:
1538 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1539 break;
1540 case MVT::i64:
1541 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1542 break;
1543 case MVT::f32:
1544 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1545 break;
1546 case MVT::f64:
1547 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1548 break;
1549 }
1550 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1551 case NVPTXISD::LoadV4:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1552 case NVPTXISD::LDGV4:
1553 switch (EltVT.getSimpleVT().SimpleTy) {
1554 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1555 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1556 case MVT::i8:
1557 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1558 break;
1559 case MVT::i16:
1560 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1561 break;
1562 case MVT::i32:
1563 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1564 break;
1565 case MVT::f32:
1566 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1567 break;
1568 }
1569 break;
1570 case NVPTXISD::LDUV4:
1571 switch (EltVT.getSimpleVT().SimpleTy) {
1572 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1573 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1574 case MVT::i8:
1575 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1576 break;
1577 case MVT::i16:
1578 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1579 break;
1580 case MVT::i32:
1581 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1582 break;
1583 case MVT::f32:
1584 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1585 break;
1586 }
1587 break;
1588 }
1589 } else {
1590 switch (N->getOpcode()) {
1591 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1592 return nullptr;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1593 case ISD::LOAD:
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1594 case ISD::INTRINSIC_W_CHAIN:
1595 if (IsLDG) {
1596 switch (EltVT.getSimpleVT().SimpleTy) {
1597 default:
1598 return nullptr;
1599 case MVT::i8:
1600 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1601 break;
1602 case MVT::i16:
1603 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1604 break;
1605 case MVT::i32:
1606 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1607 break;
1608 case MVT::i64:
1609 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1610 break;
1611 case MVT::f32:
1612 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1613 break;
1614 case MVT::f64:
1615 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1616 break;
1617 }
1618 } else {
1619 switch (EltVT.getSimpleVT().SimpleTy) {
1620 default:
1621 return nullptr;
1622 case MVT::i8:
1623 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1624 break;
1625 case MVT::i16:
1626 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1627 break;
1628 case MVT::i32:
1629 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1630 break;
1631 case MVT::i64:
1632 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1633 break;
1634 case MVT::f32:
1635 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1636 break;
1637 case MVT::f64:
1638 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1639 break;
1640 }
1641 }
1642 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1643 case NVPTXISD::LoadV2:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1644 case NVPTXISD::LDGV2:
1645 switch (EltVT.getSimpleVT().SimpleTy) {
1646 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1647 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1648 case MVT::i8:
1649 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1650 break;
1651 case MVT::i16:
1652 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1653 break;
1654 case MVT::i32:
1655 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1656 break;
1657 case MVT::i64:
1658 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1659 break;
1660 case MVT::f32:
1661 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1662 break;
1663 case MVT::f64:
1664 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1665 break;
1666 }
1667 break;
1668 case NVPTXISD::LDUV2:
1669 switch (EltVT.getSimpleVT().SimpleTy) {
1670 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1671 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1672 case MVT::i8:
1673 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1674 break;
1675 case MVT::i16:
1676 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1677 break;
1678 case MVT::i32:
1679 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1680 break;
1681 case MVT::i64:
1682 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1683 break;
1684 case MVT::f32:
1685 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1686 break;
1687 case MVT::f64:
1688 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1689 break;
1690 }
1691 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1692 case NVPTXISD::LoadV4:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1693 case NVPTXISD::LDGV4:
1694 switch (EltVT.getSimpleVT().SimpleTy) {
1695 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1696 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1697 case MVT::i8:
1698 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1699 break;
1700 case MVT::i16:
1701 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1702 break;
1703 case MVT::i32:
1704 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1705 break;
1706 case MVT::f32:
1707 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1708 break;
1709 }
1710 break;
1711 case NVPTXISD::LDUV4:
1712 switch (EltVT.getSimpleVT().SimpleTy) {
1713 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1714 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1715 case MVT::i8:
1716 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1717 break;
1718 case MVT::i16:
1719 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1720 break;
1721 case MVT::i32:
1722 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1723 break;
1724 case MVT::f32:
1725 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1726 break;
1727 }
1728 break;
1729 }
1730 }
1731
1732 SDValue Ops[] = { Base, Offset, Chain };
1733
Craig Topper2d2aa0c2014-04-30 07:17:30 +0000[diff] [blame]1734 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1735 } else {
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]1736 if (TM.is64Bit()) {
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1737 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1738 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1739 return nullptr;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1740 case ISD::LOAD:
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1741 case ISD::INTRINSIC_W_CHAIN:
1742 if (IsLDG) {
1743 switch (EltVT.getSimpleVT().SimpleTy) {
1744 default:
1745 return nullptr;
1746 case MVT::i8:
1747 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1748 break;
1749 case MVT::i16:
1750 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1751 break;
1752 case MVT::i32:
1753 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1754 break;
1755 case MVT::i64:
1756 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1757 break;
1758 case MVT::f32:
1759 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1760 break;
1761 case MVT::f64:
1762 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1763 break;
1764 }
1765 } else {
1766 switch (EltVT.getSimpleVT().SimpleTy) {
1767 default:
1768 return nullptr;
1769 case MVT::i8:
1770 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1771 break;
1772 case MVT::i16:
1773 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1774 break;
1775 case MVT::i32:
1776 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1777 break;
1778 case MVT::i64:
1779 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1780 break;
1781 case MVT::f32:
1782 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1783 break;
1784 case MVT::f64:
1785 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1786 break;
1787 }
1788 }
1789 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1790 case NVPTXISD::LoadV2:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1791 case NVPTXISD::LDGV2:
1792 switch (EltVT.getSimpleVT().SimpleTy) {
1793 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1794 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1795 case MVT::i8:
1796 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1797 break;
1798 case MVT::i16:
1799 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1800 break;
1801 case MVT::i32:
1802 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1803 break;
1804 case MVT::i64:
1805 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1806 break;
1807 case MVT::f32:
1808 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1809 break;
1810 case MVT::f64:
1811 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1812 break;
1813 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1814 break;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1815 case NVPTXISD::LDUV2:
1816 switch (EltVT.getSimpleVT().SimpleTy) {
1817 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1818 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1819 case MVT::i8:
1820 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1821 break;
1822 case MVT::i16:
1823 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1824 break;
1825 case MVT::i32:
1826 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1827 break;
1828 case MVT::i64:
1829 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1830 break;
1831 case MVT::f32:
1832 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1833 break;
1834 case MVT::f64:
1835 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1836 break;
1837 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1838 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1839 case NVPTXISD::LoadV4:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1840 case NVPTXISD::LDGV4:
1841 switch (EltVT.getSimpleVT().SimpleTy) {
1842 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1843 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1844 case MVT::i8:
1845 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1846 break;
1847 case MVT::i16:
1848 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1849 break;
1850 case MVT::i32:
1851 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1852 break;
1853 case MVT::f32:
1854 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1855 break;
1856 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1857 break;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1858 case NVPTXISD::LDUV4:
1859 switch (EltVT.getSimpleVT().SimpleTy) {
1860 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1861 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1862 case MVT::i8:
1863 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1864 break;
1865 case MVT::i16:
1866 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1867 break;
1868 case MVT::i32:
1869 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1870 break;
1871 case MVT::f32:
1872 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1873 break;
1874 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1875 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1876 }
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1877 } else {
1878 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1879 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1880 return nullptr;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1881 case ISD::LOAD:
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]1882 case ISD::INTRINSIC_W_CHAIN:
1883 if (IsLDG) {
1884 switch (EltVT.getSimpleVT().SimpleTy) {
1885 default:
1886 return nullptr;
1887 case MVT::i8:
1888 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1889 break;
1890 case MVT::i16:
1891 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1892 break;
1893 case MVT::i32:
1894 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1895 break;
1896 case MVT::i64:
1897 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1898 break;
1899 case MVT::f32:
1900 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1901 break;
1902 case MVT::f64:
1903 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1904 break;
1905 }
1906 } else {
1907 switch (EltVT.getSimpleVT().SimpleTy) {
1908 default:
1909 return nullptr;
1910 case MVT::i8:
1911 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1912 break;
1913 case MVT::i16:
1914 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1915 break;
1916 case MVT::i32:
1917 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1918 break;
1919 case MVT::i64:
1920 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1921 break;
1922 case MVT::f32:
1923 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1924 break;
1925 case MVT::f64:
1926 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1927 break;
1928 }
1929 }
1930 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1931 case NVPTXISD::LoadV2:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1932 case NVPTXISD::LDGV2:
1933 switch (EltVT.getSimpleVT().SimpleTy) {
1934 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1935 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1936 case MVT::i8:
1937 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1938 break;
1939 case MVT::i16:
1940 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1941 break;
1942 case MVT::i32:
1943 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1944 break;
1945 case MVT::i64:
1946 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1947 break;
1948 case MVT::f32:
1949 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1950 break;
1951 case MVT::f64:
1952 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1953 break;
1954 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1955 break;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1956 case NVPTXISD::LDUV2:
1957 switch (EltVT.getSimpleVT().SimpleTy) {
1958 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1959 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1960 case MVT::i8:
1961 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1962 break;
1963 case MVT::i16:
1964 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1965 break;
1966 case MVT::i32:
1967 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1968 break;
1969 case MVT::i64:
1970 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1971 break;
1972 case MVT::f32:
1973 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1974 break;
1975 case MVT::f64:
1976 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1977 break;
1978 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1979 break;
Jingyue Wu48a9bdc2015-07-20 21:28:54 +0000[diff] [blame]1980 case NVPTXISD::LoadV4:
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1981 case NVPTXISD::LDGV4:
1982 switch (EltVT.getSimpleVT().SimpleTy) {
1983 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1984 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1985 case MVT::i8:
1986 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1987 break;
1988 case MVT::i16:
1989 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1990 break;
1991 case MVT::i32:
1992 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1993 break;
1994 case MVT::f32:
1995 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1996 break;
1997 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1998 break;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]1999 case NVPTXISD::LDUV4:
2000 switch (EltVT.getSimpleVT().SimpleTy) {
2001 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2002 return nullptr;
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]2003 case MVT::i8:
2004 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
2005 break;
2006 case MVT::i16:
2007 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
2008 break;
2009 case MVT::i32:
2010 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
2011 break;
2012 case MVT::f32:
2013 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
2014 break;
2015 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2016 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2017 }
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2018 }
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2019
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]2020 SDValue Ops[] = { Op1, Chain };
Craig Topper2d2aa0c2014-04-30 07:17:30 +0000[diff] [blame]2021 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
Justin Holewinskie40e9292013-07-01 12:58:52 +0000[diff] [blame]2022 }
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2023
2024 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
Justin Holewinskib926d9d2014-06-27 18:35:51 +0000[diff] [blame]2025 MemRefs0[0] = Mem->getMemOperand();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2026 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
2027
2028 return LD;
2029}
2030
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2031SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]2032 SDLoc dl(N);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2033 StoreSDNode *ST = cast<StoreSDNode>(N);
2034 EVT StoreVT = ST->getMemoryVT();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2035 SDNode *NVPTXST = nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2036
2037 // do not support pre/post inc/dec
2038 if (ST->isIndexed())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2039 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2040
2041 if (!StoreVT.isSimple())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2042 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2043
2044 // Address Space Setting
Eric Christopher9745b3a2015-01-30 01:41:01 +0000[diff] [blame]2045 unsigned int codeAddrSpace = getCodeAddrSpace(ST);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2046
2047 // Volatile Setting
2048 // - .volatile is only availalble for .global and .shared
2049 bool isVolatile = ST->isVolatile();
2050 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2051 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2052 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2053 isVolatile = false;
2054
2055 // Vector Setting
2056 MVT SimpleVT = StoreVT.getSimpleVT();
2057 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
2058 if (SimpleVT.isVector()) {
2059 unsigned num = SimpleVT.getVectorNumElements();
2060 if (num == 2)
2061 vecType = NVPTX::PTXLdStInstCode::V2;
2062 else if (num == 4)
2063 vecType = NVPTX::PTXLdStInstCode::V4;
2064 else
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2065 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2066 }
2067
2068 // Type Setting: toType + toTypeWidth
2069 // - for integer type, always use 'u'
2070 //
2071 MVT ScalarVT = SimpleVT.getScalarType();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2072 unsigned toTypeWidth = ScalarVT.getSizeInBits();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2073 unsigned int toType;
2074 if (ScalarVT.isFloatingPoint())
2075 toType = NVPTX::PTXLdStInstCode::Float;
2076 else
2077 toType = NVPTX::PTXLdStInstCode::Unsigned;
2078
2079 // Create the machine instruction DAG
2080 SDValue Chain = N->getOperand(0);
2081 SDValue N1 = N->getOperand(1);
2082 SDValue N2 = N->getOperand(2);
2083 SDValue Addr;
2084 SDValue Offset, Base;
2085 unsigned Opcode;
Craig Topperd9c27832013-08-15 02:44:19 +0000[diff] [blame]2086 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2087
2088 if (SelectDirectAddr(N2, Addr)) {
2089 switch (SourceVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2090 case MVT::i8:
2091 Opcode = NVPTX::ST_i8_avar;
2092 break;
2093 case MVT::i16:
2094 Opcode = NVPTX::ST_i16_avar;
2095 break;
2096 case MVT::i32:
2097 Opcode = NVPTX::ST_i32_avar;
2098 break;
2099 case MVT::i64:
2100 Opcode = NVPTX::ST_i64_avar;
2101 break;
2102 case MVT::f32:
2103 Opcode = NVPTX::ST_f32_avar;
2104 break;
2105 case MVT::f64:
2106 Opcode = NVPTX::ST_f64_avar;
2107 break;
2108 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2109 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2110 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2111 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2112 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2113 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Addr,
2114 Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]2115 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]2116 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2117 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2118 switch (SourceVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2119 case MVT::i8:
2120 Opcode = NVPTX::ST_i8_asi;
2121 break;
2122 case MVT::i16:
2123 Opcode = NVPTX::ST_i16_asi;
2124 break;
2125 case MVT::i32:
2126 Opcode = NVPTX::ST_i32_asi;
2127 break;
2128 case MVT::i64:
2129 Opcode = NVPTX::ST_i64_asi;
2130 break;
2131 case MVT::f32:
2132 Opcode = NVPTX::ST_f32_asi;
2133 break;
2134 case MVT::f64:
2135 Opcode = NVPTX::ST_f64_asi;
2136 break;
2137 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2138 return nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2139 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2140 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2141 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2142 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2143 Offset, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]2144 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]2145 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2146 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2147 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2148 switch (SourceVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2149 case MVT::i8:
2150 Opcode = NVPTX::ST_i8_ari_64;
2151 break;
2152 case MVT::i16:
2153 Opcode = NVPTX::ST_i16_ari_64;
2154 break;
2155 case MVT::i32:
2156 Opcode = NVPTX::ST_i32_ari_64;
2157 break;
2158 case MVT::i64:
2159 Opcode = NVPTX::ST_i64_ari_64;
2160 break;
2161 case MVT::f32:
2162 Opcode = NVPTX::ST_f32_ari_64;
2163 break;
2164 case MVT::f64:
2165 Opcode = NVPTX::ST_f64_ari_64;
2166 break;
2167 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2168 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2169 }
2170 } else {
2171 switch (SourceVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2172 case MVT::i8:
2173 Opcode = NVPTX::ST_i8_ari;
2174 break;
2175 case MVT::i16:
2176 Opcode = NVPTX::ST_i16_ari;
2177 break;
2178 case MVT::i32:
2179 Opcode = NVPTX::ST_i32_ari;
2180 break;
2181 case MVT::i64:
2182 Opcode = NVPTX::ST_i64_ari;
2183 break;
2184 case MVT::f32:
2185 Opcode = NVPTX::ST_f32_ari;
2186 break;
2187 case MVT::f64:
2188 Opcode = NVPTX::ST_f64_ari;
2189 break;
2190 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2191 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2192 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2193 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2194 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2195 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2196 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2197 Offset, Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]2198 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2199 } else {
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]2200 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2201 switch (SourceVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2202 case MVT::i8:
2203 Opcode = NVPTX::ST_i8_areg_64;
2204 break;
2205 case MVT::i16:
2206 Opcode = NVPTX::ST_i16_areg_64;
2207 break;
2208 case MVT::i32:
2209 Opcode = NVPTX::ST_i32_areg_64;
2210 break;
2211 case MVT::i64:
2212 Opcode = NVPTX::ST_i64_areg_64;
2213 break;
2214 case MVT::f32:
2215 Opcode = NVPTX::ST_f32_areg_64;
2216 break;
2217 case MVT::f64:
2218 Opcode = NVPTX::ST_f64_areg_64;
2219 break;
2220 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2221 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2222 }
2223 } else {
2224 switch (SourceVT) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2225 case MVT::i8:
2226 Opcode = NVPTX::ST_i8_areg;
2227 break;
2228 case MVT::i16:
2229 Opcode = NVPTX::ST_i16_areg;
2230 break;
2231 case MVT::i32:
2232 Opcode = NVPTX::ST_i32_areg;
2233 break;
2234 case MVT::i64:
2235 Opcode = NVPTX::ST_i64_areg;
2236 break;
2237 case MVT::f32:
2238 Opcode = NVPTX::ST_f32_areg;
2239 break;
2240 case MVT::f64:
2241 Opcode = NVPTX::ST_f64_areg;
2242 break;
2243 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2244 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2245 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2246 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2247 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2248 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2249 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), N2,
2250 Chain };
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]2251 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2252 }
2253
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2254 if (NVPTXST) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2255 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2256 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2257 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2258 }
2259
2260 return NVPTXST;
2261}
2262
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2263SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
2264 SDValue Chain = N->getOperand(0);
2265 SDValue Op1 = N->getOperand(1);
2266 SDValue Addr, Offset, Base;
2267 unsigned Opcode;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]2268 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2269 SDNode *ST;
2270 EVT EltVT = Op1.getValueType();
2271 MemSDNode *MemSD = cast<MemSDNode>(N);
2272 EVT StoreVT = MemSD->getMemoryVT();
2273
2274 // Address Space Setting
Eric Christopher9745b3a2015-01-30 01:41:01 +0000[diff] [blame]2275 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2276
2277 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
2278 report_fatal_error("Cannot store to pointer that points to constant "
2279 "memory space");
2280 }
2281
2282 // Volatile Setting
2283 // - .volatile is only availalble for .global and .shared
2284 bool IsVolatile = MemSD->isVolatile();
2285 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2286 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2287 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2288 IsVolatile = false;
2289
2290 // Type Setting: toType + toTypeWidth
2291 // - for integer type, always use 'u'
2292 assert(StoreVT.isSimple() && "Store value is not simple");
2293 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2294 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2295 unsigned ToType;
2296 if (ScalarVT.isFloatingPoint())
2297 ToType = NVPTX::PTXLdStInstCode::Float;
2298 else
2299 ToType = NVPTX::PTXLdStInstCode::Unsigned;
2300
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2301 SmallVector<SDValue, 12> StOps;
2302 SDValue N2;
2303 unsigned VecType;
2304
2305 switch (N->getOpcode()) {
2306 case NVPTXISD::StoreV2:
2307 VecType = NVPTX::PTXLdStInstCode::V2;
2308 StOps.push_back(N->getOperand(1));
2309 StOps.push_back(N->getOperand(2));
2310 N2 = N->getOperand(3);
2311 break;
2312 case NVPTXISD::StoreV4:
2313 VecType = NVPTX::PTXLdStInstCode::V4;
2314 StOps.push_back(N->getOperand(1));
2315 StOps.push_back(N->getOperand(2));
2316 StOps.push_back(N->getOperand(3));
2317 StOps.push_back(N->getOperand(4));
2318 N2 = N->getOperand(5);
2319 break;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2320 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2321 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2322 }
2323
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2324 StOps.push_back(getI32Imm(IsVolatile, DL));
2325 StOps.push_back(getI32Imm(CodeAddrSpace, DL));
2326 StOps.push_back(getI32Imm(VecType, DL));
2327 StOps.push_back(getI32Imm(ToType, DL));
2328 StOps.push_back(getI32Imm(ToTypeWidth, DL));
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2329
2330 if (SelectDirectAddr(N2, Addr)) {
2331 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2332 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2333 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2334 case NVPTXISD::StoreV2:
2335 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2336 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2337 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2338 case MVT::i8:
2339 Opcode = NVPTX::STV_i8_v2_avar;
2340 break;
2341 case MVT::i16:
2342 Opcode = NVPTX::STV_i16_v2_avar;
2343 break;
2344 case MVT::i32:
2345 Opcode = NVPTX::STV_i32_v2_avar;
2346 break;
2347 case MVT::i64:
2348 Opcode = NVPTX::STV_i64_v2_avar;
2349 break;
2350 case MVT::f32:
2351 Opcode = NVPTX::STV_f32_v2_avar;
2352 break;
2353 case MVT::f64:
2354 Opcode = NVPTX::STV_f64_v2_avar;
2355 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2356 }
2357 break;
2358 case NVPTXISD::StoreV4:
2359 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2360 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2361 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2362 case MVT::i8:
2363 Opcode = NVPTX::STV_i8_v4_avar;
2364 break;
2365 case MVT::i16:
2366 Opcode = NVPTX::STV_i16_v4_avar;
2367 break;
2368 case MVT::i32:
2369 Opcode = NVPTX::STV_i32_v4_avar;
2370 break;
2371 case MVT::f32:
2372 Opcode = NVPTX::STV_f32_v4_avar;
2373 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2374 }
2375 break;
2376 }
2377 StOps.push_back(Addr);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]2378 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2379 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2380 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2381 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2382 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2383 case NVPTXISD::StoreV2:
2384 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2385 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2386 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2387 case MVT::i8:
2388 Opcode = NVPTX::STV_i8_v2_asi;
2389 break;
2390 case MVT::i16:
2391 Opcode = NVPTX::STV_i16_v2_asi;
2392 break;
2393 case MVT::i32:
2394 Opcode = NVPTX::STV_i32_v2_asi;
2395 break;
2396 case MVT::i64:
2397 Opcode = NVPTX::STV_i64_v2_asi;
2398 break;
2399 case MVT::f32:
2400 Opcode = NVPTX::STV_f32_v2_asi;
2401 break;
2402 case MVT::f64:
2403 Opcode = NVPTX::STV_f64_v2_asi;
2404 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2405 }
2406 break;
2407 case NVPTXISD::StoreV4:
2408 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2409 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2410 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2411 case MVT::i8:
2412 Opcode = NVPTX::STV_i8_v4_asi;
2413 break;
2414 case MVT::i16:
2415 Opcode = NVPTX::STV_i16_v4_asi;
2416 break;
2417 case MVT::i32:
2418 Opcode = NVPTX::STV_i32_v4_asi;
2419 break;
2420 case MVT::f32:
2421 Opcode = NVPTX::STV_f32_v4_asi;
2422 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2423 }
2424 break;
2425 }
2426 StOps.push_back(Base);
2427 StOps.push_back(Offset);
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]2428 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2429 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2430 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2431 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2432 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2433 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2434 case NVPTXISD::StoreV2:
2435 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2436 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2437 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2438 case MVT::i8:
2439 Opcode = NVPTX::STV_i8_v2_ari_64;
2440 break;
2441 case MVT::i16:
2442 Opcode = NVPTX::STV_i16_v2_ari_64;
2443 break;
2444 case MVT::i32:
2445 Opcode = NVPTX::STV_i32_v2_ari_64;
2446 break;
2447 case MVT::i64:
2448 Opcode = NVPTX::STV_i64_v2_ari_64;
2449 break;
2450 case MVT::f32:
2451 Opcode = NVPTX::STV_f32_v2_ari_64;
2452 break;
2453 case MVT::f64:
2454 Opcode = NVPTX::STV_f64_v2_ari_64;
2455 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2456 }
2457 break;
2458 case NVPTXISD::StoreV4:
2459 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2460 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2461 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2462 case MVT::i8:
2463 Opcode = NVPTX::STV_i8_v4_ari_64;
2464 break;
2465 case MVT::i16:
2466 Opcode = NVPTX::STV_i16_v4_ari_64;
2467 break;
2468 case MVT::i32:
2469 Opcode = NVPTX::STV_i32_v4_ari_64;
2470 break;
2471 case MVT::f32:
2472 Opcode = NVPTX::STV_f32_v4_ari_64;
2473 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2474 }
2475 break;
2476 }
2477 } else {
2478 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2479 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2480 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2481 case NVPTXISD::StoreV2:
2482 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2483 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2484 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2485 case MVT::i8:
2486 Opcode = NVPTX::STV_i8_v2_ari;
2487 break;
2488 case MVT::i16:
2489 Opcode = NVPTX::STV_i16_v2_ari;
2490 break;
2491 case MVT::i32:
2492 Opcode = NVPTX::STV_i32_v2_ari;
2493 break;
2494 case MVT::i64:
2495 Opcode = NVPTX::STV_i64_v2_ari;
2496 break;
2497 case MVT::f32:
2498 Opcode = NVPTX::STV_f32_v2_ari;
2499 break;
2500 case MVT::f64:
2501 Opcode = NVPTX::STV_f64_v2_ari;
2502 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2503 }
2504 break;
2505 case NVPTXISD::StoreV4:
2506 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2507 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2508 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2509 case MVT::i8:
2510 Opcode = NVPTX::STV_i8_v4_ari;
2511 break;
2512 case MVT::i16:
2513 Opcode = NVPTX::STV_i16_v4_ari;
2514 break;
2515 case MVT::i32:
2516 Opcode = NVPTX::STV_i32_v4_ari;
2517 break;
2518 case MVT::f32:
2519 Opcode = NVPTX::STV_f32_v4_ari;
2520 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2521 }
2522 break;
2523 }
2524 }
2525 StOps.push_back(Base);
2526 StOps.push_back(Offset);
2527 } else {
Eric Christopher02389e32015-02-19 00:08:27 +0000[diff] [blame]2528 if (TM.is64Bit()) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2529 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2530 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2531 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2532 case NVPTXISD::StoreV2:
2533 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2534 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2535 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2536 case MVT::i8:
2537 Opcode = NVPTX::STV_i8_v2_areg_64;
2538 break;
2539 case MVT::i16:
2540 Opcode = NVPTX::STV_i16_v2_areg_64;
2541 break;
2542 case MVT::i32:
2543 Opcode = NVPTX::STV_i32_v2_areg_64;
2544 break;
2545 case MVT::i64:
2546 Opcode = NVPTX::STV_i64_v2_areg_64;
2547 break;
2548 case MVT::f32:
2549 Opcode = NVPTX::STV_f32_v2_areg_64;
2550 break;
2551 case MVT::f64:
2552 Opcode = NVPTX::STV_f64_v2_areg_64;
2553 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2554 }
2555 break;
2556 case NVPTXISD::StoreV4:
2557 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2558 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2559 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2560 case MVT::i8:
2561 Opcode = NVPTX::STV_i8_v4_areg_64;
2562 break;
2563 case MVT::i16:
2564 Opcode = NVPTX::STV_i16_v4_areg_64;
2565 break;
2566 case MVT::i32:
2567 Opcode = NVPTX::STV_i32_v4_areg_64;
2568 break;
2569 case MVT::f32:
2570 Opcode = NVPTX::STV_f32_v4_areg_64;
2571 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2572 }
2573 break;
2574 }
2575 } else {
2576 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2577 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2578 return nullptr;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2579 case NVPTXISD::StoreV2:
2580 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2581 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2582 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2583 case MVT::i8:
2584 Opcode = NVPTX::STV_i8_v2_areg;
2585 break;
2586 case MVT::i16:
2587 Opcode = NVPTX::STV_i16_v2_areg;
2588 break;
2589 case MVT::i32:
2590 Opcode = NVPTX::STV_i32_v2_areg;
2591 break;
2592 case MVT::i64:
2593 Opcode = NVPTX::STV_i64_v2_areg;
2594 break;
2595 case MVT::f32:
2596 Opcode = NVPTX::STV_f32_v2_areg;
2597 break;
2598 case MVT::f64:
2599 Opcode = NVPTX::STV_f64_v2_areg;
2600 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2601 }
2602 break;
2603 case NVPTXISD::StoreV4:
2604 switch (EltVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2605 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2606 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2607 case MVT::i8:
2608 Opcode = NVPTX::STV_i8_v4_areg;
2609 break;
2610 case MVT::i16:
2611 Opcode = NVPTX::STV_i16_v4_areg;
2612 break;
2613 case MVT::i32:
2614 Opcode = NVPTX::STV_i32_v4_areg;
2615 break;
2616 case MVT::f32:
2617 Opcode = NVPTX::STV_f32_v4_areg;
2618 break;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2619 }
2620 break;
2621 }
2622 }
2623 StOps.push_back(N2);
2624 }
2625
2626 StOps.push_back(Chain);
2627
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]2628 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2629
2630 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2631 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2632 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2633
2634 return ST;
2635}
2636
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2637SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2638 SDValue Chain = Node->getOperand(0);
2639 SDValue Offset = Node->getOperand(2);
2640 SDValue Flag = Node->getOperand(3);
2641 SDLoc DL(Node);
2642 MemSDNode *Mem = cast<MemSDNode>(Node);
2643
2644 unsigned VecSize;
2645 switch (Node->getOpcode()) {
2646 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2647 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2648 case NVPTXISD::LoadParam:
2649 VecSize = 1;
2650 break;
2651 case NVPTXISD::LoadParamV2:
2652 VecSize = 2;
2653 break;
2654 case NVPTXISD::LoadParamV4:
2655 VecSize = 4;
2656 break;
2657 }
2658
2659 EVT EltVT = Node->getValueType(0);
2660 EVT MemVT = Mem->getMemoryVT();
2661
2662 unsigned Opc = 0;
2663
2664 switch (VecSize) {
2665 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2666 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2667 case 1:
2668 switch (MemVT.getSimpleVT().SimpleTy) {
2669 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2670 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2671 case MVT::i1:
2672 Opc = NVPTX::LoadParamMemI8;
2673 break;
2674 case MVT::i8:
2675 Opc = NVPTX::LoadParamMemI8;
2676 break;
2677 case MVT::i16:
2678 Opc = NVPTX::LoadParamMemI16;
2679 break;
2680 case MVT::i32:
2681 Opc = NVPTX::LoadParamMemI32;
2682 break;
2683 case MVT::i64:
2684 Opc = NVPTX::LoadParamMemI64;
2685 break;
2686 case MVT::f32:
2687 Opc = NVPTX::LoadParamMemF32;
2688 break;
2689 case MVT::f64:
2690 Opc = NVPTX::LoadParamMemF64;
2691 break;
2692 }
2693 break;
2694 case 2:
2695 switch (MemVT.getSimpleVT().SimpleTy) {
2696 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2697 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2698 case MVT::i1:
2699 Opc = NVPTX::LoadParamMemV2I8;
2700 break;
2701 case MVT::i8:
2702 Opc = NVPTX::LoadParamMemV2I8;
2703 break;
2704 case MVT::i16:
2705 Opc = NVPTX::LoadParamMemV2I16;
2706 break;
2707 case MVT::i32:
2708 Opc = NVPTX::LoadParamMemV2I32;
2709 break;
2710 case MVT::i64:
2711 Opc = NVPTX::LoadParamMemV2I64;
2712 break;
2713 case MVT::f32:
2714 Opc = NVPTX::LoadParamMemV2F32;
2715 break;
2716 case MVT::f64:
2717 Opc = NVPTX::LoadParamMemV2F64;
2718 break;
2719 }
2720 break;
2721 case 4:
2722 switch (MemVT.getSimpleVT().SimpleTy) {
2723 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2724 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2725 case MVT::i1:
2726 Opc = NVPTX::LoadParamMemV4I8;
2727 break;
2728 case MVT::i8:
2729 Opc = NVPTX::LoadParamMemV4I8;
2730 break;
2731 case MVT::i16:
2732 Opc = NVPTX::LoadParamMemV4I16;
2733 break;
2734 case MVT::i32:
2735 Opc = NVPTX::LoadParamMemV4I32;
2736 break;
2737 case MVT::f32:
2738 Opc = NVPTX::LoadParamMemV4F32;
2739 break;
2740 }
2741 break;
2742 }
2743
2744 SDVTList VTs;
2745 if (VecSize == 1) {
2746 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2747 } else if (VecSize == 2) {
2748 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2749 } else {
2750 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]2751 VTs = CurDAG->getVTList(EVTs);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2752 }
2753
2754 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2755
2756 SmallVector<SDValue, 2> Ops;
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2757 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2758 Ops.push_back(Chain);
2759 Ops.push_back(Flag);
2760
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2761 return CurDAG->getMachineNode(Opc, DL, VTs, Ops);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2762}
2763
2764SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2765 SDLoc DL(N);
2766 SDValue Chain = N->getOperand(0);
2767 SDValue Offset = N->getOperand(1);
2768 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2769 MemSDNode *Mem = cast<MemSDNode>(N);
2770
2771 // How many elements do we have?
2772 unsigned NumElts = 1;
2773 switch (N->getOpcode()) {
2774 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2775 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2776 case NVPTXISD::StoreRetval:
2777 NumElts = 1;
2778 break;
2779 case NVPTXISD::StoreRetvalV2:
2780 NumElts = 2;
2781 break;
2782 case NVPTXISD::StoreRetvalV4:
2783 NumElts = 4;
2784 break;
2785 }
2786
2787 // Build vector of operands
2788 SmallVector<SDValue, 6> Ops;
2789 for (unsigned i = 0; i < NumElts; ++i)
2790 Ops.push_back(N->getOperand(i + 2));
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2791 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2792 Ops.push_back(Chain);
2793
2794 // Determine target opcode
2795 // If we have an i1, use an 8-bit store. The lowering code in
2796 // NVPTXISelLowering will have already emitted an upcast.
2797 unsigned Opcode = 0;
2798 switch (NumElts) {
2799 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2800 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2801 case 1:
2802 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2803 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2804 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2805 case MVT::i1:
2806 Opcode = NVPTX::StoreRetvalI8;
2807 break;
2808 case MVT::i8:
2809 Opcode = NVPTX::StoreRetvalI8;
2810 break;
2811 case MVT::i16:
2812 Opcode = NVPTX::StoreRetvalI16;
2813 break;
2814 case MVT::i32:
2815 Opcode = NVPTX::StoreRetvalI32;
2816 break;
2817 case MVT::i64:
2818 Opcode = NVPTX::StoreRetvalI64;
2819 break;
2820 case MVT::f32:
2821 Opcode = NVPTX::StoreRetvalF32;
2822 break;
2823 case MVT::f64:
2824 Opcode = NVPTX::StoreRetvalF64;
2825 break;
2826 }
2827 break;
2828 case 2:
2829 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2830 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2831 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2832 case MVT::i1:
2833 Opcode = NVPTX::StoreRetvalV2I8;
2834 break;
2835 case MVT::i8:
2836 Opcode = NVPTX::StoreRetvalV2I8;
2837 break;
2838 case MVT::i16:
2839 Opcode = NVPTX::StoreRetvalV2I16;
2840 break;
2841 case MVT::i32:
2842 Opcode = NVPTX::StoreRetvalV2I32;
2843 break;
2844 case MVT::i64:
2845 Opcode = NVPTX::StoreRetvalV2I64;
2846 break;
2847 case MVT::f32:
2848 Opcode = NVPTX::StoreRetvalV2F32;
2849 break;
2850 case MVT::f64:
2851 Opcode = NVPTX::StoreRetvalV2F64;
2852 break;
2853 }
2854 break;
2855 case 4:
2856 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2857 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2858 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2859 case MVT::i1:
2860 Opcode = NVPTX::StoreRetvalV4I8;
2861 break;
2862 case MVT::i8:
2863 Opcode = NVPTX::StoreRetvalV4I8;
2864 break;
2865 case MVT::i16:
2866 Opcode = NVPTX::StoreRetvalV4I16;
2867 break;
2868 case MVT::i32:
2869 Opcode = NVPTX::StoreRetvalV4I32;
2870 break;
2871 case MVT::f32:
2872 Opcode = NVPTX::StoreRetvalV4F32;
2873 break;
2874 }
2875 break;
2876 }
2877
2878 SDNode *Ret =
2879 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2880 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2881 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2882 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2883
2884 return Ret;
2885}
2886
2887SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2888 SDLoc DL(N);
2889 SDValue Chain = N->getOperand(0);
2890 SDValue Param = N->getOperand(1);
2891 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2892 SDValue Offset = N->getOperand(2);
2893 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2894 MemSDNode *Mem = cast<MemSDNode>(N);
2895 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2896
2897 // How many elements do we have?
2898 unsigned NumElts = 1;
2899 switch (N->getOpcode()) {
2900 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2901 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2902 case NVPTXISD::StoreParamU32:
2903 case NVPTXISD::StoreParamS32:
2904 case NVPTXISD::StoreParam:
2905 NumElts = 1;
2906 break;
2907 case NVPTXISD::StoreParamV2:
2908 NumElts = 2;
2909 break;
2910 case NVPTXISD::StoreParamV4:
2911 NumElts = 4;
2912 break;
2913 }
2914
2915 // Build vector of operands
2916 SmallVector<SDValue, 8> Ops;
2917 for (unsigned i = 0; i < NumElts; ++i)
2918 Ops.push_back(N->getOperand(i + 3));
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2919 Ops.push_back(CurDAG->getTargetConstant(ParamVal, DL, MVT::i32));
2920 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2921 Ops.push_back(Chain);
2922 Ops.push_back(Flag);
2923
2924 // Determine target opcode
2925 // If we have an i1, use an 8-bit store. The lowering code in
2926 // NVPTXISelLowering will have already emitted an upcast.
2927 unsigned Opcode = 0;
2928 switch (N->getOpcode()) {
2929 default:
2930 switch (NumElts) {
2931 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2932 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2933 case 1:
2934 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2935 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2936 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2937 case MVT::i1:
2938 Opcode = NVPTX::StoreParamI8;
2939 break;
2940 case MVT::i8:
2941 Opcode = NVPTX::StoreParamI8;
2942 break;
2943 case MVT::i16:
2944 Opcode = NVPTX::StoreParamI16;
2945 break;
2946 case MVT::i32:
2947 Opcode = NVPTX::StoreParamI32;
2948 break;
2949 case MVT::i64:
2950 Opcode = NVPTX::StoreParamI64;
2951 break;
2952 case MVT::f32:
2953 Opcode = NVPTX::StoreParamF32;
2954 break;
2955 case MVT::f64:
2956 Opcode = NVPTX::StoreParamF64;
2957 break;
2958 }
2959 break;
2960 case 2:
2961 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2962 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2963 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2964 case MVT::i1:
2965 Opcode = NVPTX::StoreParamV2I8;
2966 break;
2967 case MVT::i8:
2968 Opcode = NVPTX::StoreParamV2I8;
2969 break;
2970 case MVT::i16:
2971 Opcode = NVPTX::StoreParamV2I16;
2972 break;
2973 case MVT::i32:
2974 Opcode = NVPTX::StoreParamV2I32;
2975 break;
2976 case MVT::i64:
2977 Opcode = NVPTX::StoreParamV2I64;
2978 break;
2979 case MVT::f32:
2980 Opcode = NVPTX::StoreParamV2F32;
2981 break;
2982 case MVT::f64:
2983 Opcode = NVPTX::StoreParamV2F64;
2984 break;
2985 }
2986 break;
2987 case 4:
2988 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2989 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2990 return nullptr;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2991 case MVT::i1:
2992 Opcode = NVPTX::StoreParamV4I8;
2993 break;
2994 case MVT::i8:
2995 Opcode = NVPTX::StoreParamV4I8;
2996 break;
2997 case MVT::i16:
2998 Opcode = NVPTX::StoreParamV4I16;
2999 break;
3000 case MVT::i32:
3001 Opcode = NVPTX::StoreParamV4I32;
3002 break;
3003 case MVT::f32:
3004 Opcode = NVPTX::StoreParamV4F32;
3005 break;
3006 }
3007 break;
3008 }
3009 break;
Justin Holewinskidc5e3b62013-06-28 17:58:04 +0000[diff] [blame]3010 // Special case: if we have a sign-extend/zero-extend node, insert the
3011 // conversion instruction first, and use that as the value operand to
3012 // the selected StoreParam node.
3013 case NVPTXISD::StoreParamU32: {
3014 Opcode = NVPTX::StoreParamI32;
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]3015 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
Justin Holewinskidc5e3b62013-06-28 17:58:04 +0000[diff] [blame]3016 MVT::i32);
3017 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
3018 MVT::i32, Ops[0], CvtNone);
3019 Ops[0] = SDValue(Cvt, 0);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3020 break;
Justin Holewinskidc5e3b62013-06-28 17:58:04 +0000[diff] [blame]3021 }
3022 case NVPTXISD::StoreParamS32: {
3023 Opcode = NVPTX::StoreParamI32;
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]3024 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
Justin Holewinskidc5e3b62013-06-28 17:58:04 +0000[diff] [blame]3025 MVT::i32);
3026 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
3027 MVT::i32, Ops[0], CvtNone);
3028 Ops[0] = SDValue(Cvt, 0);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3029 break;
3030 }
Justin Holewinskidc5e3b62013-06-28 17:58:04 +0000[diff] [blame]3031 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3032
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]3033 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3034 SDNode *Ret =
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]3035 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3036 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
3037 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
3038 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3039
3040 return Ret;
3041}
3042
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3043SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
3044 SDValue Chain = N->getOperand(0);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3045 SDNode *Ret = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3046 unsigned Opc = 0;
3047 SmallVector<SDValue, 8> Ops;
3048
3049 switch (N->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3050 default: return nullptr;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3051 case NVPTXISD::Tex1DFloatS32:
3052 Opc = NVPTX::TEX_1D_F32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3053 break;
3054 case NVPTXISD::Tex1DFloatFloat:
3055 Opc = NVPTX::TEX_1D_F32_F32;
3056 break;
3057 case NVPTXISD::Tex1DFloatFloatLevel:
3058 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3059 break;
3060 case NVPTXISD::Tex1DFloatFloatGrad:
3061 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3062 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3063 case NVPTXISD::Tex1DS32S32:
3064 Opc = NVPTX::TEX_1D_S32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3065 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3066 case NVPTXISD::Tex1DS32Float:
3067 Opc = NVPTX::TEX_1D_S32_F32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3068 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3069 case NVPTXISD::Tex1DS32FloatLevel:
3070 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3071 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3072 case NVPTXISD::Tex1DS32FloatGrad:
3073 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3074 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3075 case NVPTXISD::Tex1DU32S32:
3076 Opc = NVPTX::TEX_1D_U32_S32;
3077 break;
3078 case NVPTXISD::Tex1DU32Float:
3079 Opc = NVPTX::TEX_1D_U32_F32;
3080 break;
3081 case NVPTXISD::Tex1DU32FloatLevel:
3082 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3083 break;
3084 case NVPTXISD::Tex1DU32FloatGrad:
3085 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3086 break;
3087 case NVPTXISD::Tex1DArrayFloatS32:
3088 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3089 break;
3090 case NVPTXISD::Tex1DArrayFloatFloat:
3091 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3092 break;
3093 case NVPTXISD::Tex1DArrayFloatFloatLevel:
3094 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3095 break;
3096 case NVPTXISD::Tex1DArrayFloatFloatGrad:
3097 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3098 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3099 case NVPTXISD::Tex1DArrayS32S32:
3100 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3101 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3102 case NVPTXISD::Tex1DArrayS32Float:
3103 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3104 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3105 case NVPTXISD::Tex1DArrayS32FloatLevel:
3106 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3107 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3108 case NVPTXISD::Tex1DArrayS32FloatGrad:
3109 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3110 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3111 case NVPTXISD::Tex1DArrayU32S32:
3112 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3113 break;
3114 case NVPTXISD::Tex1DArrayU32Float:
3115 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3116 break;
3117 case NVPTXISD::Tex1DArrayU32FloatLevel:
3118 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3119 break;
3120 case NVPTXISD::Tex1DArrayU32FloatGrad:
3121 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3122 break;
3123 case NVPTXISD::Tex2DFloatS32:
3124 Opc = NVPTX::TEX_2D_F32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3125 break;
3126 case NVPTXISD::Tex2DFloatFloat:
3127 Opc = NVPTX::TEX_2D_F32_F32;
3128 break;
3129 case NVPTXISD::Tex2DFloatFloatLevel:
3130 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3131 break;
3132 case NVPTXISD::Tex2DFloatFloatGrad:
3133 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3134 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3135 case NVPTXISD::Tex2DS32S32:
3136 Opc = NVPTX::TEX_2D_S32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3137 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3138 case NVPTXISD::Tex2DS32Float:
3139 Opc = NVPTX::TEX_2D_S32_F32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3140 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3141 case NVPTXISD::Tex2DS32FloatLevel:
3142 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3143 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3144 case NVPTXISD::Tex2DS32FloatGrad:
3145 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3146 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3147 case NVPTXISD::Tex2DU32S32:
3148 Opc = NVPTX::TEX_2D_U32_S32;
3149 break;
3150 case NVPTXISD::Tex2DU32Float:
3151 Opc = NVPTX::TEX_2D_U32_F32;
3152 break;
3153 case NVPTXISD::Tex2DU32FloatLevel:
3154 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3155 break;
3156 case NVPTXISD::Tex2DU32FloatGrad:
3157 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3158 break;
3159 case NVPTXISD::Tex2DArrayFloatS32:
3160 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3161 break;
3162 case NVPTXISD::Tex2DArrayFloatFloat:
3163 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3164 break;
3165 case NVPTXISD::Tex2DArrayFloatFloatLevel:
3166 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3167 break;
3168 case NVPTXISD::Tex2DArrayFloatFloatGrad:
3169 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3170 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3171 case NVPTXISD::Tex2DArrayS32S32:
3172 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3173 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3174 case NVPTXISD::Tex2DArrayS32Float:
3175 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3176 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3177 case NVPTXISD::Tex2DArrayS32FloatLevel:
3178 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3179 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3180 case NVPTXISD::Tex2DArrayS32FloatGrad:
3181 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3182 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3183 case NVPTXISD::Tex2DArrayU32S32:
3184 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3185 break;
3186 case NVPTXISD::Tex2DArrayU32Float:
3187 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3188 break;
3189 case NVPTXISD::Tex2DArrayU32FloatLevel:
3190 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3191 break;
3192 case NVPTXISD::Tex2DArrayU32FloatGrad:
3193 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3194 break;
3195 case NVPTXISD::Tex3DFloatS32:
3196 Opc = NVPTX::TEX_3D_F32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3197 break;
3198 case NVPTXISD::Tex3DFloatFloat:
3199 Opc = NVPTX::TEX_3D_F32_F32;
3200 break;
3201 case NVPTXISD::Tex3DFloatFloatLevel:
3202 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3203 break;
3204 case NVPTXISD::Tex3DFloatFloatGrad:
3205 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3206 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3207 case NVPTXISD::Tex3DS32S32:
3208 Opc = NVPTX::TEX_3D_S32_S32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3209 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3210 case NVPTXISD::Tex3DS32Float:
3211 Opc = NVPTX::TEX_3D_S32_F32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3212 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3213 case NVPTXISD::Tex3DS32FloatLevel:
3214 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3215 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3216 case NVPTXISD::Tex3DS32FloatGrad:
3217 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3218 break;
3219 case NVPTXISD::Tex3DU32S32:
3220 Opc = NVPTX::TEX_3D_U32_S32;
3221 break;
3222 case NVPTXISD::Tex3DU32Float:
3223 Opc = NVPTX::TEX_3D_U32_F32;
3224 break;
3225 case NVPTXISD::Tex3DU32FloatLevel:
3226 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3227 break;
3228 case NVPTXISD::Tex3DU32FloatGrad:
3229 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3230 break;
3231 case NVPTXISD::TexCubeFloatFloat:
3232 Opc = NVPTX::TEX_CUBE_F32_F32;
3233 break;
3234 case NVPTXISD::TexCubeFloatFloatLevel:
3235 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3236 break;
3237 case NVPTXISD::TexCubeS32Float:
3238 Opc = NVPTX::TEX_CUBE_S32_F32;
3239 break;
3240 case NVPTXISD::TexCubeS32FloatLevel:
3241 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3242 break;
3243 case NVPTXISD::TexCubeU32Float:
3244 Opc = NVPTX::TEX_CUBE_U32_F32;
3245 break;
3246 case NVPTXISD::TexCubeU32FloatLevel:
3247 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3248 break;
3249 case NVPTXISD::TexCubeArrayFloatFloat:
3250 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3251 break;
3252 case NVPTXISD::TexCubeArrayFloatFloatLevel:
3253 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3254 break;
3255 case NVPTXISD::TexCubeArrayS32Float:
3256 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3257 break;
3258 case NVPTXISD::TexCubeArrayS32FloatLevel:
3259 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3260 break;
3261 case NVPTXISD::TexCubeArrayU32Float:
3262 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3263 break;
3264 case NVPTXISD::TexCubeArrayU32FloatLevel:
3265 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3266 break;
3267 case NVPTXISD::Tld4R2DFloatFloat:
3268 Opc = NVPTX::TLD4_R_2D_F32_F32;
3269 break;
3270 case NVPTXISD::Tld4G2DFloatFloat:
3271 Opc = NVPTX::TLD4_G_2D_F32_F32;
3272 break;
3273 case NVPTXISD::Tld4B2DFloatFloat:
3274 Opc = NVPTX::TLD4_B_2D_F32_F32;
3275 break;
3276 case NVPTXISD::Tld4A2DFloatFloat:
3277 Opc = NVPTX::TLD4_A_2D_F32_F32;
3278 break;
3279 case NVPTXISD::Tld4R2DS64Float:
3280 Opc = NVPTX::TLD4_R_2D_S32_F32;
3281 break;
3282 case NVPTXISD::Tld4G2DS64Float:
3283 Opc = NVPTX::TLD4_G_2D_S32_F32;
3284 break;
3285 case NVPTXISD::Tld4B2DS64Float:
3286 Opc = NVPTX::TLD4_B_2D_S32_F32;
3287 break;
3288 case NVPTXISD::Tld4A2DS64Float:
3289 Opc = NVPTX::TLD4_A_2D_S32_F32;
3290 break;
3291 case NVPTXISD::Tld4R2DU64Float:
3292 Opc = NVPTX::TLD4_R_2D_U32_F32;
3293 break;
3294 case NVPTXISD::Tld4G2DU64Float:
3295 Opc = NVPTX::TLD4_G_2D_U32_F32;
3296 break;
3297 case NVPTXISD::Tld4B2DU64Float:
3298 Opc = NVPTX::TLD4_B_2D_U32_F32;
3299 break;
3300 case NVPTXISD::Tld4A2DU64Float:
3301 Opc = NVPTX::TLD4_A_2D_U32_F32;
3302 break;
3303 case NVPTXISD::TexUnified1DFloatS32:
3304 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3305 break;
3306 case NVPTXISD::TexUnified1DFloatFloat:
3307 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3308 break;
3309 case NVPTXISD::TexUnified1DFloatFloatLevel:
3310 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3311 break;
3312 case NVPTXISD::TexUnified1DFloatFloatGrad:
3313 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3314 break;
3315 case NVPTXISD::TexUnified1DS32S32:
3316 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3317 break;
3318 case NVPTXISD::TexUnified1DS32Float:
3319 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3320 break;
3321 case NVPTXISD::TexUnified1DS32FloatLevel:
3322 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3323 break;
3324 case NVPTXISD::TexUnified1DS32FloatGrad:
3325 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3326 break;
3327 case NVPTXISD::TexUnified1DU32S32:
3328 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3329 break;
3330 case NVPTXISD::TexUnified1DU32Float:
3331 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3332 break;
3333 case NVPTXISD::TexUnified1DU32FloatLevel:
3334 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3335 break;
3336 case NVPTXISD::TexUnified1DU32FloatGrad:
3337 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3338 break;
3339 case NVPTXISD::TexUnified1DArrayFloatS32:
3340 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3341 break;
3342 case NVPTXISD::TexUnified1DArrayFloatFloat:
3343 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3344 break;
3345 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
3346 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3347 break;
3348 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
3349 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3350 break;
3351 case NVPTXISD::TexUnified1DArrayS32S32:
3352 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3353 break;
3354 case NVPTXISD::TexUnified1DArrayS32Float:
3355 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3356 break;
3357 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
3358 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3359 break;
3360 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
3361 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3362 break;
3363 case NVPTXISD::TexUnified1DArrayU32S32:
3364 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3365 break;
3366 case NVPTXISD::TexUnified1DArrayU32Float:
3367 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3368 break;
3369 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
3370 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3371 break;
3372 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
3373 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3374 break;
3375 case NVPTXISD::TexUnified2DFloatS32:
3376 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3377 break;
3378 case NVPTXISD::TexUnified2DFloatFloat:
3379 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3380 break;
3381 case NVPTXISD::TexUnified2DFloatFloatLevel:
3382 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3383 break;
3384 case NVPTXISD::TexUnified2DFloatFloatGrad:
3385 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3386 break;
3387 case NVPTXISD::TexUnified2DS32S32:
3388 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3389 break;
3390 case NVPTXISD::TexUnified2DS32Float:
3391 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3392 break;
3393 case NVPTXISD::TexUnified2DS32FloatLevel:
3394 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3395 break;
3396 case NVPTXISD::TexUnified2DS32FloatGrad:
3397 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3398 break;
3399 case NVPTXISD::TexUnified2DU32S32:
3400 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3401 break;
3402 case NVPTXISD::TexUnified2DU32Float:
3403 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3404 break;
3405 case NVPTXISD::TexUnified2DU32FloatLevel:
3406 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3407 break;
3408 case NVPTXISD::TexUnified2DU32FloatGrad:
3409 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3410 break;
3411 case NVPTXISD::TexUnified2DArrayFloatS32:
3412 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3413 break;
3414 case NVPTXISD::TexUnified2DArrayFloatFloat:
3415 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3416 break;
3417 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
3418 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3419 break;
3420 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
3421 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3422 break;
3423 case NVPTXISD::TexUnified2DArrayS32S32:
3424 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3425 break;
3426 case NVPTXISD::TexUnified2DArrayS32Float:
3427 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3428 break;
3429 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
3430 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3431 break;
3432 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
3433 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3434 break;
3435 case NVPTXISD::TexUnified2DArrayU32S32:
3436 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3437 break;
3438 case NVPTXISD::TexUnified2DArrayU32Float:
3439 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3440 break;
3441 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
3442 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3443 break;
3444 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
3445 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3446 break;
3447 case NVPTXISD::TexUnified3DFloatS32:
3448 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3449 break;
3450 case NVPTXISD::TexUnified3DFloatFloat:
3451 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3452 break;
3453 case NVPTXISD::TexUnified3DFloatFloatLevel:
3454 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3455 break;
3456 case NVPTXISD::TexUnified3DFloatFloatGrad:
3457 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3458 break;
3459 case NVPTXISD::TexUnified3DS32S32:
3460 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3461 break;
3462 case NVPTXISD::TexUnified3DS32Float:
3463 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3464 break;
3465 case NVPTXISD::TexUnified3DS32FloatLevel:
3466 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3467 break;
3468 case NVPTXISD::TexUnified3DS32FloatGrad:
3469 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3470 break;
3471 case NVPTXISD::TexUnified3DU32S32:
3472 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3473 break;
3474 case NVPTXISD::TexUnified3DU32Float:
3475 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3476 break;
3477 case NVPTXISD::TexUnified3DU32FloatLevel:
3478 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3479 break;
3480 case NVPTXISD::TexUnified3DU32FloatGrad:
3481 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3482 break;
3483 case NVPTXISD::TexUnifiedCubeFloatFloat:
3484 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3485 break;
3486 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
3487 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3488 break;
3489 case NVPTXISD::TexUnifiedCubeS32Float:
3490 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3491 break;
3492 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
3493 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3494 break;
3495 case NVPTXISD::TexUnifiedCubeU32Float:
3496 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3497 break;
3498 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
3499 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3500 break;
3501 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
3502 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3503 break;
3504 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
3505 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3506 break;
3507 case NVPTXISD::TexUnifiedCubeArrayS32Float:
3508 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3509 break;
3510 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
3511 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3512 break;
3513 case NVPTXISD::TexUnifiedCubeArrayU32Float:
3514 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3515 break;
3516 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
3517 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3518 break;
3519 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
3520 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3521 break;
3522 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
3523 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3524 break;
3525 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
3526 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3527 break;
3528 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
3529 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3530 break;
3531 case NVPTXISD::Tld4UnifiedR2DS64Float:
3532 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3533 break;
3534 case NVPTXISD::Tld4UnifiedG2DS64Float:
3535 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3536 break;
3537 case NVPTXISD::Tld4UnifiedB2DS64Float:
3538 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3539 break;
3540 case NVPTXISD::Tld4UnifiedA2DS64Float:
3541 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3542 break;
3543 case NVPTXISD::Tld4UnifiedR2DU64Float:
3544 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3545 break;
3546 case NVPTXISD::Tld4UnifiedG2DU64Float:
3547 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3548 break;
3549 case NVPTXISD::Tld4UnifiedB2DU64Float:
3550 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3551 break;
3552 case NVPTXISD::Tld4UnifiedA2DU64Float:
3553 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3554 break;
3555 }
3556
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3557 // Copy over operands
3558 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3559 Ops.push_back(N->getOperand(i));
3560 }
3561
3562 Ops.push_back(Chain);
3563 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
3564 return Ret;
3565}
3566
3567SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
3568 SDValue Chain = N->getOperand(0);
3569 SDValue TexHandle = N->getOperand(1);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3570 SDNode *Ret = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3571 unsigned Opc = 0;
3572 SmallVector<SDValue, 8> Ops;
3573 switch (N->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3574 default: return nullptr;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3575 case NVPTXISD::Suld1DI8Clamp:
3576 Opc = NVPTX::SULD_1D_I8_CLAMP;
3577 Ops.push_back(TexHandle);
3578 Ops.push_back(N->getOperand(2));
3579 Ops.push_back(Chain);
3580 break;
3581 case NVPTXISD::Suld1DI16Clamp:
3582 Opc = NVPTX::SULD_1D_I16_CLAMP;
3583 Ops.push_back(TexHandle);
3584 Ops.push_back(N->getOperand(2));
3585 Ops.push_back(Chain);
3586 break;
3587 case NVPTXISD::Suld1DI32Clamp:
3588 Opc = NVPTX::SULD_1D_I32_CLAMP;
3589 Ops.push_back(TexHandle);
3590 Ops.push_back(N->getOperand(2));
3591 Ops.push_back(Chain);
3592 break;
3593 case NVPTXISD::Suld1DI64Clamp:
3594 Opc = NVPTX::SULD_1D_I64_CLAMP;
3595 Ops.push_back(TexHandle);
3596 Ops.push_back(N->getOperand(2));
3597 Ops.push_back(Chain);
3598 break;
3599 case NVPTXISD::Suld1DV2I8Clamp:
3600 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3601 Ops.push_back(TexHandle);
3602 Ops.push_back(N->getOperand(2));
3603 Ops.push_back(Chain);
3604 break;
3605 case NVPTXISD::Suld1DV2I16Clamp:
3606 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3607 Ops.push_back(TexHandle);
3608 Ops.push_back(N->getOperand(2));
3609 Ops.push_back(Chain);
3610 break;
3611 case NVPTXISD::Suld1DV2I32Clamp:
3612 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3613 Ops.push_back(TexHandle);
3614 Ops.push_back(N->getOperand(2));
3615 Ops.push_back(Chain);
3616 break;
3617 case NVPTXISD::Suld1DV2I64Clamp:
3618 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3619 Ops.push_back(TexHandle);
3620 Ops.push_back(N->getOperand(2));
3621 Ops.push_back(Chain);
3622 break;
3623 case NVPTXISD::Suld1DV4I8Clamp:
3624 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3625 Ops.push_back(TexHandle);
3626 Ops.push_back(N->getOperand(2));
3627 Ops.push_back(Chain);
3628 break;
3629 case NVPTXISD::Suld1DV4I16Clamp:
3630 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3631 Ops.push_back(TexHandle);
3632 Ops.push_back(N->getOperand(2));
3633 Ops.push_back(Chain);
3634 break;
3635 case NVPTXISD::Suld1DV4I32Clamp:
3636 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3637 Ops.push_back(TexHandle);
3638 Ops.push_back(N->getOperand(2));
3639 Ops.push_back(Chain);
3640 break;
3641 case NVPTXISD::Suld1DArrayI8Clamp:
3642 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3643 Ops.push_back(TexHandle);
3644 Ops.push_back(N->getOperand(2));
3645 Ops.push_back(N->getOperand(3));
3646 Ops.push_back(Chain);
3647 break;
3648 case NVPTXISD::Suld1DArrayI16Clamp:
3649 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3650 Ops.push_back(TexHandle);
3651 Ops.push_back(N->getOperand(2));
3652 Ops.push_back(N->getOperand(3));
3653 Ops.push_back(Chain);
3654 break;
3655 case NVPTXISD::Suld1DArrayI32Clamp:
3656 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3657 Ops.push_back(TexHandle);
3658 Ops.push_back(N->getOperand(2));
3659 Ops.push_back(N->getOperand(3));
3660 Ops.push_back(Chain);
3661 break;
3662 case NVPTXISD::Suld1DArrayI64Clamp:
3663 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3664 Ops.push_back(TexHandle);
3665 Ops.push_back(N->getOperand(2));
3666 Ops.push_back(N->getOperand(3));
3667 Ops.push_back(Chain);
3668 break;
3669 case NVPTXISD::Suld1DArrayV2I8Clamp:
3670 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3671 Ops.push_back(TexHandle);
3672 Ops.push_back(N->getOperand(2));
3673 Ops.push_back(N->getOperand(3));
3674 Ops.push_back(Chain);
3675 break;
3676 case NVPTXISD::Suld1DArrayV2I16Clamp:
3677 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3678 Ops.push_back(TexHandle);
3679 Ops.push_back(N->getOperand(2));
3680 Ops.push_back(N->getOperand(3));
3681 Ops.push_back(Chain);
3682 break;
3683 case NVPTXISD::Suld1DArrayV2I32Clamp:
3684 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3685 Ops.push_back(TexHandle);
3686 Ops.push_back(N->getOperand(2));
3687 Ops.push_back(N->getOperand(3));
3688 Ops.push_back(Chain);
3689 break;
3690 case NVPTXISD::Suld1DArrayV2I64Clamp:
3691 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3692 Ops.push_back(TexHandle);
3693 Ops.push_back(N->getOperand(2));
3694 Ops.push_back(N->getOperand(3));
3695 Ops.push_back(Chain);
3696 break;
3697 case NVPTXISD::Suld1DArrayV4I8Clamp:
3698 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3699 Ops.push_back(TexHandle);
3700 Ops.push_back(N->getOperand(2));
3701 Ops.push_back(N->getOperand(3));
3702 Ops.push_back(Chain);
3703 break;
3704 case NVPTXISD::Suld1DArrayV4I16Clamp:
3705 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3706 Ops.push_back(TexHandle);
3707 Ops.push_back(N->getOperand(2));
3708 Ops.push_back(N->getOperand(3));
3709 Ops.push_back(Chain);
3710 break;
3711 case NVPTXISD::Suld1DArrayV4I32Clamp:
3712 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3713 Ops.push_back(TexHandle);
3714 Ops.push_back(N->getOperand(2));
3715 Ops.push_back(N->getOperand(3));
3716 Ops.push_back(Chain);
3717 break;
3718 case NVPTXISD::Suld2DI8Clamp:
3719 Opc = NVPTX::SULD_2D_I8_CLAMP;
3720 Ops.push_back(TexHandle);
3721 Ops.push_back(N->getOperand(2));
3722 Ops.push_back(N->getOperand(3));
3723 Ops.push_back(Chain);
3724 break;
3725 case NVPTXISD::Suld2DI16Clamp:
3726 Opc = NVPTX::SULD_2D_I16_CLAMP;
3727 Ops.push_back(TexHandle);
3728 Ops.push_back(N->getOperand(2));
3729 Ops.push_back(N->getOperand(3));
3730 Ops.push_back(Chain);
3731 break;
3732 case NVPTXISD::Suld2DI32Clamp:
3733 Opc = NVPTX::SULD_2D_I32_CLAMP;
3734 Ops.push_back(TexHandle);
3735 Ops.push_back(N->getOperand(2));
3736 Ops.push_back(N->getOperand(3));
3737 Ops.push_back(Chain);
3738 break;
3739 case NVPTXISD::Suld2DI64Clamp:
3740 Opc = NVPTX::SULD_2D_I64_CLAMP;
3741 Ops.push_back(TexHandle);
3742 Ops.push_back(N->getOperand(2));
3743 Ops.push_back(N->getOperand(3));
3744 Ops.push_back(Chain);
3745 break;
3746 case NVPTXISD::Suld2DV2I8Clamp:
3747 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3748 Ops.push_back(TexHandle);
3749 Ops.push_back(N->getOperand(2));
3750 Ops.push_back(N->getOperand(3));
3751 Ops.push_back(Chain);
3752 break;
3753 case NVPTXISD::Suld2DV2I16Clamp:
3754 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3755 Ops.push_back(TexHandle);
3756 Ops.push_back(N->getOperand(2));
3757 Ops.push_back(N->getOperand(3));
3758 Ops.push_back(Chain);
3759 break;
3760 case NVPTXISD::Suld2DV2I32Clamp:
3761 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3762 Ops.push_back(TexHandle);
3763 Ops.push_back(N->getOperand(2));
3764 Ops.push_back(N->getOperand(3));
3765 Ops.push_back(Chain);
3766 break;
3767 case NVPTXISD::Suld2DV2I64Clamp:
3768 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3769 Ops.push_back(TexHandle);
3770 Ops.push_back(N->getOperand(2));
3771 Ops.push_back(N->getOperand(3));
3772 Ops.push_back(Chain);
3773 break;
3774 case NVPTXISD::Suld2DV4I8Clamp:
3775 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3776 Ops.push_back(TexHandle);
3777 Ops.push_back(N->getOperand(2));
3778 Ops.push_back(N->getOperand(3));
3779 Ops.push_back(Chain);
3780 break;
3781 case NVPTXISD::Suld2DV4I16Clamp:
3782 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3783 Ops.push_back(TexHandle);
3784 Ops.push_back(N->getOperand(2));
3785 Ops.push_back(N->getOperand(3));
3786 Ops.push_back(Chain);
3787 break;
3788 case NVPTXISD::Suld2DV4I32Clamp:
3789 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3790 Ops.push_back(TexHandle);
3791 Ops.push_back(N->getOperand(2));
3792 Ops.push_back(N->getOperand(3));
3793 Ops.push_back(Chain);
3794 break;
3795 case NVPTXISD::Suld2DArrayI8Clamp:
3796 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3797 Ops.push_back(TexHandle);
3798 Ops.push_back(N->getOperand(2));
3799 Ops.push_back(N->getOperand(3));
3800 Ops.push_back(N->getOperand(4));
3801 Ops.push_back(Chain);
3802 break;
3803 case NVPTXISD::Suld2DArrayI16Clamp:
3804 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3805 Ops.push_back(TexHandle);
3806 Ops.push_back(N->getOperand(2));
3807 Ops.push_back(N->getOperand(3));
3808 Ops.push_back(N->getOperand(4));
3809 Ops.push_back(Chain);
3810 break;
3811 case NVPTXISD::Suld2DArrayI32Clamp:
3812 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3813 Ops.push_back(TexHandle);
3814 Ops.push_back(N->getOperand(2));
3815 Ops.push_back(N->getOperand(3));
3816 Ops.push_back(N->getOperand(4));
3817 Ops.push_back(Chain);
3818 break;
3819 case NVPTXISD::Suld2DArrayI64Clamp:
3820 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3821 Ops.push_back(TexHandle);
3822 Ops.push_back(N->getOperand(2));
3823 Ops.push_back(N->getOperand(3));
3824 Ops.push_back(N->getOperand(4));
3825 Ops.push_back(Chain);
3826 break;
3827 case NVPTXISD::Suld2DArrayV2I8Clamp:
3828 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3829 Ops.push_back(TexHandle);
3830 Ops.push_back(N->getOperand(2));
3831 Ops.push_back(N->getOperand(3));
3832 Ops.push_back(N->getOperand(4));
3833 Ops.push_back(Chain);
3834 break;
3835 case NVPTXISD::Suld2DArrayV2I16Clamp:
3836 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3837 Ops.push_back(TexHandle);
3838 Ops.push_back(N->getOperand(2));
3839 Ops.push_back(N->getOperand(3));
3840 Ops.push_back(N->getOperand(4));
3841 Ops.push_back(Chain);
3842 break;
3843 case NVPTXISD::Suld2DArrayV2I32Clamp:
3844 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3845 Ops.push_back(TexHandle);
3846 Ops.push_back(N->getOperand(2));
3847 Ops.push_back(N->getOperand(3));
3848 Ops.push_back(N->getOperand(4));
3849 Ops.push_back(Chain);
3850 break;
3851 case NVPTXISD::Suld2DArrayV2I64Clamp:
3852 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3853 Ops.push_back(TexHandle);
3854 Ops.push_back(N->getOperand(2));
3855 Ops.push_back(N->getOperand(3));
3856 Ops.push_back(N->getOperand(4));
3857 Ops.push_back(Chain);
3858 break;
3859 case NVPTXISD::Suld2DArrayV4I8Clamp:
3860 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3861 Ops.push_back(TexHandle);
3862 Ops.push_back(N->getOperand(2));
3863 Ops.push_back(N->getOperand(3));
3864 Ops.push_back(N->getOperand(4));
3865 Ops.push_back(Chain);
3866 break;
3867 case NVPTXISD::Suld2DArrayV4I16Clamp:
3868 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3869 Ops.push_back(TexHandle);
3870 Ops.push_back(N->getOperand(2));
3871 Ops.push_back(N->getOperand(3));
3872 Ops.push_back(N->getOperand(4));
3873 Ops.push_back(Chain);
3874 break;
3875 case NVPTXISD::Suld2DArrayV4I32Clamp:
3876 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3877 Ops.push_back(TexHandle);
3878 Ops.push_back(N->getOperand(2));
3879 Ops.push_back(N->getOperand(3));
3880 Ops.push_back(N->getOperand(4));
3881 Ops.push_back(Chain);
3882 break;
3883 case NVPTXISD::Suld3DI8Clamp:
3884 Opc = NVPTX::SULD_3D_I8_CLAMP;
3885 Ops.push_back(TexHandle);
3886 Ops.push_back(N->getOperand(2));
3887 Ops.push_back(N->getOperand(3));
3888 Ops.push_back(N->getOperand(4));
3889 Ops.push_back(Chain);
3890 break;
3891 case NVPTXISD::Suld3DI16Clamp:
3892 Opc = NVPTX::SULD_3D_I16_CLAMP;
3893 Ops.push_back(TexHandle);
3894 Ops.push_back(N->getOperand(2));
3895 Ops.push_back(N->getOperand(3));
3896 Ops.push_back(N->getOperand(4));
3897 Ops.push_back(Chain);
3898 break;
3899 case NVPTXISD::Suld3DI32Clamp:
3900 Opc = NVPTX::SULD_3D_I32_CLAMP;
3901 Ops.push_back(TexHandle);
3902 Ops.push_back(N->getOperand(2));
3903 Ops.push_back(N->getOperand(3));
3904 Ops.push_back(N->getOperand(4));
3905 Ops.push_back(Chain);
3906 break;
3907 case NVPTXISD::Suld3DI64Clamp:
3908 Opc = NVPTX::SULD_3D_I64_CLAMP;
3909 Ops.push_back(TexHandle);
3910 Ops.push_back(N->getOperand(2));
3911 Ops.push_back(N->getOperand(3));
3912 Ops.push_back(N->getOperand(4));
3913 Ops.push_back(Chain);
3914 break;
3915 case NVPTXISD::Suld3DV2I8Clamp:
3916 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
3917 Ops.push_back(TexHandle);
3918 Ops.push_back(N->getOperand(2));
3919 Ops.push_back(N->getOperand(3));
3920 Ops.push_back(N->getOperand(4));
3921 Ops.push_back(Chain);
3922 break;
3923 case NVPTXISD::Suld3DV2I16Clamp:
3924 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
3925 Ops.push_back(TexHandle);
3926 Ops.push_back(N->getOperand(2));
3927 Ops.push_back(N->getOperand(3));
3928 Ops.push_back(N->getOperand(4));
3929 Ops.push_back(Chain);
3930 break;
3931 case NVPTXISD::Suld3DV2I32Clamp:
3932 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
3933 Ops.push_back(TexHandle);
3934 Ops.push_back(N->getOperand(2));
3935 Ops.push_back(N->getOperand(3));
3936 Ops.push_back(N->getOperand(4));
3937 Ops.push_back(Chain);
3938 break;
3939 case NVPTXISD::Suld3DV2I64Clamp:
3940 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
3941 Ops.push_back(TexHandle);
3942 Ops.push_back(N->getOperand(2));
3943 Ops.push_back(N->getOperand(3));
3944 Ops.push_back(N->getOperand(4));
3945 Ops.push_back(Chain);
3946 break;
3947 case NVPTXISD::Suld3DV4I8Clamp:
3948 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
3949 Ops.push_back(TexHandle);
3950 Ops.push_back(N->getOperand(2));
3951 Ops.push_back(N->getOperand(3));
3952 Ops.push_back(N->getOperand(4));
3953 Ops.push_back(Chain);
3954 break;
3955 case NVPTXISD::Suld3DV4I16Clamp:
3956 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
3957 Ops.push_back(TexHandle);
3958 Ops.push_back(N->getOperand(2));
3959 Ops.push_back(N->getOperand(3));
3960 Ops.push_back(N->getOperand(4));
3961 Ops.push_back(Chain);
3962 break;
3963 case NVPTXISD::Suld3DV4I32Clamp:
3964 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
3965 Ops.push_back(TexHandle);
3966 Ops.push_back(N->getOperand(2));
3967 Ops.push_back(N->getOperand(3));
3968 Ops.push_back(N->getOperand(4));
3969 Ops.push_back(Chain);
3970 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3971 case NVPTXISD::Suld1DI8Trap:
3972 Opc = NVPTX::SULD_1D_I8_TRAP;
3973 Ops.push_back(TexHandle);
3974 Ops.push_back(N->getOperand(2));
3975 Ops.push_back(Chain);
3976 break;
3977 case NVPTXISD::Suld1DI16Trap:
3978 Opc = NVPTX::SULD_1D_I16_TRAP;
3979 Ops.push_back(TexHandle);
3980 Ops.push_back(N->getOperand(2));
3981 Ops.push_back(Chain);
3982 break;
3983 case NVPTXISD::Suld1DI32Trap:
3984 Opc = NVPTX::SULD_1D_I32_TRAP;
3985 Ops.push_back(TexHandle);
3986 Ops.push_back(N->getOperand(2));
3987 Ops.push_back(Chain);
3988 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]3989 case NVPTXISD::Suld1DI64Trap:
3990 Opc = NVPTX::SULD_1D_I64_TRAP;
3991 Ops.push_back(TexHandle);
3992 Ops.push_back(N->getOperand(2));
3993 Ops.push_back(Chain);
3994 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]3995 case NVPTXISD::Suld1DV2I8Trap:
3996 Opc = NVPTX::SULD_1D_V2I8_TRAP;
3997 Ops.push_back(TexHandle);
3998 Ops.push_back(N->getOperand(2));
3999 Ops.push_back(Chain);
4000 break;
4001 case NVPTXISD::Suld1DV2I16Trap:
4002 Opc = NVPTX::SULD_1D_V2I16_TRAP;
4003 Ops.push_back(TexHandle);
4004 Ops.push_back(N->getOperand(2));
4005 Ops.push_back(Chain);
4006 break;
4007 case NVPTXISD::Suld1DV2I32Trap:
4008 Opc = NVPTX::SULD_1D_V2I32_TRAP;
4009 Ops.push_back(TexHandle);
4010 Ops.push_back(N->getOperand(2));
4011 Ops.push_back(Chain);
4012 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4013 case NVPTXISD::Suld1DV2I64Trap:
4014 Opc = NVPTX::SULD_1D_V2I64_TRAP;
4015 Ops.push_back(TexHandle);
4016 Ops.push_back(N->getOperand(2));
4017 Ops.push_back(Chain);
4018 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4019 case NVPTXISD::Suld1DV4I8Trap:
4020 Opc = NVPTX::SULD_1D_V4I8_TRAP;
4021 Ops.push_back(TexHandle);
4022 Ops.push_back(N->getOperand(2));
4023 Ops.push_back(Chain);
4024 break;
4025 case NVPTXISD::Suld1DV4I16Trap:
4026 Opc = NVPTX::SULD_1D_V4I16_TRAP;
4027 Ops.push_back(TexHandle);
4028 Ops.push_back(N->getOperand(2));
4029 Ops.push_back(Chain);
4030 break;
4031 case NVPTXISD::Suld1DV4I32Trap:
4032 Opc = NVPTX::SULD_1D_V4I32_TRAP;
4033 Ops.push_back(TexHandle);
4034 Ops.push_back(N->getOperand(2));
4035 Ops.push_back(Chain);
4036 break;
4037 case NVPTXISD::Suld1DArrayI8Trap:
4038 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4039 Ops.push_back(TexHandle);
4040 Ops.push_back(N->getOperand(2));
4041 Ops.push_back(N->getOperand(3));
4042 Ops.push_back(Chain);
4043 break;
4044 case NVPTXISD::Suld1DArrayI16Trap:
4045 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4046 Ops.push_back(TexHandle);
4047 Ops.push_back(N->getOperand(2));
4048 Ops.push_back(N->getOperand(3));
4049 Ops.push_back(Chain);
4050 break;
4051 case NVPTXISD::Suld1DArrayI32Trap:
4052 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4053 Ops.push_back(TexHandle);
4054 Ops.push_back(N->getOperand(2));
4055 Ops.push_back(N->getOperand(3));
4056 Ops.push_back(Chain);
4057 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4058 case NVPTXISD::Suld1DArrayI64Trap:
4059 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4060 Ops.push_back(TexHandle);
4061 Ops.push_back(N->getOperand(2));
4062 Ops.push_back(N->getOperand(3));
4063 Ops.push_back(Chain);
4064 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4065 case NVPTXISD::Suld1DArrayV2I8Trap:
4066 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4067 Ops.push_back(TexHandle);
4068 Ops.push_back(N->getOperand(2));
4069 Ops.push_back(N->getOperand(3));
4070 Ops.push_back(Chain);
4071 break;
4072 case NVPTXISD::Suld1DArrayV2I16Trap:
4073 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4074 Ops.push_back(TexHandle);
4075 Ops.push_back(N->getOperand(2));
4076 Ops.push_back(N->getOperand(3));
4077 Ops.push_back(Chain);
4078 break;
4079 case NVPTXISD::Suld1DArrayV2I32Trap:
4080 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4081 Ops.push_back(TexHandle);
4082 Ops.push_back(N->getOperand(2));
4083 Ops.push_back(N->getOperand(3));
4084 Ops.push_back(Chain);
4085 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4086 case NVPTXISD::Suld1DArrayV2I64Trap:
4087 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4088 Ops.push_back(TexHandle);
4089 Ops.push_back(N->getOperand(2));
4090 Ops.push_back(N->getOperand(3));
4091 Ops.push_back(Chain);
4092 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4093 case NVPTXISD::Suld1DArrayV4I8Trap:
4094 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4095 Ops.push_back(TexHandle);
4096 Ops.push_back(N->getOperand(2));
4097 Ops.push_back(N->getOperand(3));
4098 Ops.push_back(Chain);
4099 break;
4100 case NVPTXISD::Suld1DArrayV4I16Trap:
4101 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4102 Ops.push_back(TexHandle);
4103 Ops.push_back(N->getOperand(2));
4104 Ops.push_back(N->getOperand(3));
4105 Ops.push_back(Chain);
4106 break;
4107 case NVPTXISD::Suld1DArrayV4I32Trap:
4108 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4109 Ops.push_back(TexHandle);
4110 Ops.push_back(N->getOperand(2));
4111 Ops.push_back(N->getOperand(3));
4112 Ops.push_back(Chain);
4113 break;
4114 case NVPTXISD::Suld2DI8Trap:
4115 Opc = NVPTX::SULD_2D_I8_TRAP;
4116 Ops.push_back(TexHandle);
4117 Ops.push_back(N->getOperand(2));
4118 Ops.push_back(N->getOperand(3));
4119 Ops.push_back(Chain);
4120 break;
4121 case NVPTXISD::Suld2DI16Trap:
4122 Opc = NVPTX::SULD_2D_I16_TRAP;
4123 Ops.push_back(TexHandle);
4124 Ops.push_back(N->getOperand(2));
4125 Ops.push_back(N->getOperand(3));
4126 Ops.push_back(Chain);
4127 break;
4128 case NVPTXISD::Suld2DI32Trap:
4129 Opc = NVPTX::SULD_2D_I32_TRAP;
4130 Ops.push_back(TexHandle);
4131 Ops.push_back(N->getOperand(2));
4132 Ops.push_back(N->getOperand(3));
4133 Ops.push_back(Chain);
4134 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4135 case NVPTXISD::Suld2DI64Trap:
4136 Opc = NVPTX::SULD_2D_I64_TRAP;
4137 Ops.push_back(TexHandle);
4138 Ops.push_back(N->getOperand(2));
4139 Ops.push_back(N->getOperand(3));
4140 Ops.push_back(Chain);
4141 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4142 case NVPTXISD::Suld2DV2I8Trap:
4143 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4144 Ops.push_back(TexHandle);
4145 Ops.push_back(N->getOperand(2));
4146 Ops.push_back(N->getOperand(3));
4147 Ops.push_back(Chain);
4148 break;
4149 case NVPTXISD::Suld2DV2I16Trap:
4150 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4151 Ops.push_back(TexHandle);
4152 Ops.push_back(N->getOperand(2));
4153 Ops.push_back(N->getOperand(3));
4154 Ops.push_back(Chain);
4155 break;
4156 case NVPTXISD::Suld2DV2I32Trap:
4157 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4158 Ops.push_back(TexHandle);
4159 Ops.push_back(N->getOperand(2));
4160 Ops.push_back(N->getOperand(3));
4161 Ops.push_back(Chain);
4162 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4163 case NVPTXISD::Suld2DV2I64Trap:
4164 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4165 Ops.push_back(TexHandle);
4166 Ops.push_back(N->getOperand(2));
4167 Ops.push_back(N->getOperand(3));
4168 Ops.push_back(Chain);
4169 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4170 case NVPTXISD::Suld2DV4I8Trap:
4171 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4172 Ops.push_back(TexHandle);
4173 Ops.push_back(N->getOperand(2));
4174 Ops.push_back(N->getOperand(3));
4175 Ops.push_back(Chain);
4176 break;
4177 case NVPTXISD::Suld2DV4I16Trap:
4178 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4179 Ops.push_back(TexHandle);
4180 Ops.push_back(N->getOperand(2));
4181 Ops.push_back(N->getOperand(3));
4182 Ops.push_back(Chain);
4183 break;
4184 case NVPTXISD::Suld2DV4I32Trap:
4185 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4186 Ops.push_back(TexHandle);
4187 Ops.push_back(N->getOperand(2));
4188 Ops.push_back(N->getOperand(3));
4189 Ops.push_back(Chain);
4190 break;
4191 case NVPTXISD::Suld2DArrayI8Trap:
4192 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4193 Ops.push_back(TexHandle);
4194 Ops.push_back(N->getOperand(2));
4195 Ops.push_back(N->getOperand(3));
4196 Ops.push_back(N->getOperand(4));
4197 Ops.push_back(Chain);
4198 break;
4199 case NVPTXISD::Suld2DArrayI16Trap:
4200 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4201 Ops.push_back(TexHandle);
4202 Ops.push_back(N->getOperand(2));
4203 Ops.push_back(N->getOperand(3));
4204 Ops.push_back(N->getOperand(4));
4205 Ops.push_back(Chain);
4206 break;
4207 case NVPTXISD::Suld2DArrayI32Trap:
4208 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4209 Ops.push_back(TexHandle);
4210 Ops.push_back(N->getOperand(2));
4211 Ops.push_back(N->getOperand(3));
4212 Ops.push_back(N->getOperand(4));
4213 Ops.push_back(Chain);
4214 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4215 case NVPTXISD::Suld2DArrayI64Trap:
4216 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4217 Ops.push_back(TexHandle);
4218 Ops.push_back(N->getOperand(2));
4219 Ops.push_back(N->getOperand(3));
4220 Ops.push_back(N->getOperand(4));
4221 Ops.push_back(Chain);
4222 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4223 case NVPTXISD::Suld2DArrayV2I8Trap:
4224 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4225 Ops.push_back(TexHandle);
4226 Ops.push_back(N->getOperand(2));
4227 Ops.push_back(N->getOperand(3));
4228 Ops.push_back(N->getOperand(4));
4229 Ops.push_back(Chain);
4230 break;
4231 case NVPTXISD::Suld2DArrayV2I16Trap:
4232 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4233 Ops.push_back(TexHandle);
4234 Ops.push_back(N->getOperand(2));
4235 Ops.push_back(N->getOperand(3));
4236 Ops.push_back(N->getOperand(4));
4237 Ops.push_back(Chain);
4238 break;
4239 case NVPTXISD::Suld2DArrayV2I32Trap:
4240 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4241 Ops.push_back(TexHandle);
4242 Ops.push_back(N->getOperand(2));
4243 Ops.push_back(N->getOperand(3));
4244 Ops.push_back(N->getOperand(4));
4245 Ops.push_back(Chain);
4246 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4247 case NVPTXISD::Suld2DArrayV2I64Trap:
4248 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4249 Ops.push_back(TexHandle);
4250 Ops.push_back(N->getOperand(2));
4251 Ops.push_back(N->getOperand(3));
4252 Ops.push_back(N->getOperand(4));
4253 Ops.push_back(Chain);
4254 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4255 case NVPTXISD::Suld2DArrayV4I8Trap:
4256 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4257 Ops.push_back(TexHandle);
4258 Ops.push_back(N->getOperand(2));
4259 Ops.push_back(N->getOperand(3));
4260 Ops.push_back(N->getOperand(4));
4261 Ops.push_back(Chain);
4262 break;
4263 case NVPTXISD::Suld2DArrayV4I16Trap:
4264 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4265 Ops.push_back(TexHandle);
4266 Ops.push_back(N->getOperand(2));
4267 Ops.push_back(N->getOperand(3));
4268 Ops.push_back(N->getOperand(4));
4269 Ops.push_back(Chain);
4270 break;
4271 case NVPTXISD::Suld2DArrayV4I32Trap:
4272 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4273 Ops.push_back(TexHandle);
4274 Ops.push_back(N->getOperand(2));
4275 Ops.push_back(N->getOperand(3));
4276 Ops.push_back(N->getOperand(4));
4277 Ops.push_back(Chain);
4278 break;
4279 case NVPTXISD::Suld3DI8Trap:
4280 Opc = NVPTX::SULD_3D_I8_TRAP;
4281 Ops.push_back(TexHandle);
4282 Ops.push_back(N->getOperand(2));
4283 Ops.push_back(N->getOperand(3));
4284 Ops.push_back(N->getOperand(4));
4285 Ops.push_back(Chain);
4286 break;
4287 case NVPTXISD::Suld3DI16Trap:
4288 Opc = NVPTX::SULD_3D_I16_TRAP;
4289 Ops.push_back(TexHandle);
4290 Ops.push_back(N->getOperand(2));
4291 Ops.push_back(N->getOperand(3));
4292 Ops.push_back(N->getOperand(4));
4293 Ops.push_back(Chain);
4294 break;
4295 case NVPTXISD::Suld3DI32Trap:
4296 Opc = NVPTX::SULD_3D_I32_TRAP;
4297 Ops.push_back(TexHandle);
4298 Ops.push_back(N->getOperand(2));
4299 Ops.push_back(N->getOperand(3));
4300 Ops.push_back(N->getOperand(4));
4301 Ops.push_back(Chain);
4302 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4303 case NVPTXISD::Suld3DI64Trap:
4304 Opc = NVPTX::SULD_3D_I64_TRAP;
4305 Ops.push_back(TexHandle);
4306 Ops.push_back(N->getOperand(2));
4307 Ops.push_back(N->getOperand(3));
4308 Ops.push_back(N->getOperand(4));
4309 Ops.push_back(Chain);
4310 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4311 case NVPTXISD::Suld3DV2I8Trap:
4312 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4313 Ops.push_back(TexHandle);
4314 Ops.push_back(N->getOperand(2));
4315 Ops.push_back(N->getOperand(3));
4316 Ops.push_back(N->getOperand(4));
4317 Ops.push_back(Chain);
4318 break;
4319 case NVPTXISD::Suld3DV2I16Trap:
4320 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4321 Ops.push_back(TexHandle);
4322 Ops.push_back(N->getOperand(2));
4323 Ops.push_back(N->getOperand(3));
4324 Ops.push_back(N->getOperand(4));
4325 Ops.push_back(Chain);
4326 break;
4327 case NVPTXISD::Suld3DV2I32Trap:
4328 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4329 Ops.push_back(TexHandle);
4330 Ops.push_back(N->getOperand(2));
4331 Ops.push_back(N->getOperand(3));
4332 Ops.push_back(N->getOperand(4));
4333 Ops.push_back(Chain);
4334 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4335 case NVPTXISD::Suld3DV2I64Trap:
4336 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4337 Ops.push_back(TexHandle);
4338 Ops.push_back(N->getOperand(2));
4339 Ops.push_back(N->getOperand(3));
4340 Ops.push_back(N->getOperand(4));
4341 Ops.push_back(Chain);
4342 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4343 case NVPTXISD::Suld3DV4I8Trap:
4344 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4345 Ops.push_back(TexHandle);
4346 Ops.push_back(N->getOperand(2));
4347 Ops.push_back(N->getOperand(3));
4348 Ops.push_back(N->getOperand(4));
4349 Ops.push_back(Chain);
4350 break;
4351 case NVPTXISD::Suld3DV4I16Trap:
4352 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4353 Ops.push_back(TexHandle);
4354 Ops.push_back(N->getOperand(2));
4355 Ops.push_back(N->getOperand(3));
4356 Ops.push_back(N->getOperand(4));
4357 Ops.push_back(Chain);
4358 break;
4359 case NVPTXISD::Suld3DV4I32Trap:
4360 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4361 Ops.push_back(TexHandle);
4362 Ops.push_back(N->getOperand(2));
4363 Ops.push_back(N->getOperand(3));
4364 Ops.push_back(N->getOperand(4));
4365 Ops.push_back(Chain);
4366 break;
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4367 case NVPTXISD::Suld1DI8Zero:
4368 Opc = NVPTX::SULD_1D_I8_ZERO;
4369 Ops.push_back(TexHandle);
4370 Ops.push_back(N->getOperand(2));
4371 Ops.push_back(Chain);
4372 break;
4373 case NVPTXISD::Suld1DI16Zero:
4374 Opc = NVPTX::SULD_1D_I16_ZERO;
4375 Ops.push_back(TexHandle);
4376 Ops.push_back(N->getOperand(2));
4377 Ops.push_back(Chain);
4378 break;
4379 case NVPTXISD::Suld1DI32Zero:
4380 Opc = NVPTX::SULD_1D_I32_ZERO;
4381 Ops.push_back(TexHandle);
4382 Ops.push_back(N->getOperand(2));
4383 Ops.push_back(Chain);
4384 break;
4385 case NVPTXISD::Suld1DI64Zero:
4386 Opc = NVPTX::SULD_1D_I64_ZERO;
4387 Ops.push_back(TexHandle);
4388 Ops.push_back(N->getOperand(2));
4389 Ops.push_back(Chain);
4390 break;
4391 case NVPTXISD::Suld1DV2I8Zero:
4392 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4393 Ops.push_back(TexHandle);
4394 Ops.push_back(N->getOperand(2));
4395 Ops.push_back(Chain);
4396 break;
4397 case NVPTXISD::Suld1DV2I16Zero:
4398 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4399 Ops.push_back(TexHandle);
4400 Ops.push_back(N->getOperand(2));
4401 Ops.push_back(Chain);
4402 break;
4403 case NVPTXISD::Suld1DV2I32Zero:
4404 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4405 Ops.push_back(TexHandle);
4406 Ops.push_back(N->getOperand(2));
4407 Ops.push_back(Chain);
4408 break;
4409 case NVPTXISD::Suld1DV2I64Zero:
4410 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4411 Ops.push_back(TexHandle);
4412 Ops.push_back(N->getOperand(2));
4413 Ops.push_back(Chain);
4414 break;
4415 case NVPTXISD::Suld1DV4I8Zero:
4416 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4417 Ops.push_back(TexHandle);
4418 Ops.push_back(N->getOperand(2));
4419 Ops.push_back(Chain);
4420 break;
4421 case NVPTXISD::Suld1DV4I16Zero:
4422 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4423 Ops.push_back(TexHandle);
4424 Ops.push_back(N->getOperand(2));
4425 Ops.push_back(Chain);
4426 break;
4427 case NVPTXISD::Suld1DV4I32Zero:
4428 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4429 Ops.push_back(TexHandle);
4430 Ops.push_back(N->getOperand(2));
4431 Ops.push_back(Chain);
4432 break;
4433 case NVPTXISD::Suld1DArrayI8Zero:
4434 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4435 Ops.push_back(TexHandle);
4436 Ops.push_back(N->getOperand(2));
4437 Ops.push_back(N->getOperand(3));
4438 Ops.push_back(Chain);
4439 break;
4440 case NVPTXISD::Suld1DArrayI16Zero:
4441 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4442 Ops.push_back(TexHandle);
4443 Ops.push_back(N->getOperand(2));
4444 Ops.push_back(N->getOperand(3));
4445 Ops.push_back(Chain);
4446 break;
4447 case NVPTXISD::Suld1DArrayI32Zero:
4448 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4449 Ops.push_back(TexHandle);
4450 Ops.push_back(N->getOperand(2));
4451 Ops.push_back(N->getOperand(3));
4452 Ops.push_back(Chain);
4453 break;
4454 case NVPTXISD::Suld1DArrayI64Zero:
4455 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4456 Ops.push_back(TexHandle);
4457 Ops.push_back(N->getOperand(2));
4458 Ops.push_back(N->getOperand(3));
4459 Ops.push_back(Chain);
4460 break;
4461 case NVPTXISD::Suld1DArrayV2I8Zero:
4462 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4463 Ops.push_back(TexHandle);
4464 Ops.push_back(N->getOperand(2));
4465 Ops.push_back(N->getOperand(3));
4466 Ops.push_back(Chain);
4467 break;
4468 case NVPTXISD::Suld1DArrayV2I16Zero:
4469 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4470 Ops.push_back(TexHandle);
4471 Ops.push_back(N->getOperand(2));
4472 Ops.push_back(N->getOperand(3));
4473 Ops.push_back(Chain);
4474 break;
4475 case NVPTXISD::Suld1DArrayV2I32Zero:
4476 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4477 Ops.push_back(TexHandle);
4478 Ops.push_back(N->getOperand(2));
4479 Ops.push_back(N->getOperand(3));
4480 Ops.push_back(Chain);
4481 break;
4482 case NVPTXISD::Suld1DArrayV2I64Zero:
4483 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4484 Ops.push_back(TexHandle);
4485 Ops.push_back(N->getOperand(2));
4486 Ops.push_back(N->getOperand(3));
4487 Ops.push_back(Chain);
4488 break;
4489 case NVPTXISD::Suld1DArrayV4I8Zero:
4490 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4491 Ops.push_back(TexHandle);
4492 Ops.push_back(N->getOperand(2));
4493 Ops.push_back(N->getOperand(3));
4494 Ops.push_back(Chain);
4495 break;
4496 case NVPTXISD::Suld1DArrayV4I16Zero:
4497 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4498 Ops.push_back(TexHandle);
4499 Ops.push_back(N->getOperand(2));
4500 Ops.push_back(N->getOperand(3));
4501 Ops.push_back(Chain);
4502 break;
4503 case NVPTXISD::Suld1DArrayV4I32Zero:
4504 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4505 Ops.push_back(TexHandle);
4506 Ops.push_back(N->getOperand(2));
4507 Ops.push_back(N->getOperand(3));
4508 Ops.push_back(Chain);
4509 break;
4510 case NVPTXISD::Suld2DI8Zero:
4511 Opc = NVPTX::SULD_2D_I8_ZERO;
4512 Ops.push_back(TexHandle);
4513 Ops.push_back(N->getOperand(2));
4514 Ops.push_back(N->getOperand(3));
4515 Ops.push_back(Chain);
4516 break;
4517 case NVPTXISD::Suld2DI16Zero:
4518 Opc = NVPTX::SULD_2D_I16_ZERO;
4519 Ops.push_back(TexHandle);
4520 Ops.push_back(N->getOperand(2));
4521 Ops.push_back(N->getOperand(3));
4522 Ops.push_back(Chain);
4523 break;
4524 case NVPTXISD::Suld2DI32Zero:
4525 Opc = NVPTX::SULD_2D_I32_ZERO;
4526 Ops.push_back(TexHandle);
4527 Ops.push_back(N->getOperand(2));
4528 Ops.push_back(N->getOperand(3));
4529 Ops.push_back(Chain);
4530 break;
4531 case NVPTXISD::Suld2DI64Zero:
4532 Opc = NVPTX::SULD_2D_I64_ZERO;
4533 Ops.push_back(TexHandle);
4534 Ops.push_back(N->getOperand(2));
4535 Ops.push_back(N->getOperand(3));
4536 Ops.push_back(Chain);
4537 break;
4538 case NVPTXISD::Suld2DV2I8Zero:
4539 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4540 Ops.push_back(TexHandle);
4541 Ops.push_back(N->getOperand(2));
4542 Ops.push_back(N->getOperand(3));
4543 Ops.push_back(Chain);
4544 break;
4545 case NVPTXISD::Suld2DV2I16Zero:
4546 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4547 Ops.push_back(TexHandle);
4548 Ops.push_back(N->getOperand(2));
4549 Ops.push_back(N->getOperand(3));
4550 Ops.push_back(Chain);
4551 break;
4552 case NVPTXISD::Suld2DV2I32Zero:
4553 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4554 Ops.push_back(TexHandle);
4555 Ops.push_back(N->getOperand(2));
4556 Ops.push_back(N->getOperand(3));
4557 Ops.push_back(Chain);
4558 break;
4559 case NVPTXISD::Suld2DV2I64Zero:
4560 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4561 Ops.push_back(TexHandle);
4562 Ops.push_back(N->getOperand(2));
4563 Ops.push_back(N->getOperand(3));
4564 Ops.push_back(Chain);
4565 break;
4566 case NVPTXISD::Suld2DV4I8Zero:
4567 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4568 Ops.push_back(TexHandle);
4569 Ops.push_back(N->getOperand(2));
4570 Ops.push_back(N->getOperand(3));
4571 Ops.push_back(Chain);
4572 break;
4573 case NVPTXISD::Suld2DV4I16Zero:
4574 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4575 Ops.push_back(TexHandle);
4576 Ops.push_back(N->getOperand(2));
4577 Ops.push_back(N->getOperand(3));
4578 Ops.push_back(Chain);
4579 break;
4580 case NVPTXISD::Suld2DV4I32Zero:
4581 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4582 Ops.push_back(TexHandle);
4583 Ops.push_back(N->getOperand(2));
4584 Ops.push_back(N->getOperand(3));
4585 Ops.push_back(Chain);
4586 break;
4587 case NVPTXISD::Suld2DArrayI8Zero:
4588 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4589 Ops.push_back(TexHandle);
4590 Ops.push_back(N->getOperand(2));
4591 Ops.push_back(N->getOperand(3));
4592 Ops.push_back(N->getOperand(4));
4593 Ops.push_back(Chain);
4594 break;
4595 case NVPTXISD::Suld2DArrayI16Zero:
4596 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4597 Ops.push_back(TexHandle);
4598 Ops.push_back(N->getOperand(2));
4599 Ops.push_back(N->getOperand(3));
4600 Ops.push_back(N->getOperand(4));
4601 Ops.push_back(Chain);
4602 break;
4603 case NVPTXISD::Suld2DArrayI32Zero:
4604 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4605 Ops.push_back(TexHandle);
4606 Ops.push_back(N->getOperand(2));
4607 Ops.push_back(N->getOperand(3));
4608 Ops.push_back(N->getOperand(4));
4609 Ops.push_back(Chain);
4610 break;
4611 case NVPTXISD::Suld2DArrayI64Zero:
4612 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4613 Ops.push_back(TexHandle);
4614 Ops.push_back(N->getOperand(2));
4615 Ops.push_back(N->getOperand(3));
4616 Ops.push_back(N->getOperand(4));
4617 Ops.push_back(Chain);
4618 break;
4619 case NVPTXISD::Suld2DArrayV2I8Zero:
4620 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4621 Ops.push_back(TexHandle);
4622 Ops.push_back(N->getOperand(2));
4623 Ops.push_back(N->getOperand(3));
4624 Ops.push_back(N->getOperand(4));
4625 Ops.push_back(Chain);
4626 break;
4627 case NVPTXISD::Suld2DArrayV2I16Zero:
4628 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4629 Ops.push_back(TexHandle);
4630 Ops.push_back(N->getOperand(2));
4631 Ops.push_back(N->getOperand(3));
4632 Ops.push_back(N->getOperand(4));
4633 Ops.push_back(Chain);
4634 break;
4635 case NVPTXISD::Suld2DArrayV2I32Zero:
4636 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4637 Ops.push_back(TexHandle);
4638 Ops.push_back(N->getOperand(2));
4639 Ops.push_back(N->getOperand(3));
4640 Ops.push_back(N->getOperand(4));
4641 Ops.push_back(Chain);
4642 break;
4643 case NVPTXISD::Suld2DArrayV2I64Zero:
4644 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4645 Ops.push_back(TexHandle);
4646 Ops.push_back(N->getOperand(2));
4647 Ops.push_back(N->getOperand(3));
4648 Ops.push_back(N->getOperand(4));
4649 Ops.push_back(Chain);
4650 break;
4651 case NVPTXISD::Suld2DArrayV4I8Zero:
4652 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4653 Ops.push_back(TexHandle);
4654 Ops.push_back(N->getOperand(2));
4655 Ops.push_back(N->getOperand(3));
4656 Ops.push_back(N->getOperand(4));
4657 Ops.push_back(Chain);
4658 break;
4659 case NVPTXISD::Suld2DArrayV4I16Zero:
4660 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4661 Ops.push_back(TexHandle);
4662 Ops.push_back(N->getOperand(2));
4663 Ops.push_back(N->getOperand(3));
4664 Ops.push_back(N->getOperand(4));
4665 Ops.push_back(Chain);
4666 break;
4667 case NVPTXISD::Suld2DArrayV4I32Zero:
4668 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4669 Ops.push_back(TexHandle);
4670 Ops.push_back(N->getOperand(2));
4671 Ops.push_back(N->getOperand(3));
4672 Ops.push_back(N->getOperand(4));
4673 Ops.push_back(Chain);
4674 break;
4675 case NVPTXISD::Suld3DI8Zero:
4676 Opc = NVPTX::SULD_3D_I8_ZERO;
4677 Ops.push_back(TexHandle);
4678 Ops.push_back(N->getOperand(2));
4679 Ops.push_back(N->getOperand(3));
4680 Ops.push_back(N->getOperand(4));
4681 Ops.push_back(Chain);
4682 break;
4683 case NVPTXISD::Suld3DI16Zero:
4684 Opc = NVPTX::SULD_3D_I16_ZERO;
4685 Ops.push_back(TexHandle);
4686 Ops.push_back(N->getOperand(2));
4687 Ops.push_back(N->getOperand(3));
4688 Ops.push_back(N->getOperand(4));
4689 Ops.push_back(Chain);
4690 break;
4691 case NVPTXISD::Suld3DI32Zero:
4692 Opc = NVPTX::SULD_3D_I32_ZERO;
4693 Ops.push_back(TexHandle);
4694 Ops.push_back(N->getOperand(2));
4695 Ops.push_back(N->getOperand(3));
4696 Ops.push_back(N->getOperand(4));
4697 Ops.push_back(Chain);
4698 break;
4699 case NVPTXISD::Suld3DI64Zero:
4700 Opc = NVPTX::SULD_3D_I64_ZERO;
4701 Ops.push_back(TexHandle);
4702 Ops.push_back(N->getOperand(2));
4703 Ops.push_back(N->getOperand(3));
4704 Ops.push_back(N->getOperand(4));
4705 Ops.push_back(Chain);
4706 break;
4707 case NVPTXISD::Suld3DV2I8Zero:
4708 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4709 Ops.push_back(TexHandle);
4710 Ops.push_back(N->getOperand(2));
4711 Ops.push_back(N->getOperand(3));
4712 Ops.push_back(N->getOperand(4));
4713 Ops.push_back(Chain);
4714 break;
4715 case NVPTXISD::Suld3DV2I16Zero:
4716 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4717 Ops.push_back(TexHandle);
4718 Ops.push_back(N->getOperand(2));
4719 Ops.push_back(N->getOperand(3));
4720 Ops.push_back(N->getOperand(4));
4721 Ops.push_back(Chain);
4722 break;
4723 case NVPTXISD::Suld3DV2I32Zero:
4724 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4725 Ops.push_back(TexHandle);
4726 Ops.push_back(N->getOperand(2));
4727 Ops.push_back(N->getOperand(3));
4728 Ops.push_back(N->getOperand(4));
4729 Ops.push_back(Chain);
4730 break;
4731 case NVPTXISD::Suld3DV2I64Zero:
4732 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4733 Ops.push_back(TexHandle);
4734 Ops.push_back(N->getOperand(2));
4735 Ops.push_back(N->getOperand(3));
4736 Ops.push_back(N->getOperand(4));
4737 Ops.push_back(Chain);
4738 break;
4739 case NVPTXISD::Suld3DV4I8Zero:
4740 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4741 Ops.push_back(TexHandle);
4742 Ops.push_back(N->getOperand(2));
4743 Ops.push_back(N->getOperand(3));
4744 Ops.push_back(N->getOperand(4));
4745 Ops.push_back(Chain);
4746 break;
4747 case NVPTXISD::Suld3DV4I16Zero:
4748 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4749 Ops.push_back(TexHandle);
4750 Ops.push_back(N->getOperand(2));
4751 Ops.push_back(N->getOperand(3));
4752 Ops.push_back(N->getOperand(4));
4753 Ops.push_back(Chain);
4754 break;
4755 case NVPTXISD::Suld3DV4I32Zero:
4756 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4757 Ops.push_back(TexHandle);
4758 Ops.push_back(N->getOperand(2));
4759 Ops.push_back(N->getOperand(3));
4760 Ops.push_back(N->getOperand(4));
4761 Ops.push_back(Chain);
4762 break;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]4763 }
4764 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4765 return Ret;
4766}
4767
Justin Holewinski9a2350e2014-07-17 11:59:04 +0000[diff] [blame]4768
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4769/// SelectBFE - Look for instruction sequences that can be made more efficient
4770/// by using the 'bfe' (bit-field extract) PTX instruction
4771SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]4772 SDLoc DL(N);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4773 SDValue LHS = N->getOperand(0);
4774 SDValue RHS = N->getOperand(1);
4775 SDValue Len;
4776 SDValue Start;
4777 SDValue Val;
4778 bool IsSigned = false;
4779
4780 if (N->getOpcode() == ISD::AND) {
4781 // Canonicalize the operands
4782 // We want 'and %val, %mask'
4783 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4784 std::swap(LHS, RHS);
4785 }
4786
4787 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
4788 if (!Mask) {
4789 // We need a constant mask on the RHS of the AND
4790 return NULL;
4791 }
4792
4793 // Extract the mask bits
4794 uint64_t MaskVal = Mask->getZExtValue();
4795 if (!isMask_64(MaskVal)) {
4796 // We *could* handle shifted masks here, but doing so would require an
4797 // 'and' operation to fix up the low-order bits so we would trade
4798 // shr+and for bfe+and, which has the same throughput
4799 return NULL;
4800 }
4801
4802 // How many bits are in our mask?
Benjamin Kramer5f6a9072015-02-12 15:35:40 +0000[diff] [blame]4803 uint64_t NumBits = countTrailingOnes(MaskVal);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]4804 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4805
4806 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
4807 // We have a 'srl/and' pair, extract the effective start bit and length
4808 Val = LHS.getNode()->getOperand(0);
4809 Start = LHS.getNode()->getOperand(1);
4810 ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
4811 if (StartConst) {
4812 uint64_t StartVal = StartConst->getZExtValue();
4813 // How many "good" bits do we have left? "good" is defined here as bits
4814 // that exist in the original value, not shifted in.
4815 uint64_t GoodBits = Start.getValueType().getSizeInBits() - StartVal;
4816 if (NumBits > GoodBits) {
4817 // Do not handle the case where bits have been shifted in. In theory
4818 // we could handle this, but the cost is likely higher than just
4819 // emitting the srl/and pair.
4820 return NULL;
4821 }
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]4822 Start = CurDAG->getTargetConstant(StartVal, DL, MVT::i32);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4823 } else {
4824 // Do not handle the case where the shift amount (can be zero if no srl
4825 // was found) is not constant. We could handle this case, but it would
4826 // require run-time logic that would be more expensive than just
4827 // emitting the srl/and pair.
4828 return NULL;
4829 }
4830 } else {
4831 // Do not handle the case where the LHS of the and is not a shift. While
4832 // it would be trivial to handle this case, it would just transform
4833 // 'and' -> 'bfe', but 'and' has higher-throughput.
4834 return NULL;
4835 }
4836 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
4837 if (LHS->getOpcode() == ISD::AND) {
4838 ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
4839 if (!ShiftCnst) {
4840 // Shift amount must be constant
4841 return NULL;
4842 }
4843
4844 uint64_t ShiftAmt = ShiftCnst->getZExtValue();
4845
4846 SDValue AndLHS = LHS->getOperand(0);
4847 SDValue AndRHS = LHS->getOperand(1);
4848
4849 // Canonicalize the AND to have the mask on the RHS
4850 if (isa<ConstantSDNode>(AndLHS)) {
4851 std::swap(AndLHS, AndRHS);
4852 }
4853
4854 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
4855 if (!MaskCnst) {
4856 // Mask must be constant
4857 return NULL;
4858 }
4859
4860 uint64_t MaskVal = MaskCnst->getZExtValue();
4861 uint64_t NumZeros;
4862 uint64_t NumBits;
4863 if (isMask_64(MaskVal)) {
4864 NumZeros = 0;
4865 // The number of bits in the result bitfield will be the number of
4866 // trailing ones (the AND) minus the number of bits we shift off
Benjamin Kramer5f6a9072015-02-12 15:35:40 +0000[diff] [blame]4867 NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4868 } else if (isShiftedMask_64(MaskVal)) {
4869 NumZeros = countTrailingZeros(MaskVal);
Benjamin Kramer5f6a9072015-02-12 15:35:40 +0000[diff] [blame]4870 unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4871 // The number of bits in the result bitfield will be the number of
4872 // trailing zeros plus the number of set bits in the mask minus the
4873 // number of bits we shift off
4874 NumBits = NumZeros + NumOnes - ShiftAmt;
4875 } else {
4876 // This is not a mask we can handle
4877 return NULL;
4878 }
4879
4880 if (ShiftAmt < NumZeros) {
4881 // Handling this case would require extra logic that would make this
4882 // transformation non-profitable
4883 return NULL;
4884 }
4885
4886 Val = AndLHS;
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]4887 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32);
4888 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4889 } else if (LHS->getOpcode() == ISD::SHL) {
4890 // Here, we have a pattern like:
4891 //
4892 // (sra (shl val, NN), MM)
4893 // or
4894 // (srl (shl val, NN), MM)
4895 //
4896 // If MM >= NN, we can efficiently optimize this with bfe
4897 Val = LHS->getOperand(0);
4898
4899 SDValue ShlRHS = LHS->getOperand(1);
4900 ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
4901 if (!ShlCnst) {
4902 // Shift amount must be constant
4903 return NULL;
4904 }
4905 uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
4906
4907 SDValue ShrRHS = RHS;
4908 ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
4909 if (!ShrCnst) {
4910 // Shift amount must be constant
4911 return NULL;
4912 }
4913 uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
4914
4915 // To avoid extra codegen and be profitable, we need Outer >= Inner
4916 if (OuterShiftAmt < InnerShiftAmt) {
4917 return NULL;
4918 }
4919
4920 // If the outer shift is more than the type size, we have no bitfield to
4921 // extract (since we also check that the inner shift is <= the outer shift
4922 // then this also implies that the inner shift is < the type size)
4923 if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
4924 return NULL;
4925 }
4926
4927 Start =
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]4928 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, DL, MVT::i32);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4929 Len =
4930 CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]4931 OuterShiftAmt, DL, MVT::i32);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4932
4933 if (N->getOpcode() == ISD::SRA) {
4934 // If we have a arithmetic right shift, we need to use the signed bfe
4935 // variant
4936 IsSigned = true;
4937 }
4938 } else {
4939 // No can do...
4940 return NULL;
4941 }
4942 } else {
4943 // No can do...
4944 return NULL;
4945 }
4946
4947
4948 unsigned Opc;
4949 // For the BFE operations we form here from "and" and "srl", always use the
4950 // unsigned variants.
4951 if (Val.getValueType() == MVT::i32) {
4952 if (IsSigned) {
4953 Opc = NVPTX::BFE_S32rii;
4954 } else {
4955 Opc = NVPTX::BFE_U32rii;
4956 }
4957 } else if (Val.getValueType() == MVT::i64) {
4958 if (IsSigned) {
4959 Opc = NVPTX::BFE_S64rii;
4960 } else {
4961 Opc = NVPTX::BFE_U64rii;
4962 }
4963 } else {
4964 // We cannot handle this type
4965 return NULL;
4966 }
4967
4968 SDValue Ops[] = {
4969 Val, Start, Len
4970 };
4971
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]4972 return CurDAG->getMachineNode(Opc, DL, N->getVTList(), Ops);
Justin Holewinskica7a4f12014-06-27 18:35:27 +0000[diff] [blame]4973}
4974
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]4975// SelectDirectAddr - Match a direct address for DAG.
4976// A direct address could be a globaladdress or externalsymbol.
4977bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
4978 // Return true if TGA or ES.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]4979 if (N.getOpcode() == ISD::TargetGlobalAddress ||
4980 N.getOpcode() == ISD::TargetExternalSymbol) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]4981 Address = N;
4982 return true;
4983 }
4984 if (N.getOpcode() == NVPTXISD::Wrapper) {
4985 Address = N.getOperand(0);
4986 return true;
4987 }
4988 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
4989 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
4990 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
4991 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
4992 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
4993 }
4994 return false;
4995}
4996
4997// symbol+offset
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]4998bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
4999 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5000 if (Addr.getOpcode() == ISD::ADD) {
5001 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]5002 SDValue base = Addr.getOperand(0);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5003 if (SelectDirectAddr(base, Base)) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]5004 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
5005 mvt);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5006 return true;
5007 }
5008 }
5009 }
5010 return false;
5011}
5012
5013// symbol+offset
5014bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
5015 SDValue &Base, SDValue &Offset) {
5016 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
5017}
5018
5019// symbol+offset
5020bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
5021 SDValue &Base, SDValue &Offset) {
5022 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
5023}
5024
5025// register+offset
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]5026bool NVPTXDAGToDAGISel::SelectADDRri_imp(
5027 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5028 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
5029 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]5030 Offset = CurDAG->getTargetConstant(0, SDLoc(OpNode), mvt);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5031 return true;
5032 }
5033 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
5034 Addr.getOpcode() == ISD::TargetGlobalAddress)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]5035 return false; // direct calls.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5036
5037 if (Addr.getOpcode() == ISD::ADD) {
5038 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
5039 return false;
5040 }
5041 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5042 if (FrameIndexSDNode *FIN =
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]5043 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5044 // Constant offset from frame ref.
5045 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5046 else
5047 Base = Addr.getOperand(0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]5048 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
5049 mvt);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5050 return true;
5051 }
5052 }
5053 return false;
5054}
5055
5056// register+offset
5057bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
5058 SDValue &Base, SDValue &Offset) {
5059 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5060}
5061
5062// register+offset
5063bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
5064 SDValue &Base, SDValue &Offset) {
5065 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5066}
5067
5068bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
5069 unsigned int spN) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5070 const Value *Src = nullptr;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5071 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
Nick Lewyckyaad475b2014-04-15 07:22:52 +0000[diff] [blame]5072 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5073 return true;
5074 Src = mN->getMemOperand()->getValue();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5075 }
5076 if (!Src)
5077 return false;
Craig Toppere3dcce92015-08-01 22:20:21 +0000[diff] [blame^]5078 if (auto *PT = dyn_cast<PointerType>(Src->getType()))
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5079 return (PT->getAddressSpace() == spN);
5080 return false;
5081}
5082
5083/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
5084/// inline asm expressions.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]5085bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
Daniel Sanders60f1db02015-03-13 12:45:09 +0000[diff] [blame]5086 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5087 SDValue Op0, Op1;
Daniel Sanders60f1db02015-03-13 12:45:09 +0000[diff] [blame]5088 switch (ConstraintID) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]5089 default:
5090 return true;
Daniel Sanders60f1db02015-03-13 12:45:09 +0000[diff] [blame]5091 case InlineAsm::Constraint_m: // memory
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5092 if (SelectDirectAddr(Op, Op0)) {
5093 OutOps.push_back(Op0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]5094 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]5095 return false;
5096 }
5097 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
5098 OutOps.push_back(Op0);
5099 OutOps.push_back(Op1);
5100 return false;
5101 }
5102 break;
5103 }
5104 return true;
5105}