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gerrit-public.fairphone.software / toolchain / llvm-project / e407736a065bd59d87c30da91e609583cb1cf552 / . / llvm / test / CodeGen / AArch64 / dp-3source.ll
blob: 81d9e15532fa95d678f6c0999e0b5952951817eb [file] [log] [blame]
Tim Northovere3d42362013-02-01 11:40:47 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]2
3define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]4; CHECK-LABEL: test_madd32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]5 %mid = mul i32 %val1, %val2
6 %res = add i32 %val0, %mid
7; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
8 ret i32 %res
9}
10
11define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]12; CHECK-LABEL: test_madd64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]13 %mid = mul i64 %val1, %val2
14 %res = add i64 %val0, %mid
15; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
16 ret i64 %res
17}
18
19define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]20; CHECK-LABEL: test_msub32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]21 %mid = mul i32 %val1, %val2
22 %res = sub i32 %val0, %mid
23; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
24 ret i32 %res
25}
26
27define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]28; CHECK-LABEL: test_msub64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]29 %mid = mul i64 %val1, %val2
30 %res = sub i64 %val0, %mid
31; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
32 ret i64 %res
33}
34
35define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]36; CHECK-LABEL: test_smaddl:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]37 %ext1 = sext i32 %val1 to i64
38 %ext2 = sext i32 %val2 to i64
39 %prod = mul i64 %ext1, %ext2
40 %res = add i64 %acc, %prod
41; CHECK: smaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
42 ret i64 %res
43}
44
45define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]46; CHECK-LABEL: test_smsubl:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]47 %ext1 = sext i32 %val1 to i64
48 %ext2 = sext i32 %val2 to i64
49 %prod = mul i64 %ext1, %ext2
50 %res = sub i64 %acc, %prod
51; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
52 ret i64 %res
53}
54
55define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]56; CHECK-LABEL: test_umaddl:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]57 %ext1 = zext i32 %val1 to i64
58 %ext2 = zext i32 %val2 to i64
59 %prod = mul i64 %ext1, %ext2
60 %res = add i64 %acc, %prod
61; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
62 ret i64 %res
63}
64
65define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]66; CHECK-LABEL: test_umsubl:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]67 %ext1 = zext i32 %val1 to i64
68 %ext2 = zext i32 %val2 to i64
69 %prod = mul i64 %ext1, %ext2
70 %res = sub i64 %acc, %prod
71; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
72 ret i64 %res
73}
74
75define i64 @test_smulh(i64 %lhs, i64 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]76; CHECK-LABEL: test_smulh:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]77 %ext1 = sext i64 %lhs to i128
78 %ext2 = sext i64 %rhs to i128
79 %res = mul i128 %ext1, %ext2
80 %high = lshr i128 %res, 64
81 %val = trunc i128 %high to i64
82; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
83 ret i64 %val
84}
85
86define i64 @test_umulh(i64 %lhs, i64 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]87; CHECK-LABEL: test_umulh:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]88 %ext1 = zext i64 %lhs to i128
89 %ext2 = zext i64 %rhs to i128
90 %res = mul i128 %ext1, %ext2
91 %high = lshr i128 %res, 64
92 %val = trunc i128 %high to i64
93; CHECK: umulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
94 ret i64 %val
95}
96
97define i32 @test_mul32(i32 %lhs, i32 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]98; CHECK-LABEL: test_mul32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]99 %res = mul i32 %lhs, %rhs
100; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
101 ret i32 %res
102}
103
104define i64 @test_mul64(i64 %lhs, i64 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]105; CHECK-LABEL: test_mul64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]106 %res = mul i64 %lhs, %rhs
107; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
108 ret i64 %res
109}
110
111define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]112; CHECK-LABEL: test_mneg32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]113 %prod = mul i32 %lhs, %rhs
114 %res = sub i32 0, %prod
115; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
116 ret i32 %res
117}
118
119define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]120; CHECK-LABEL: test_mneg64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]121 %prod = mul i64 %lhs, %rhs
122 %res = sub i64 0, %prod
123; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
124 ret i64 %res
125}
126
127define i64 @test_smull(i32 %lhs, i32 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]128; CHECK-LABEL: test_smull:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]129 %ext1 = sext i32 %lhs to i64
130 %ext2 = sext i32 %rhs to i64
131 %res = mul i64 %ext1, %ext2
132; CHECK: smull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
133 ret i64 %res
134}
135
136define i64 @test_umull(i32 %lhs, i32 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]137; CHECK-LABEL: test_umull:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]138 %ext1 = zext i32 %lhs to i64
139 %ext2 = zext i32 %rhs to i64
140 %res = mul i64 %ext1, %ext2
141; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
142 ret i64 %res
143}
144
145define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]146; CHECK-LABEL: test_smnegl:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]147 %ext1 = sext i32 %lhs to i64
148 %ext2 = sext i32 %rhs to i64
149 %prod = mul i64 %ext1, %ext2
150 %res = sub i64 0, %prod
151; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
152 ret i64 %res
153}
154
155define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]156; CHECK-LABEL: test_umnegl:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]157 %ext1 = zext i32 %lhs to i64
158 %ext2 = zext i32 %rhs to i64
159 %prod = mul i64 %ext1, %ext2
160 %res = sub i64 0, %prod
161; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
162 ret i64 %res
163}