blob: ba0f5ade2cc1a3b595417d701fd8b8931edf7c9a [file] [log] [blame]
Michael Kuperstein946b3b22014-09-23 08:48:01 +00001; RUN: llvm-dis < %s.bc| FileCheck %s
Duncan P. N. Exon Smithfee1f502014-07-29 01:10:57 +00002
3; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
4; The test checks that LLVM does not misread terminator instructions from
5; older bitcode files.
6
7define i32 @condbr(i1 %cond){
8entry:
9; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel
10 br i1 %cond, label %TrueLabel, label %FalseLabel
Michael Kuperstein946b3b22014-09-23 08:48:01 +000011
Duncan P. N. Exon Smithfee1f502014-07-29 01:10:57 +000012 TrueLabel:
13 ret i32 1
Michael Kuperstein946b3b22014-09-23 08:48:01 +000014
Duncan P. N. Exon Smithfee1f502014-07-29 01:10:57 +000015 FalseLabel:
16 ret i32 0
17}
18
19define i32 @uncondbr(){
20entry:
21; CHECK: br label %uncondLabel
22 br label %uncondLabel
Michael Kuperstein946b3b22014-09-23 08:48:01 +000023
Duncan P. N. Exon Smithfee1f502014-07-29 01:10:57 +000024 uncondLabel:
25 ret i32 1
26}
27
28define i32 @indirectbr(i8* %Addr){
29entry:
30; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2]
31 indirectbr i8* %Addr, [ label %bb1, label %bb2 ]
Michael Kuperstein946b3b22014-09-23 08:48:01 +000032
Duncan P. N. Exon Smithfee1f502014-07-29 01:10:57 +000033 bb1:
34 ret i32 1
Michael Kuperstein946b3b22014-09-23 08:48:01 +000035
Duncan P. N. Exon Smithfee1f502014-07-29 01:10:57 +000036 bb2:
37 ret i32 0
38}
39
40define void @unreachable(){
41entry:
42; CHECK: unreachable
43 unreachable
Michael Kuperstein946b3b22014-09-23 08:48:01 +000044
Duncan P. N. Exon Smithfee1f502014-07-29 01:10:57 +000045 ret void
46}
47
Michael Kuperstein946b3b22014-09-23 08:48:01 +000048define i32 @retInstr(){
49entry:
50; CHECK: ret i32 1
51 ret i32 1
52}
53
54define void @retInstr2(){
55entry:
56; CHECK: ret void
57 ret void
58}
59
60define i32 @switchInstr(i32 %x){
61entry:
62; CHECK: switch i32 %x, label %label3 [
63 switch i32 %x, label %label3 [
64; CHECK-NEXT: i32 1, label %label1
65 i32 1, label %label1
66; CHECK-NEXT: i32 2, label %label2
67 i32 2, label %label2
68 ]
69label1:
70 ret i32 1
71label2:
72 ret i32 2
73label3:
74 ret i32 0
75}
76