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Alex Bradbury6b2cca72016-11-01 23:47:30 +00001//===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Alex Bradbury6b2cca72016-11-01 23:47:30 +00006//
7//===----------------------------------------------------------------------===//
8
Alex Bradbury9d3f1252017-09-28 08:26:24 +00009#include "MCTargetDesc/RISCVFixupKinds.h"
Alex Bradbury6b2cca72016-11-01 23:47:30 +000010#include "MCTargetDesc/RISCVMCTargetDesc.h"
11#include "llvm/MC/MCELFObjectWriter.h"
12#include "llvm/MC/MCFixup.h"
Alex Bradbury5c1eef42017-10-11 12:09:06 +000013#include "llvm/MC/MCObjectWriter.h"
Alex Bradbury6b2cca72016-11-01 23:47:30 +000014#include "llvm/Support/ErrorHandling.h"
15
16using namespace llvm;
17
18namespace {
19class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
20public:
21 RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit);
22
23 ~RISCVELFObjectWriter() override;
24
Shiva Chen98f93892018-04-25 14:18:55 +000025 // Return true if the given relocation must be with a symbol rather than
26 // section plus offset.
27 bool needsRelocateWithSymbol(const MCSymbol &Sym,
28 unsigned Type) const override {
29 // TODO: this is very conservative, update once RISC-V psABI requirements
30 // are clarified.
31 return true;
32 }
33
Alex Bradbury6b2cca72016-11-01 23:47:30 +000034protected:
35 unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
36 const MCFixup &Fixup, bool IsPCRel) const override;
37};
38}
39
40RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
41 : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV,
Alex Bradburydd834842017-08-20 06:55:14 +000042 /*HasRelocationAddend*/ true) {}
Alex Bradbury6b2cca72016-11-01 23:47:30 +000043
44RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
45
46unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
47 const MCValue &Target,
48 const MCFixup &Fixup,
49 bool IsPCRel) const {
Alex Bradbury9d3f1252017-09-28 08:26:24 +000050 // Determine the type of the relocation
51 switch ((unsigned)Fixup.getKind()) {
52 default:
53 llvm_unreachable("invalid fixup kind!");
54 case FK_Data_4:
55 return ELF::R_RISCV_32;
56 case FK_Data_8:
57 return ELF::R_RISCV_64;
Alex Bradbury257d5b52018-05-23 12:36:18 +000058 case FK_Data_Add_1:
59 return ELF::R_RISCV_ADD8;
60 case FK_Data_Add_2:
61 return ELF::R_RISCV_ADD16;
62 case FK_Data_Add_4:
63 return ELF::R_RISCV_ADD32;
64 case FK_Data_Add_8:
65 return ELF::R_RISCV_ADD64;
66 case FK_Data_Sub_1:
67 return ELF::R_RISCV_SUB8;
68 case FK_Data_Sub_2:
69 return ELF::R_RISCV_SUB16;
70 case FK_Data_Sub_4:
71 return ELF::R_RISCV_SUB32;
72 case FK_Data_Sub_8:
73 return ELF::R_RISCV_SUB64;
Alex Bradbury9d3f1252017-09-28 08:26:24 +000074 case RISCV::fixup_riscv_hi20:
75 return ELF::R_RISCV_HI20;
76 case RISCV::fixup_riscv_lo12_i:
77 return ELF::R_RISCV_LO12_I;
78 case RISCV::fixup_riscv_lo12_s:
79 return ELF::R_RISCV_LO12_S;
80 case RISCV::fixup_riscv_pcrel_hi20:
81 return ELF::R_RISCV_PCREL_HI20;
Ahmed Charles646ab872018-02-06 00:55:23 +000082 case RISCV::fixup_riscv_pcrel_lo12_i:
83 return ELF::R_RISCV_PCREL_LO12_I;
84 case RISCV::fixup_riscv_pcrel_lo12_s:
85 return ELF::R_RISCV_PCREL_LO12_S;
Alex Bradbury8eb87e52019-02-15 09:43:46 +000086 case RISCV::fixup_riscv_got_hi20:
87 return ELF::R_RISCV_GOT_HI20;
Lewis Revillaa79a3f2019-04-04 14:13:37 +000088 case RISCV::fixup_riscv_tprel_hi20:
89 return ELF::R_RISCV_TPREL_HI20;
90 case RISCV::fixup_riscv_tprel_lo12_i:
91 return ELF::R_RISCV_TPREL_LO12_I;
92 case RISCV::fixup_riscv_tprel_lo12_s:
93 return ELF::R_RISCV_TPREL_LO12_S;
94 case RISCV::fixup_riscv_tprel_add:
95 return ELF::R_RISCV_TPREL_ADD;
Lewis Revilldf3cb472019-04-23 14:46:13 +000096 case RISCV::fixup_riscv_tls_got_hi20:
97 return ELF::R_RISCV_TLS_GOT_HI20;
98 case RISCV::fixup_riscv_tls_gd_hi20:
99 return ELF::R_RISCV_TLS_GD_HI20;
Alex Bradbury9d3f1252017-09-28 08:26:24 +0000100 case RISCV::fixup_riscv_jal:
101 return ELF::R_RISCV_JAL;
102 case RISCV::fixup_riscv_branch:
103 return ELF::R_RISCV_BRANCH;
Alex Bradburyf8f4b902017-12-07 13:19:57 +0000104 case RISCV::fixup_riscv_rvc_jump:
105 return ELF::R_RISCV_RVC_JUMP;
106 case RISCV::fixup_riscv_rvc_branch:
107 return ELF::R_RISCV_RVC_BRANCH;
Shiva Chen98f93892018-04-25 14:18:55 +0000108 case RISCV::fixup_riscv_call:
109 return ELF::R_RISCV_CALL;
Alex Bradburyf8078f62019-04-02 12:47:20 +0000110 case RISCV::fixup_riscv_call_plt:
111 return ELF::R_RISCV_CALL_PLT;
Shiva Chen43bfe842018-05-24 06:21:23 +0000112 case RISCV::fixup_riscv_relax:
113 return ELF::R_RISCV_RELAX;
Shiva Chen5af037f2019-01-30 11:16:59 +0000114 case RISCV::fixup_riscv_align:
115 return ELF::R_RISCV_ALIGN;
Alex Bradbury9d3f1252017-09-28 08:26:24 +0000116 }
Alex Bradbury6b2cca72016-11-01 23:47:30 +0000117}
118
Peter Collingbournedcd7d6c2018-05-21 19:20:29 +0000119std::unique_ptr<MCObjectTargetWriter>
120llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
121 return llvm::make_unique<RISCVELFObjectWriter>(OSABI, Is64Bit);
Alex Bradbury6b2cca72016-11-01 23:47:30 +0000122}