Blame - llvm/lib/Target/AMDGPU/Processors.td - toolchain/llvm-project

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Tom Stellard	c2516c6	2013-05-03 17:21:14 +0000	[diff] [blame]	1	//===-- Processors.td - R600 Processor definitions ------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	9
				10	class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
				11	: Processor<Name, itin, Features>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	12
				13	//===----------------------------------------------------------------------===//
				14	// R600
				15	//===----------------------------------------------------------------------===//
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	16	def : Proc<"r600", R600_VLIW5_Itin,
Matt Arsenault	8e00194	2016-06-02 18:37:16 +0000	[diff] [blame]	17	[FeatureR600, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	18
				19	def : Proc<"r630", R600_VLIW5_Itin,
				20	[FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	21
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	22	def : Proc<"rs880", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	23	[FeatureR600, FeatureWavefrontSize16]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	24
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	25	def : Proc<"rv670", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	26	[FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	27
				28	//===----------------------------------------------------------------------===//
				29	// R700
				30	//===----------------------------------------------------------------------===//
				31
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	32	def : Proc<"rv710", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	33	[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	34
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	35	def : Proc<"rv730", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	36	[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	37
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	38	def : Proc<"rv770", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	39	[FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	40
				41	//===----------------------------------------------------------------------===//
				42	// Evergreen
				43	//===----------------------------------------------------------------------===//
				44
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	45	def : Proc<"cedar", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	46	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32,
				47	FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	48
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	49	def : Proc<"redwood", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	50	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64,
				51	FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	52
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	53	def : Proc<"sumo", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	54	[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	55
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	56	def : Proc<"juniper", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	57	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	58
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	59	def : Proc<"cypress", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	60	[FeatureEvergreen, FeatureFP64, FeatureVertexCache,
				61	FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	62
				63	//===----------------------------------------------------------------------===//
				64	// Northern Islands
				65	//===----------------------------------------------------------------------===//
				66
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	67	def : Proc<"barts", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	68	[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	69
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	70	def : Proc<"turks", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	71	[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	72
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	73	def : Proc<"caicos", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	74	[FeatureNorthernIslands, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	75
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	76	def : Proc<"cayman", R600_VLIW4_Itin,
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	77	[FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	78
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	79	//===----------------------------------------------------------------------===//
				80	// Southern Islands
				81	//===----------------------------------------------------------------------===//
				82
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	83	def : ProcessorModel<"SI", SIFullSpeedModel,
Matt Arsenault	e83690c	2016-01-18 21:13:50 +0000	[diff] [blame]	84	[FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	85	>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	86
Matt Arsenault	e83690c	2016-01-18 21:13:50 +0000	[diff] [blame]	87	def : ProcessorModel<"tahiti", SIFullSpeedModel,
				88	[FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	89	>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	90
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	91	def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	92
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	93	def : ProcessorModel<"verde", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	94
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	95	def : ProcessorModel<"oland", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	96
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	97	def : ProcessorModel<"hainan", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	98
				99	//===----------------------------------------------------------------------===//
				100	// Sea Islands
				101	//===----------------------------------------------------------------------===//
				102
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	103	def : ProcessorModel<"bonaire", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	104	[FeatureISAVersion7_0_0]
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	105	>;
Tom Stellard	10b1502	2014-05-02 15:41:49 +0000	[diff] [blame]	106
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	107	def : ProcessorModel<"kabini", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	108	[FeatureISAVersion7_0_2]
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	109	>;
				110
				111	def : ProcessorModel<"kaveri", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	112	[FeatureISAVersion7_0_0]
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	113	>;
				114
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	115	def : ProcessorModel<"hawaii", SIFullSpeedModel,
				116	[FeatureISAVersion7_0_1]
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	117	>;
				118
				119	def : ProcessorModel<"mullins", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	120	[FeatureISAVersion7_0_2]>;
				121
				122	def : ProcessorModel<"gfx700", SIQuarterSpeedModel,
				123	[FeatureISAVersion7_0_0]
				124	>;
				125
				126	def : ProcessorModel<"gfx701", SIFullSpeedModel,
				127	[FeatureISAVersion7_0_1]
				128	>;
				129
				130	def : ProcessorModel<"gfx702", SIQuarterSpeedModel,
				131	[FeatureISAVersion7_0_2]
				132	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	133
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	134	//===----------------------------------------------------------------------===//
				135	// Volcanic Islands
				136	//===----------------------------------------------------------------------===//
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	137
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	138	def : ProcessorModel<"tonga", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	139	[FeatureISAVersion8_0_2]
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	140	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	141
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	142	def : ProcessorModel<"iceland", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	143	[FeatureISAVersion8_0_0]
Marek Olsak	4d00dd2	2015-03-09 15:48:09 +0000	[diff] [blame]	144	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	145
Tom Stellard	347ac79	2015-06-26 21:15:07 +0000	[diff] [blame]	146	def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	147	[FeatureISAVersion8_0_1]
Tom Stellard	347ac79	2015-06-26 21:15:07 +0000	[diff] [blame]	148	>;
Tom Stellard	d488605	2015-08-06 19:43:02 +0000	[diff] [blame]	149
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	150	def : ProcessorModel<"fiji", SIQuarterSpeedModel,
				151	[FeatureISAVersion8_0_3]
Tom Stellard	d488605	2015-08-06 19:43:02 +0000	[diff] [blame]	152	>;
Tom Stellard	afd6e2f	2015-11-13 17:06:32 +0000	[diff] [blame]	153
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	154	def : ProcessorModel<"stoney", SIQuarterSpeedModel,
				155	[FeatureISAVersion8_1_0]
Tom Stellard	afd6e2f	2015-11-13 17:06:32 +0000	[diff] [blame]	156	>;
Tom Stellard	9babad2	2016-03-24 15:31:05 +0000	[diff] [blame]	157
				158	def : ProcessorModel<"polaris10", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	159	[FeatureISAVersion8_0_3]
Tom Stellard	9babad2	2016-03-24 15:31:05 +0000	[diff] [blame]	160	>;
				161
				162	def : ProcessorModel<"polaris11", SIQuarterSpeedModel,
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	163	[FeatureISAVersion8_0_3]
Tom Stellard	9babad2	2016-03-24 15:31:05 +0000	[diff] [blame]	164	>;
Yaxun Liu	94add85	2016-10-26 16:37:56 +0000	[diff] [blame]	165
				166	def : ProcessorModel<"gfx800", SIQuarterSpeedModel,
				167	[FeatureISAVersion8_0_0]
				168	>;
				169
				170	def : ProcessorModel<"gfx801", SIQuarterSpeedModel,
				171	[FeatureISAVersion8_0_1]
				172	>;
				173
				174	def : ProcessorModel<"gfx802", SIQuarterSpeedModel,
				175	[FeatureISAVersion8_0_2]
				176	>;
				177
				178	def : ProcessorModel<"gfx803", SIQuarterSpeedModel,
				179	[FeatureISAVersion8_0_3]
				180	>;
				181
				182	def : ProcessorModel<"gfx804", SIQuarterSpeedModel,
				183	[FeatureISAVersion8_0_4]
				184	>;
				185
				186	def : ProcessorModel<"gfx810", SIQuarterSpeedModel,
				187	[FeatureISAVersion8_1_0]
				188	>;
				189
Matt Arsenault	e823d92	2017-02-18 18:29:53 +0000	[diff] [blame^]	190	def : ProcessorModel<"gfx900", SIQuarterSpeedModel,
				191	[FeatureGFX9, FeatureISAVersion9_0_0, FeatureLDSBankCount32]
				192	>;
				193
				194	def : ProcessorModel<"gfx901", SIQuarterSpeedModel,
				195	[FeatureGFX9, FeatureXNACK, FeatureISAVersion9_0_1, FeatureLDSBankCount32]
				196	>;