| Renato Golin | e07a22a | 2014-09-02 22:45:13 +0000 | [diff] [blame] | 1 | ; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s |
| Evan Cheng | c7ea8df | 2009-06-25 20:59:23 +0000 | [diff] [blame] | 2 | |
| 3 | define i64 @f1(i64 %a, i64 %b) { |
| Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 4 | ; CHECK-LABEL: f1: |
| Bob Wilson | 04580c8 | 2009-10-27 05:50:28 +0000 | [diff] [blame] | 5 | ; CHECK: subs r |
| 6 | ; CHECK: sbc r |
| Evan Cheng | c7ea8df | 2009-06-25 20:59:23 +0000 | [diff] [blame] | 7 | entry: |
| 8 | %tmp = sub i64 %a, %b |
| 9 | ret i64 %tmp |
| 10 | } |
| 11 | |
| 12 | define i64 @f2(i64 %a, i64 %b) { |
| Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 13 | ; CHECK-LABEL: f2: |
| Bob Wilson | 04580c8 | 2009-10-27 05:50:28 +0000 | [diff] [blame] | 14 | ; CHECK: adc r |
| 15 | ; CHECK: subs r |
| 16 | ; CHECK: sbc r |
| Evan Cheng | c7ea8df | 2009-06-25 20:59:23 +0000 | [diff] [blame] | 17 | entry: |
| 18 | %tmp1 = shl i64 %a, 1 |
| 19 | %tmp2 = sub i64 %tmp1, %b |
| 20 | ret i64 %tmp2 |
| 21 | } |
| Andrew Trick | 0ed5778 | 2011-04-23 03:55:32 +0000 | [diff] [blame] | 22 | |
| 23 | ; add with live carry |
| 24 | define i64 @f3(i32 %al, i32 %bl) { |
| Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 25 | ; CHECK-LABEL: f3: |
| Andrew Trick | 0ed5778 | 2011-04-23 03:55:32 +0000 | [diff] [blame] | 26 | ; CHECK: adds r |
| Andrew Trick | 0ed5778 | 2011-04-23 03:55:32 +0000 | [diff] [blame] | 27 | ; CHECK: adc r |
| 28 | entry: |
| 29 | ; unsigned wide add |
| 30 | %aw = zext i32 %al to i64 |
| 31 | %bw = zext i32 %bl to i64 |
| 32 | %cw = add i64 %aw, %bw |
| 33 | ; ch == carry bit |
| 34 | %ch = lshr i64 %cw, 32 |
| 35 | %dw = add i64 %ch, %bw |
| 36 | ret i64 %dw |
| 37 | } |
| Evan Cheng | 0b758ed | 2011-09-06 18:52:20 +0000 | [diff] [blame] | 38 | |
| 39 | ; rdar://10073745 |
| 40 | define i64 @f4(i64 %x) nounwind readnone { |
| 41 | entry: |
| Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 42 | ; CHECK-LABEL: f4: |
| Evan Cheng | 0b758ed | 2011-09-06 18:52:20 +0000 | [diff] [blame] | 43 | ; CHECK: rsbs r |
| 44 | ; CHECK: rsc r |
| 45 | %0 = sub nsw i64 0, %x |
| 46 | ret i64 %0 |
| 47 | } |
| Evan Cheng | 59ed7d4 | 2012-10-24 19:53:01 +0000 | [diff] [blame] | 48 | |
| 49 | ; rdar://12559385 |
| 50 | define i64 @f5(i32 %vi) { |
| 51 | entry: |
| Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 52 | ; CHECK-LABEL: f5: |
| Evan Cheng | 59ed7d4 | 2012-10-24 19:53:01 +0000 | [diff] [blame] | 53 | ; CHECK: movw [[REG:r[0-9]+]], #36102 |
| 54 | ; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]] |
| 55 | %v0 = zext i32 %vi to i64 |
| 56 | %v1 = xor i64 %v0, -155057456198619 |
| 57 | %v4 = add i64 %v1, 155057456198619 |
| 58 | %v5 = add i64 %v4, %v1 |
| 59 | ret i64 %v5 |
| 60 | } |