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gerrit-public.fairphone.software / toolchain / llvm-project / e8aab7480c2550b51fd60d6eb102b361e70931d7 / . / llvm / test / CodeGen / Thumb2 / float-cmp.ll
blob: 88d6c3b0adb86a2e84ee1d048d494a5a327c0f83 [file] [log] [blame]
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]1; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
2; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
Oliver Stannard37e4daa2014-10-01 09:02:17 +0000[diff] [blame]3; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]4; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
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8define i1 @cmp_f_false(float %a, float %b) {
9; CHECK-LABEL: cmp_f_false:
10; NONE: movs r0, #0
11; HARD: movs r0, #0
12 %1 = fcmp false float %a, %b
13 ret i1 %1
14}
15define i1 @cmp_f_oeq(float %a, float %b) {
16; CHECK-LABEL: cmp_f_oeq:
17; NONE: bl __aeabi_fcmpeq
18; HARD: vcmpe.f32
19; HARD: moveq r0, #1
20 %1 = fcmp oeq float %a, %b
21 ret i1 %1
22}
23define i1 @cmp_f_ogt(float %a, float %b) {
24; CHECK-LABEL: cmp_f_ogt:
25; NONE: bl __aeabi_fcmpgt
26; HARD: vcmpe.f32
27; HARD: movgt r0, #1
28 %1 = fcmp ogt float %a, %b
29 ret i1 %1
30}
31define i1 @cmp_f_oge(float %a, float %b) {
32; CHECK-LABEL: cmp_f_oge:
33; NONE: bl __aeabi_fcmpge
34; HARD: vcmpe.f32
35; HARD: movge r0, #1
36 %1 = fcmp oge float %a, %b
37 ret i1 %1
38}
39define i1 @cmp_f_olt(float %a, float %b) {
40; CHECK-LABEL: cmp_f_olt:
41; NONE: bl __aeabi_fcmplt
42; HARD: vcmpe.f32
43; HARD: movmi r0, #1
44 %1 = fcmp olt float %a, %b
45 ret i1 %1
46}
47define i1 @cmp_f_ole(float %a, float %b) {
48; CHECK-LABEL: cmp_f_ole:
49; NONE: bl __aeabi_fcmple
50; HARD: vcmpe.f32
51; HARD: movls r0, #1
52 %1 = fcmp ole float %a, %b
53 ret i1 %1
54}
55define i1 @cmp_f_one(float %a, float %b) {
56; CHECK-LABEL: cmp_f_one:
57; NONE: bl __aeabi_fcmpgt
58; NONE: bl __aeabi_fcmplt
59; HARD: vcmpe.f32
60; HARD: movmi r0, #1
61; HARD: movgt r0, #1
62 %1 = fcmp one float %a, %b
63 ret i1 %1
64}
65define i1 @cmp_f_ord(float %a, float %b) {
66; CHECK-LABEL: cmp_f_ord:
67; NONE: bl __aeabi_fcmpun
68; HARD: vcmpe.f32
69; HARD: movvc r0, #1
70 %1 = fcmp ord float %a, %b
71 ret i1 %1
72}define i1 @cmp_f_ueq(float %a, float %b) {
73; CHECK-LABEL: cmp_f_ueq:
74; NONE: bl __aeabi_fcmpeq
75; NONE: bl __aeabi_fcmpun
76; HARD: vcmpe.f32
77; HARD: moveq r0, #1
78; HARD: movvs r0, #1
79 %1 = fcmp ueq float %a, %b
80 ret i1 %1
81}
82define i1 @cmp_f_ugt(float %a, float %b) {
83; CHECK-LABEL: cmp_f_ugt:
84; NONE: bl __aeabi_fcmpgt
85; NONE: bl __aeabi_fcmpun
86; HARD: vcmpe.f32
87; HARD: movhi r0, #1
88 %1 = fcmp ugt float %a, %b
89 ret i1 %1
90}
91define i1 @cmp_f_uge(float %a, float %b) {
92; CHECK-LABEL: cmp_f_uge:
93; NONE: bl __aeabi_fcmpge
94; NONE: bl __aeabi_fcmpun
95; HARD: vcmpe.f32
96; HARD: movpl r0, #1
97 %1 = fcmp uge float %a, %b
98 ret i1 %1
99}
100define i1 @cmp_f_ult(float %a, float %b) {
101; CHECK-LABEL: cmp_f_ult:
102; NONE: bl __aeabi_fcmplt
103; NONE: bl __aeabi_fcmpun
104; HARD: vcmpe.f32
105; HARD: movlt r0, #1
106 %1 = fcmp ult float %a, %b
107 ret i1 %1
108}
109define i1 @cmp_f_ule(float %a, float %b) {
110; CHECK-LABEL: cmp_f_ule:
111; NONE: bl __aeabi_fcmple
112; NONE: bl __aeabi_fcmpun
113; HARD: vcmpe.f32
114; HARD: movle r0, #1
115 %1 = fcmp ule float %a, %b
116 ret i1 %1
117}
118define i1 @cmp_f_une(float %a, float %b) {
119; CHECK-LABEL: cmp_f_une:
120; NONE: bl __aeabi_fcmpeq
121; HARD: vcmpe.f32
122; HARD: movne r0, #1
123 %1 = fcmp une float %a, %b
124 ret i1 %1
125}
126define i1 @cmp_f_uno(float %a, float %b) {
127; CHECK-LABEL: cmp_f_uno:
128; NONE: bl __aeabi_fcmpun
129; HARD: vcmpe.f32
130; HARD: movvs r0, #1
131 %1 = fcmp uno float %a, %b
132 ret i1 %1
133}
134define i1 @cmp_f_true(float %a, float %b) {
135; CHECK-LABEL: cmp_f_true:
136; NONE: movs r0, #1
137; HARD: movs r0, #1
138 %1 = fcmp true float %a, %b
139 ret i1 %1
140}
141
142define i1 @cmp_d_false(double %a, double %b) {
143; CHECK-LABEL: cmp_d_false:
144; NONE: movs r0, #0
145; HARD: movs r0, #0
146 %1 = fcmp false double %a, %b
147 ret i1 %1
148}
149define i1 @cmp_d_oeq(double %a, double %b) {
150; CHECK-LABEL: cmp_d_oeq:
151; NONE: bl __aeabi_dcmpeq
152; SP: bl __aeabi_dcmpeq
153; DP: vcmpe.f64
154; DP: moveq r0, #1
155 %1 = fcmp oeq double %a, %b
156 ret i1 %1
157}
158define i1 @cmp_d_ogt(double %a, double %b) {
159; CHECK-LABEL: cmp_d_ogt:
160; NONE: bl __aeabi_dcmpgt
161; SP: bl __aeabi_dcmpgt
162; DP: vcmpe.f64
163; DP: movgt r0, #1
164 %1 = fcmp ogt double %a, %b
165 ret i1 %1
166}
167define i1 @cmp_d_oge(double %a, double %b) {
168; CHECK-LABEL: cmp_d_oge:
169; NONE: bl __aeabi_dcmpge
170; SP: bl __aeabi_dcmpge
171; DP: vcmpe.f64
172; DP: movge r0, #1
173 %1 = fcmp oge double %a, %b
174 ret i1 %1
175}
176define i1 @cmp_d_olt(double %a, double %b) {
177; CHECK-LABEL: cmp_d_olt:
178; NONE: bl __aeabi_dcmplt
179; SP: bl __aeabi_dcmplt
180; DP: vcmpe.f64
181; DP: movmi r0, #1
182 %1 = fcmp olt double %a, %b
183 ret i1 %1
184}
185define i1 @cmp_d_ole(double %a, double %b) {
186; CHECK-LABEL: cmp_d_ole:
187; NONE: bl __aeabi_dcmple
188; SP: bl __aeabi_dcmple
189; DP: vcmpe.f64
190; DP: movls r0, #1
191 %1 = fcmp ole double %a, %b
192 ret i1 %1
193}
194define i1 @cmp_d_one(double %a, double %b) {
195; CHECK-LABEL: cmp_d_one:
196; NONE: bl __aeabi_dcmpgt
197; NONE: bl __aeabi_dcmplt
198; SP: bl __aeabi_dcmpgt
199; SP: bl __aeabi_dcmplt
200; DP: vcmpe.f64
201; DP: movmi r0, #1
202; DP: movgt r0, #1
203 %1 = fcmp one double %a, %b
204 ret i1 %1
205}
206define i1 @cmp_d_ord(double %a, double %b) {
207; CHECK-LABEL: cmp_d_ord:
208; NONE: bl __aeabi_dcmpun
209; SP: bl __aeabi_dcmpun
210; DP: vcmpe.f64
211; DP: movvc r0, #1
212 %1 = fcmp ord double %a, %b
213 ret i1 %1
214}
215define i1 @cmp_d_ugt(double %a, double %b) {
216; CHECK-LABEL: cmp_d_ugt:
217; NONE: bl __aeabi_dcmpgt
218; NONE: bl __aeabi_dcmpun
219; SP: bl __aeabi_dcmpgt
220; SP: bl __aeabi_dcmpun
221; DP: vcmpe.f64
222; DP: movhi r0, #1
223 %1 = fcmp ugt double %a, %b
224 ret i1 %1
225}
226
227define i1 @cmp_d_ult(double %a, double %b) {
228; CHECK-LABEL: cmp_d_ult:
229; NONE: bl __aeabi_dcmplt
230; NONE: bl __aeabi_dcmpun
231; SP: bl __aeabi_dcmplt
232; SP: bl __aeabi_dcmpun
233; DP: vcmpe.f64
234; DP: movlt r0, #1
235 %1 = fcmp ult double %a, %b
236 ret i1 %1
237}
238
239
240define i1 @cmp_d_uno(double %a, double %b) {
241; CHECK-LABEL: cmp_d_uno:
242; NONE: bl __aeabi_dcmpun
243; SP: bl __aeabi_dcmpun
244; DP: vcmpe.f64
245; DP: movvs r0, #1
246 %1 = fcmp uno double %a, %b
247 ret i1 %1
248}
249define i1 @cmp_d_true(double %a, double %b) {
250; CHECK-LABEL: cmp_d_true:
251; NONE: movs r0, #1
252; HARD: movs r0, #1
253 %1 = fcmp true double %a, %b
254 ret i1 %1
255}
256define i1 @cmp_d_ueq(double %a, double %b) {
257; CHECK-LABEL: cmp_d_ueq:
258; NONE: bl __aeabi_dcmpeq
259; NONE: bl __aeabi_dcmpun
260; SP: bl __aeabi_dcmpeq
261; SP: bl __aeabi_dcmpun
262; DP: vcmpe.f64
263; DP: moveq r0, #1
264; DP: movvs r0, #1
265 %1 = fcmp ueq double %a, %b
266 ret i1 %1
267}
268
269define i1 @cmp_d_uge(double %a, double %b) {
270; CHECK-LABEL: cmp_d_uge:
271; NONE: bl __aeabi_dcmpge
272; NONE: bl __aeabi_dcmpun
273; SP: bl __aeabi_dcmpge
274; SP: bl __aeabi_dcmpun
275; DP: vcmpe.f64
276; DP: movpl r0, #1
277 %1 = fcmp uge double %a, %b
278 ret i1 %1
279}
280
281define i1 @cmp_d_ule(double %a, double %b) {
282; CHECK-LABEL: cmp_d_ule:
283; NONE: bl __aeabi_dcmple
284; NONE: bl __aeabi_dcmpun
285; SP: bl __aeabi_dcmple
286; SP: bl __aeabi_dcmpun
287; DP: vcmpe.f64
288; DP: movle r0, #1
289 %1 = fcmp ule double %a, %b
290 ret i1 %1
291}
292
293define i1 @cmp_d_une(double %a, double %b) {
294; CHECK-LABEL: cmp_d_une:
295; NONE: bl __aeabi_dcmpeq
296; SP: bl __aeabi_dcmpeq
297; DP: vcmpe.f64
298; DP: movne r0, #1
299 %1 = fcmp une double %a, %b
300 ret i1 %1
301}