Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame^] | 1 | //===-- MipsHazardSchedule.cpp - Workaround pipeline hazards---------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This pass is used to workaround certain pipeline hazards. For now, this covers |
| 11 | /// compact branch hazards. In future this pass can be extended to other pipeline |
| 12 | /// hazards, such as various MIPS1 hazards, processor errata that require |
| 13 | /// instruction reorganization, etc. |
| 14 | /// |
| 15 | /// This pass has to run after the delay slot filler as that pass can introduce |
| 16 | /// pipeline hazards, hence the existing hazard recognizer is not suitable. |
| 17 | /// |
| 18 | /// Hazards handled: forbidden slots for MIPSR6. |
| 19 | /// |
| 20 | /// A forbidden slot hazard occurs when a compact branch instruction is executed |
| 21 | /// and the adjacent instruction in memory is a control transfer instruction such |
| 22 | /// as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE. |
| 23 | /// |
| 24 | /// For example: |
| 25 | /// |
| 26 | /// 0x8004 bnec a1,v0,<P+0x18> |
| 27 | /// 0x8008 beqc a1,a2,<P+0x54> |
| 28 | /// |
| 29 | /// In such cases, the processor is required to signal a Reserved Instruction |
| 30 | /// exception. |
| 31 | /// |
| 32 | /// Here, if the instruction at 0x8004 is executed, the processor will raise an |
| 33 | /// exception as there is a control transfer instruction at 0x8008. |
| 34 | /// |
| 35 | /// There are two sources of forbidden slot hazards: |
| 36 | /// |
| 37 | /// A) A previous pass has created a compact branch directly. |
| 38 | /// B) Transforming a delay slot branch into compact branch. This case can be |
| 39 | /// difficult to process as lookahead for hazards is insufficent, as |
| 40 | /// backwards delay slot fillling can also produce hazards in previously |
| 41 | /// processed instuctions. |
| 42 | /// |
| 43 | //===----------------------------------------------------------------------===// |
| 44 | |
| 45 | #include "Mips.h" |
| 46 | #include "MipsInstrInfo.h" |
| 47 | #include "MipsSEInstrInfo.h" |
| 48 | #include "MipsTargetMachine.h" |
| 49 | #include "llvm/IR/Function.h" |
| 50 | #include "llvm/ADT/Statistic.h" |
| 51 | #include "llvm/CodeGen/MachineFunctionPass.h" |
| 52 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 53 | #include "llvm/Support/CommandLine.h" |
| 54 | #include "llvm/Target/TargetInstrInfo.h" |
| 55 | #include "llvm/Target/TargetMachine.h" |
| 56 | #include "llvm/Target/TargetRegisterInfo.h" |
| 57 | |
| 58 | using namespace llvm; |
| 59 | |
| 60 | #define DEBUG_TYPE "mips-hazard-schedule" |
| 61 | |
| 62 | STATISTIC(NumInsertedNops, "Number of nops inserted"); |
| 63 | |
| 64 | namespace { |
| 65 | |
| 66 | typedef MachineBasicBlock::iterator Iter; |
| 67 | typedef MachineBasicBlock::reverse_iterator ReverseIter; |
| 68 | |
| 69 | class MipsHazardSchedule : public MachineFunctionPass { |
| 70 | |
| 71 | public: |
| 72 | MipsHazardSchedule(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm) {} |
| 73 | |
| 74 | const char *getPassName() const override { return "Mips Hazard Schedule"; } |
| 75 | |
| 76 | bool runOnMachineFunction(MachineFunction &F) override; |
| 77 | |
| 78 | private: |
| 79 | static char ID; |
| 80 | const TargetMachine &TM; |
| 81 | }; |
| 82 | |
| 83 | char MipsHazardSchedule::ID = 0; |
| 84 | } // end of anonymous namespace |
| 85 | |
| 86 | /// Returns a pass that clears pipeline hazards. |
| 87 | FunctionPass *llvm::createMipsHazardSchedule(MipsTargetMachine &tm) { |
| 88 | return new MipsHazardSchedule(tm); |
| 89 | } |
| 90 | |
| 91 | bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) { |
| 92 | |
| 93 | const MipsSubtarget *STI = |
| 94 | &static_cast<const MipsSubtarget &>(MF.getSubtarget()); |
| 95 | |
| 96 | // Forbidden slot hazards are only defined for MIPSR6. |
| 97 | if (!STI->hasMips32r6() || STI->inMicroMipsMode()) |
| 98 | return false; |
| 99 | |
| 100 | bool Changed = false; |
| 101 | const MipsInstrInfo *TII = STI->getInstrInfo(); |
| 102 | |
| 103 | for (MachineFunction::iterator FI = MF.begin(); FI != MF.end(); ++FI) { |
| 104 | for (Iter I = FI->begin(); I != FI->end(); ++I) { |
| 105 | |
| 106 | // Forbidden slot hazard handling. Use lookahead over state. |
| 107 | if (!TII->HasForbiddenSlot(*I)) |
| 108 | continue; |
| 109 | |
| 110 | bool InsertNop = false; |
| 111 | // Next instruction in the basic block. |
| 112 | if (std::next(I) != FI->end() && |
| 113 | !TII->SafeInForbiddenSlot(*std::next(I))) { |
| 114 | InsertNop = true; |
| 115 | } else { |
| 116 | // Next instruction in the physical successor basic block. |
| 117 | for (auto *Succ : FI->successors()) { |
| 118 | if (FI->isLayoutSuccessor(Succ) && |
| 119 | Succ->getFirstNonDebugInstr() != Succ->end() && |
| 120 | !TII->SafeInForbiddenSlot(*Succ->getFirstNonDebugInstr())) { |
| 121 | InsertNop = true; |
| 122 | break; |
| 123 | } |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | if (InsertNop) { |
| 128 | Changed = true; |
| 129 | MIBundleBuilder(I) |
| 130 | .append(BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP))); |
| 131 | NumInsertedNops++; |
| 132 | } |
| 133 | } |
| 134 | } |
| 135 | return Changed; |
| 136 | } |