Tom Stellard | ca16621 | 2017-01-30 21:56:46 +0000 | [diff] [blame] | 1 | //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This file declares the targeting of the InstructionSelector class for |
| 11 | /// AMDGPU. |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H |
| 15 | #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H |
| 16 | |
Yaxun Liu | 1a14bfa | 2017-03-27 14:04:01 +0000 | [diff] [blame] | 17 | #include "AMDGPU.h" |
Tom Stellard | ca16621 | 2017-01-30 21:56:46 +0000 | [diff] [blame] | 18 | #include "llvm/ADT/ArrayRef.h" |
| 19 | #include "llvm/ADT/SmallVector.h" |
Chandler Carruth | 6bda14b | 2017-06-06 11:49:48 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" |
Tom Stellard | ca16621 | 2017-01-30 21:56:46 +0000 | [diff] [blame] | 21 | |
| 22 | namespace llvm { |
| 23 | |
| 24 | class AMDGPUInstrInfo; |
| 25 | class AMDGPURegisterBankInfo; |
| 26 | class MachineInstr; |
| 27 | class MachineOperand; |
| 28 | class MachineRegisterInfo; |
| 29 | class SIInstrInfo; |
| 30 | class SIRegisterInfo; |
| 31 | class SISubtarget; |
| 32 | |
| 33 | class AMDGPUInstructionSelector : public InstructionSelector { |
| 34 | public: |
| 35 | AMDGPUInstructionSelector(const SISubtarget &STI, |
| 36 | const AMDGPURegisterBankInfo &RBI); |
| 37 | |
Daniel Sanders | f76f315 | 2017-11-16 00:46:35 +0000 | [diff] [blame] | 38 | bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override; |
| 39 | |
Tom Stellard | ca16621 | 2017-01-30 21:56:46 +0000 | [diff] [blame] | 40 | private: |
| 41 | struct GEPInfo { |
| 42 | const MachineInstr &GEP; |
| 43 | SmallVector<unsigned, 2> SgprParts; |
| 44 | SmallVector<unsigned, 2> VgprParts; |
| 45 | int64_t Imm; |
| 46 | GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } |
| 47 | }; |
| 48 | |
| 49 | MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const; |
| 50 | bool selectG_CONSTANT(MachineInstr &I) const; |
| 51 | bool selectG_ADD(MachineInstr &I) const; |
| 52 | bool selectG_GEP(MachineInstr &I) const; |
| 53 | bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; |
| 54 | void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, |
| 55 | SmallVectorImpl<GEPInfo> &AddrInfo) const; |
| 56 | bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const; |
| 57 | bool selectG_LOAD(MachineInstr &I) const; |
| 58 | bool selectG_STORE(MachineInstr &I) const; |
| 59 | |
| 60 | const SIInstrInfo &TII; |
| 61 | const SIRegisterInfo &TRI; |
| 62 | const AMDGPURegisterBankInfo &RBI; |
Yaxun Liu | 1a14bfa | 2017-03-27 14:04:01 +0000 | [diff] [blame] | 63 | protected: |
| 64 | AMDGPUAS AMDGPUASI; |
Tom Stellard | ca16621 | 2017-01-30 21:56:46 +0000 | [diff] [blame] | 65 | }; |
| 66 | |
| 67 | } // End llvm namespace. |
| 68 | #endif |