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gerrit-public.fairphone.software / toolchain / llvm-project / e93c63d468d36e67cb15d183ecc6b8216c87c138 / . / llvm / test / CodeGen / AArch64 / arm64-code-model-large-abs.ll
blob: 171941748c8fd8aff593730ffdca998468e98359 [file] [log] [blame]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]1; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large < %s | FileCheck %s
2
3@var8 = global i8 0
4@var16 = global i16 0
5@var32 = global i32 0
6@var64 = global i64 0
7
8define i8* @global_addr() {
9; CHECK-LABEL: global_addr:
10 ret i8* @var8
11 ; The movz/movk calculation should end up returned directly in x0.
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]12; CHECK: movz x0, #:abs_g0_nc:var8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]13; CHECK: movk x0, #:abs_g1_nc:var8
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]14; CHECK: movk x0, #:abs_g2_nc:var8
15; CHECK: movk x0, #:abs_g3:var8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]16; CHECK-NEXT: ret
17}
18
19define i8 @global_i8() {
20; CHECK-LABEL: global_i8:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]21 %val = load i8, i8* @var8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]22 ret i8 %val
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]23; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]24; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]25; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
26; CHECK: movk x[[ADDR_REG]], #:abs_g3:var8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]27; CHECK: ldrb w0, [x[[ADDR_REG]]]
28}
29
30define i16 @global_i16() {
31; CHECK-LABEL: global_i16:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]32 %val = load i16, i16* @var16
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]33 ret i16 %val
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]34; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]35; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]36; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
37; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]38; CHECK: ldrh w0, [x[[ADDR_REG]]]
39}
40
41define i32 @global_i32() {
42; CHECK-LABEL: global_i32:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]43 %val = load i32, i32* @var32
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]44 ret i32 %val
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]45; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var32
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]46; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]47; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
48; CHECK: movk x[[ADDR_REG]], #:abs_g3:var32
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]49; CHECK: ldr w0, [x[[ADDR_REG]]]
50}
51
52define i64 @global_i64() {
53; CHECK-LABEL: global_i64:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]54 %val = load i64, i64* @var64
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]55 ret i64 %val
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]56; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var64
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]57; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]58; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
59; CHECK: movk x[[ADDR_REG]], #:abs_g3:var64
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]60; CHECK: ldr x0, [x[[ADDR_REG]]]
61}
62
63define <2 x i64> @constpool() {
64; CHECK-LABEL: constpool:
65 ret <2 x i64> <i64 123456789, i64 987654321100>
66
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]67; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]68; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:[[CPADDR]]
Evandro Menezes7960b2e2017-01-18 18:57:08 +0000[diff] [blame]69; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
70; CHECK: movk x[[ADDR_REG]], #:abs_g3:[[CPADDR]]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]71; CHECK: ldr q0, [x[[ADDR_REG]]]
72}