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gerrit-public.fairphone.software / toolchain / llvm-project / e93c63d468d36e67cb15d183ecc6b8216c87c138 / . / llvm / test / CodeGen / AArch64 / arm64-large-frame.ll
blob: d1244e73b0f333c7f82e0ce452155b5e6dc4990d [file] [log] [blame]
Chad Rosierd0165742015-12-21 14:43:45 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -disable-fp-elim -disable-post-ra < %s | FileCheck %s
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]2declare void @use_addr(i8*)
3
4@addr = global i8* null
5
6define void @test_bigframe() {
7; CHECK-LABEL: test_bigframe:
8; CHECK: .cfi_startproc
9
10 %var1 = alloca i8, i32 20000000
11 %var2 = alloca i8, i32 16
12 %var3 = alloca i8, i32 20000000
13
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]14; CHECK: sub sp, sp, #4095, lsl #12
15; CHECK: sub sp, sp, #4095, lsl #12
16; CHECK: sub sp, sp, #1575, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]17; CHECK: sub sp, sp, #2576
18; CHECK: .cfi_def_cfa_offset 40000032
19
20
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]21; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
22; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]23; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
24 store volatile i8* %var1, i8** @addr
25
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]26 %var1plus2 = getelementptr i8, i8* %var1, i32 2
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]27 store volatile i8* %var1plus2, i8** @addr
28
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]29; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
30; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]31; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
32 store volatile i8* %var2, i8** @addr
33
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]34 %var2plus2 = getelementptr i8, i8* %var2, i32 2
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]35 store volatile i8* %var2plus2, i8** @addr
36
37 store volatile i8* %var3, i8** @addr
38
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]39 %var3plus2 = getelementptr i8, i8* %var3, i32 2
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]40 store volatile i8* %var3plus2, i8** @addr
41
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]42; CHECK: add sp, sp, #4095, lsl #12
43; CHECK: add sp, sp, #4095, lsl #12
44; CHECK: add sp, sp, #1575, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]45; CHECK: add sp, sp, #2576
46; CHECK: .cfi_endproc
47 ret void
48}
49
50define void @test_mediumframe() {
51; CHECK-LABEL: test_mediumframe:
52 %var1 = alloca i8, i32 1000000
53 %var2 = alloca i8, i32 16
54 %var3 = alloca i8, i32 1000000
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]55; CHECK: sub sp, sp, #488, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]56; CHECK-NEXT: sub sp, sp, #1168
57
58 store volatile i8* %var1, i8** @addr
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]59; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]60; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #592
61
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]62; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #244, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]63; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #576
64
65 store volatile i8* %var2, i8** @addr
Tim Northovercfd6e662014-04-30 11:19:15 +0000[diff] [blame]66; CHECK: add sp, sp, #488, lsl #12
Tim Northover52d32832014-04-22 12:45:47 +0000[diff] [blame]67; CHECK: add sp, sp, #1168
68 ret void
69}