| Alexander Timofeev | 982aee6 | 2017-07-04 17:32:00 +0000 | [diff] [blame] | 1 | ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s |
| 2 | ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s |
| Matt Arsenault | bc63770 | 2013-11-14 07:57:29 +0000 | [diff] [blame] | 3 | |
| 4 | ; Copy VGPR -> SGPR used twice as an instruction operand, which is then |
| 5 | ; used in an REG_SEQUENCE that also needs to be handled. |
| 6 | |
| Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 7 | ; SI-LABEL: {{^}}test_dup_operands: |
| Dmitry Preobrazhensky | a0342dc | 2017-11-20 18:24:21 +0000 | [diff] [blame] | 8 | ; SI: v_add_{{[iu]}}32_e32 |
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 9 | define amdgpu_kernel void @test_dup_operands(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %in) { |
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 10 | %a = load <2 x i32>, <2 x i32> addrspace(1)* %in |
| Matt Arsenault | bc63770 | 2013-11-14 07:57:29 +0000 | [diff] [blame] | 11 | %lo = extractelement <2 x i32> %a, i32 0 |
| 12 | %hi = extractelement <2 x i32> %a, i32 1 |
| 13 | %add = add i32 %lo, %lo |
| 14 | %vec0 = insertelement <2 x i32> undef, i32 %add, i32 0 |
| 15 | %vec1 = insertelement <2 x i32> %vec0, i32 %hi, i32 1 |
| 16 | store <2 x i32> %vec1, <2 x i32> addrspace(1)* %out, align 8 |
| 17 | ret void |
| 18 | } |
| 19 | |