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gerrit-public.fairphone.software / toolchain / llvm-project / e93c63d468d36e67cb15d183ecc6b8216c87c138 / . / llvm / test / CodeGen / PowerPC / swaps-le-6.ll
blob: d573441f2cc9c37cbb3d807ebb0608f5917a4fa0 [file] [log] [blame]
Nemanja Ivanovic6e7879c2016-09-22 09:52:19 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs -mcpu=pwr8 \
2; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
3
4; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P9 \
6; RUN: --implicit-check-not xxswapd
7
8; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
9; RUN: -verify-machineinstrs -mattr=-power9-vector < %s | FileCheck %s
Bill Schmidt2be80542015-07-21 21:40:17 +0000[diff] [blame]10
11; These tests verify that VSX swap optimization works when loading a scalar
12; into a vector register.
13
14
15@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
16@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
17@y = global double 1.780000e+00, align 8
18
19define void @bar0() {
20entry:
21 %0 = load <2 x double>, <2 x double>* @x, align 16
22 %1 = load double, double* @y, align 8
23 %vecins = insertelement <2 x double> %0, double %1, i32 0
24 store <2 x double> %vecins, <2 x double>* @z, align 16
25 ret void
26}
27
28; CHECK-LABEL: @bar0
29; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
30; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
Bill Schmidt34af5e12015-11-10 21:38:26 +0000[diff] [blame]31; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
Bill Schmidt2be80542015-07-21 21:40:17 +0000[diff] [blame]32; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1
33; CHECK: stxvd2x [[REG5]]
34
Nemanja Ivanovic6e7879c2016-09-22 09:52:19 +0000[diff] [blame]35; CHECK-P9-LABEL: @bar0
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame]36; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]37; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
Nemanja Ivanovic6e7879c2016-09-22 09:52:19 +0000[diff] [blame]38; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]39; CHECK-P9: xxpermdi [[REG5:[0-9]+]], [[REG1]], [[REG4]], 1
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame]40; CHECK-P9: stxvx [[REG5]]
Nemanja Ivanovic6e7879c2016-09-22 09:52:19 +0000[diff] [blame]41
Bill Schmidt2be80542015-07-21 21:40:17 +0000[diff] [blame]42define void @bar1() {
43entry:
44 %0 = load <2 x double>, <2 x double>* @x, align 16
45 %1 = load double, double* @y, align 8
46 %vecins = insertelement <2 x double> %0, double %1, i32 1
47 store <2 x double> %vecins, <2 x double>* @z, align 16
48 ret void
49}
50
51; CHECK-LABEL: @bar1
52; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
53; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
Bill Schmidt34af5e12015-11-10 21:38:26 +0000[diff] [blame]54; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
Bill Schmidt2be80542015-07-21 21:40:17 +0000[diff] [blame]55; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]]
56; CHECK: stxvd2x [[REG5]]
57
Nemanja Ivanovic6e7879c2016-09-22 09:52:19 +0000[diff] [blame]58; CHECK-P9-LABEL: @bar1
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame]59; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]60; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
Nemanja Ivanovic6e7879c2016-09-22 09:52:19 +0000[diff] [blame]61; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
Nemanja Ivanovic6354d232016-10-04 11:25:52 +0000[diff] [blame]62; CHECK-P9: xxmrgld [[REG5:[0-9]+]], [[REG4]], [[REG1]]
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame]63; CHECK-P9: stxvx [[REG5]]
Nemanja Ivanovic6e7879c2016-09-22 09:52:19 +0000[diff] [blame]64