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Ulrich Weigand9e3577f2013-05-06 16:17:29 +00001; Test 128-bit addition in which the second operand is variable.
2;
Richard Sandifordfac8b102013-07-19 16:37:00 +00003; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00005
Richard Sandiforded1fab62013-07-03 10:10:02 +00006declare i128 *@foo()
7
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00008; Test register addition.
9define void @f1(i128 *%ptr) {
Stephen Lind24ab202013-07-14 06:24:09 +000010; CHECK-LABEL: f1:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000011; CHECK: algr
12; CHECK: alcgr
13; CHECK: br %r14
David Blaikiea79ac142015-02-27 21:17:42 +000014 %value = load i128 , i128 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000015 %add = add i128 %value, %value
16 store i128 %add, i128 *%ptr
17 ret void
18}
19
20; Test memory addition with no offset. Making the load of %a volatile
21; should force the memory operand to be %b.
22define void @f2(i128 *%aptr, i64 %addr) {
Stephen Lind24ab202013-07-14 06:24:09 +000023; CHECK-LABEL: f2:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000024; CHECK: alg {{%r[0-5]}}, 8(%r3)
25; CHECK: alcg {{%r[0-5]}}, 0(%r3)
26; CHECK: br %r14
27 %bptr = inttoptr i64 %addr to i128 *
David Blaikiea79ac142015-02-27 21:17:42 +000028 %a = load volatile i128 , i128 *%aptr
29 %b = load i128 , i128 *%bptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000030 %add = add i128 %a, %b
31 store i128 %add, i128 *%aptr
32 ret void
33}
34
35; Test the highest aligned offset that is in range of both ALG and ALCG.
36define void @f3(i128 *%aptr, i64 %base) {
Stephen Lind24ab202013-07-14 06:24:09 +000037; CHECK-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000038; CHECK: alg {{%r[0-5]}}, 524280(%r3)
39; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
40; CHECK: br %r14
41 %addr = add i64 %base, 524272
42 %bptr = inttoptr i64 %addr to i128 *
David Blaikiea79ac142015-02-27 21:17:42 +000043 %a = load volatile i128 , i128 *%aptr
44 %b = load i128 , i128 *%bptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000045 %add = add i128 %a, %b
46 store i128 %add, i128 *%aptr
47 ret void
48}
49
50; Test the next doubleword up, which requires separate address logic for ALG.
51define void @f4(i128 *%aptr, i64 %base) {
Stephen Lind24ab202013-07-14 06:24:09 +000052; CHECK-LABEL: f4:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000053; CHECK: lgr [[BASE:%r[1-5]]], %r3
54; CHECK: agfi [[BASE]], 524288
55; CHECK: alg {{%r[0-5]}}, 0([[BASE]])
56; CHECK: alcg {{%r[0-5]}}, 524280(%r3)
57; CHECK: br %r14
58 %addr = add i64 %base, 524280
59 %bptr = inttoptr i64 %addr to i128 *
David Blaikiea79ac142015-02-27 21:17:42 +000060 %a = load volatile i128 , i128 *%aptr
61 %b = load i128 , i128 *%bptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000062 %add = add i128 %a, %b
63 store i128 %add, i128 *%aptr
64 ret void
65}
66
67; Test the next doubleword after that, which requires separate logic for
68; both instructions. It would be better to create an anchor at 524288
69; that both instructions can use, but that isn't implemented yet.
70define void @f5(i128 *%aptr, i64 %base) {
Stephen Lind24ab202013-07-14 06:24:09 +000071; CHECK-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000072; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}})
73; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
74; CHECK: br %r14
75 %addr = add i64 %base, 524288
76 %bptr = inttoptr i64 %addr to i128 *
David Blaikiea79ac142015-02-27 21:17:42 +000077 %a = load volatile i128 , i128 *%aptr
78 %b = load i128 , i128 *%bptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000079 %add = add i128 %a, %b
80 store i128 %add, i128 *%aptr
81 ret void
82}
83
84; Test the lowest displacement that is in range of both ALG and ALCG.
85define void @f6(i128 *%aptr, i64 %base) {
Stephen Lind24ab202013-07-14 06:24:09 +000086; CHECK-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000087; CHECK: alg {{%r[0-5]}}, -524280(%r3)
88; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
89; CHECK: br %r14
90 %addr = add i64 %base, -524288
91 %bptr = inttoptr i64 %addr to i128 *
David Blaikiea79ac142015-02-27 21:17:42 +000092 %a = load volatile i128 , i128 *%aptr
93 %b = load i128 , i128 *%bptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000094 %add = add i128 %a, %b
95 store i128 %add, i128 *%aptr
96 ret void
97}
98
99; Test the next doubleword down, which is out of range of the ALCG.
100define void @f7(i128 *%aptr, i64 %base) {
Stephen Lind24ab202013-07-14 06:24:09 +0000101; CHECK-LABEL: f7:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000102; CHECK: alg {{%r[0-5]}}, -524288(%r3)
103; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
104; CHECK: br %r14
105 %addr = add i64 %base, -524296
106 %bptr = inttoptr i64 %addr to i128 *
David Blaikiea79ac142015-02-27 21:17:42 +0000107 %a = load volatile i128 , i128 *%aptr
108 %b = load i128 , i128 *%bptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000109 %add = add i128 %a, %b
110 store i128 %add, i128 *%aptr
111 ret void
112}
113
Richard Sandiforded1fab62013-07-03 10:10:02 +0000114; Check that additions of spilled values can use ALG and ALCG rather than
115; ALGR and ALCGR.
116define void @f8(i128 *%ptr0) {
Stephen Lind24ab202013-07-14 06:24:09 +0000117; CHECK-LABEL: f8:
Richard Sandiforded1fab62013-07-03 10:10:02 +0000118; CHECK: brasl %r14, foo@PLT
119; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
120; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
121; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000122 %ptr1 = getelementptr i128, i128 *%ptr0, i128 2
123 %ptr2 = getelementptr i128, i128 *%ptr0, i128 4
124 %ptr3 = getelementptr i128, i128 *%ptr0, i128 6
125 %ptr4 = getelementptr i128, i128 *%ptr0, i128 8
Richard Sandiforded1fab62013-07-03 10:10:02 +0000126
David Blaikiea79ac142015-02-27 21:17:42 +0000127 %val0 = load i128 , i128 *%ptr0
128 %val1 = load i128 , i128 *%ptr1
129 %val2 = load i128 , i128 *%ptr2
130 %val3 = load i128 , i128 *%ptr3
131 %val4 = load i128 , i128 *%ptr4
Richard Sandiforded1fab62013-07-03 10:10:02 +0000132
133 %retptr = call i128 *@foo()
134
David Blaikiea79ac142015-02-27 21:17:42 +0000135 %ret = load i128 , i128 *%retptr
Richard Sandiforded1fab62013-07-03 10:10:02 +0000136 %add0 = add i128 %ret, %val0
137 %add1 = add i128 %add0, %val1
138 %add2 = add i128 %add1, %val2
139 %add3 = add i128 %add2, %val3
140 %add4 = add i128 %add3, %val4
141 store i128 %add4, i128 *%retptr
142
143 ret void
144}