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gerrit-public.fairphone.software / toolchain / llvm-project / e93c63d468d36e67cb15d183ecc6b8216c87c138 / . / llvm / test / CodeGen / SystemZ / int-move-03.ll
blob: 60eb0042ca873a0f5d4f252db7df5965366d56cf [file] [log] [blame]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]1; Test 64-bit GPR loads.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Check LG with no displacement.
6define i64 @f1(i64 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]7; CHECK-LABEL: f1:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]8; CHECK: lg %r2, 0(%r2)
9; CHECK: br %r14
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]10 %val = load i64 , i64 *%src
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]11 ret i64 %val
12}
13
14; Check the high end of the aligned LG range.
15define i64 @f2(i64 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]16; CHECK-LABEL: f2:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]17; CHECK: lg %r2, 524280(%r2)
18; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]19 %ptr = getelementptr i64, i64 *%src, i64 65535
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]20 %val = load i64 , i64 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]21 ret i64 %val
22}
23
24; Check the next doubleword up, which needs separate address logic.
25; Other sequences besides this one would be OK.
26define i64 @f3(i64 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]27; CHECK-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]28; CHECK: agfi %r2, 524288
29; CHECK: lg %r2, 0(%r2)
30; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]31 %ptr = getelementptr i64, i64 *%src, i64 65536
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]32 %val = load i64 , i64 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]33 ret i64 %val
34}
35
36; Check the high end of the negative aligned LG range.
37define i64 @f4(i64 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]38; CHECK-LABEL: f4:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]39; CHECK: lg %r2, -8(%r2)
40; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]41 %ptr = getelementptr i64, i64 *%src, i64 -1
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]42 %val = load i64 , i64 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]43 ret i64 %val
44}
45
46; Check the low end of the LG range.
47define i64 @f5(i64 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]48; CHECK-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]49; CHECK: lg %r2, -524288(%r2)
50; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]51 %ptr = getelementptr i64, i64 *%src, i64 -65536
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]52 %val = load i64 , i64 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]53 ret i64 %val
54}
55
56; Check the next doubleword down, which needs separate address logic.
57; Other sequences besides this one would be OK.
58define i64 @f6(i64 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]59; CHECK-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]60; CHECK: agfi %r2, -524296
61; CHECK: lg %r2, 0(%r2)
62; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]63 %ptr = getelementptr i64, i64 *%src, i64 -65537
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]64 %val = load i64 , i64 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]65 ret i64 %val
66}
67
68; Check that LG allows an index.
69define i64 @f7(i64 %src, i64 %index) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]70; CHECK-LABEL: f7:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]71; CHECK: lg %r2, 524287({{%r3,%r2|%r2,%r3}})
72; CHECK: br %r14
73 %add1 = add i64 %src, %index
74 %add2 = add i64 %add1, 524287
75 %ptr = inttoptr i64 %add2 to i64 *
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]76 %val = load i64 , i64 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]77 ret i64 %val
78}