blob: 4daa8d926ec7b1ee9b331dec36715fe297c7df59 [file] [log] [blame]
Simon Pilgrime0935942017-04-26 13:03:00 +00001; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
4
5define i32 @PR22970_i32(i32* nocapture readonly, i32) {
6; X86-LABEL: PR22970_i32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00007; X86: # %bb.0:
Simon Pilgrime0935942017-04-26 13:03:00 +00008; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
9; X86-NEXT: movl $4095, %ecx # imm = 0xFFF
10; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx
11; X86-NEXT: movl 32(%eax,%ecx,4), %eax
12; X86-NEXT: retl
13;
14; X64-LABEL: PR22970_i32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000015; X64: # %bb.0:
Francis Visoiu Mistriha8a83d12017-12-07 10:40:31 +000016; X64-NEXT: # kill: def %esi killed %esi def %rsi
Simon Pilgrime0935942017-04-26 13:03:00 +000017; X64-NEXT: andl $4095, %esi # imm = 0xFFF
18; X64-NEXT: movl 32(%rdi,%rsi,4), %eax
19; X64-NEXT: retq
20 %3 = and i32 %1, 4095
21 %4 = add nuw nsw i32 %3, 8
22 %5 = zext i32 %4 to i64
23 %6 = getelementptr inbounds i32, i32* %0, i64 %5
24 %7 = load i32, i32* %6, align 4
25 ret i32 %7
26}
27
28define i32 @PR22970_i64(i32* nocapture readonly, i64) {
29; X86-LABEL: PR22970_i64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000030; X86: # %bb.0:
Simon Pilgrime0935942017-04-26 13:03:00 +000031; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
32; X86-NEXT: movl $4095, %ecx # imm = 0xFFF
33; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx
34; X86-NEXT: movl 32(%eax,%ecx,4), %eax
35; X86-NEXT: retl
36;
37; X64-LABEL: PR22970_i64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000038; X64: # %bb.0:
Simon Pilgrime0935942017-04-26 13:03:00 +000039; X64-NEXT: andl $4095, %esi # imm = 0xFFF
40; X64-NEXT: movl 32(%rdi,%rsi,4), %eax
41; X64-NEXT: retq
42 %3 = and i64 %1, 4095
43 %4 = add nuw nsw i64 %3, 8
44 %5 = getelementptr inbounds i32, i32* %0, i64 %4
45 %6 = load i32, i32* %5, align 4
46 ret i32 %6
47}