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gerrit-public.fairphone.software / toolchain / llvm-project / aab3cfe023752c32da984afb281d322d631ad298 / . / llvm / test / CodeGen / ARM / atomic-64bit.ll
blob: 0477d4f40160069104fed7fb24f206032402b9c7 [file] [log] [blame]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]1; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
Joey Goulye1de9e92013-08-22 12:19:24 +0000[diff] [blame]2; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-THUMB
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]3
4define i64 @test1(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]5; CHECK-LABEL: test1:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]6; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]7; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
8; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
9; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
10; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]11; CHECK: cmp
12; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]13; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]15; CHECK-THUMB-LABEL: test1:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]16; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]17; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
18; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
19; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
20; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
21; CHECK-THUMB: cmp
22; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]23; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]24
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]25 %r = atomicrmw add i64* %ptr, i64 %val seq_cst
26 ret i64 %r
27}
28
29define i64 @test2(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]30; CHECK-LABEL: test2:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]31; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]32; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
33; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
34; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
35; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]36; CHECK: cmp
37; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]38; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]39
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]40; CHECK-THUMB-LABEL: test2:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]41; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]42; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
43; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
44; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
45; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
46; CHECK-THUMB: cmp
47; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]48; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]49
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]50 %r = atomicrmw sub i64* %ptr, i64 %val seq_cst
51 ret i64 %r
52}
53
54define i64 @test3(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]55; CHECK-LABEL: test3:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]56; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]57; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
58; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
59; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
60; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]61; CHECK: cmp
62; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]63; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]64
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]65; CHECK-THUMB-LABEL: test3:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]66; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]67; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
68; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
69; CHECK-THUMB: and.w [[REG4:[a-z0-9]+]], [[REG2]]
70; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
71; CHECK-THUMB: cmp
72; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]73; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]74
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]75 %r = atomicrmw and i64* %ptr, i64 %val seq_cst
76 ret i64 %r
77}
78
79define i64 @test4(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]80; CHECK-LABEL: test4:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]81; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]82; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
83; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
84; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
85; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]86; CHECK: cmp
87; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]88; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]89
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]90; CHECK-THUMB-LABEL: test4:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]91; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]92; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
93; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
94; CHECK-THUMB: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
95; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
96; CHECK-THUMB: cmp
97; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]98; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]99
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]100 %r = atomicrmw or i64* %ptr, i64 %val seq_cst
101 ret i64 %r
102}
103
104define i64 @test5(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]105; CHECK-LABEL: test5:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]106; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]107; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
108; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
109; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
110; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]111; CHECK: cmp
112; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]113; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]114
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]115; CHECK-THUMB-LABEL: test5:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]116; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]117; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
118; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
119; CHECK-THUMB: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
120; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
121; CHECK-THUMB: cmp
122; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]123; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]124
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]125 %r = atomicrmw xor i64* %ptr, i64 %val seq_cst
126 ret i64 %r
127}
128
129define i64 @test6(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]130; CHECK-LABEL: test6:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]131; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]132; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
133; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]134; CHECK: cmp
135; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]136; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]137
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]138; CHECK-THUMB-LABEL: test6:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]139; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]140; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
141; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
142; CHECK-THUMB: cmp
143; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]144; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]145
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]146 %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
147 ret i64 %r
Eli Friedman2c7bb522011-08-31 00:41:05 +0000[diff] [blame]148}
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]149
150define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]151; CHECK-LABEL: test7:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]152; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]153; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
154; CHECK: cmp [[REG1]]
155; CHECK: cmpeq [[REG2]]
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]156; CHECK: bne
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]157; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]158; CHECK: cmp
159; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]160; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]161
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]162; CHECK-THUMB-LABEL: test7:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]163; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]164; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
165; CHECK-THUMB: cmp [[REG1]]
166; CHECK-THUMB: it eq
167; CHECK-THUMB: cmpeq [[REG2]]
168; CHECK-THUMB: bne
169; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
170; CHECK-THUMB: cmp
171; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]172; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]173
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]174 %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
175 ret i64 %r
176}
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]177
Amara Emersonb4ad2f32013-09-26 12:22:36 +0000[diff] [blame]178; Compiles down to a single ldrexd
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]179define i64 @test8(i64* %ptr) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]180; CHECK-LABEL: test8:
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]181; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]182; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]183
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]184; CHECK-THUMB-LABEL: test8:
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]185; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]186; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]187
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]188 %r = load atomic i64* %ptr seq_cst, align 8
189 ret i64 %r
190}
191
192; Compiles down to atomicrmw xchg; there really isn't any more efficient
193; way to write it.
194define void @test9(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]195; CHECK-LABEL: test9:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]196; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]197; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
198; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]199; CHECK: cmp
200; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]201; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]202
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]203; CHECK-THUMB-LABEL: test9:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]204; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]205; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
206; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
207; CHECK-THUMB: cmp
208; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]209; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]210
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]211 store atomic i64 %val, i64* %ptr seq_cst, align 8
212 ret void
213}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]214
215define i64 @test10(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]216; CHECK-LABEL: test10:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]217; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]218; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
219; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
220; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
Silviu Baranga3eb45a02013-01-25 10:39:49 +0000[diff] [blame]221; CHECK: blt
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]222; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
223; CHECK: cmp
224; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]225; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]226
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]227; CHECK-THUMB-LABEL: test10:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]228; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]229; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
230; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
231; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
232; CHECK-THUMB: blt
233; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
234; CHECK-THUMB: cmp
235; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]236; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]237
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]238 %r = atomicrmw min i64* %ptr, i64 %val seq_cst
239 ret i64 %r
240}
241
242define i64 @test11(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]243; CHECK-LABEL: test11:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]244; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]245; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
246; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
247; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
Silviu Baranga3eb45a02013-01-25 10:39:49 +0000[diff] [blame]248; CHECK: blo
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]249; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
250; CHECK: cmp
251; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]252; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]253
254
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]255; CHECK-THUMB-LABEL: test11:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]256; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]257; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
258; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
259; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
260; CHECK-THUMB: blo
261; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
262; CHECK-THUMB: cmp
263; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]264; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]265
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]266 %r = atomicrmw umin i64* %ptr, i64 %val seq_cst
267 ret i64 %r
268}
269
270define i64 @test12(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]271; CHECK-LABEL: test12:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]272; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]273; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
274; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
275; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
276; CHECK: bge
277; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
278; CHECK: cmp
279; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]280; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]281
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]282; CHECK-THUMB-LABEL: test12:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]283; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]284; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
285; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
286; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
287; CHECK-THUMB: bge
288; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
289; CHECK-THUMB: cmp
290; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]291; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]292
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]293 %r = atomicrmw max i64* %ptr, i64 %val seq_cst
294 ret i64 %r
295}
296
297define i64 @test13(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]298; CHECK-LABEL: test13:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]299; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]300; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
301; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
302; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
303; CHECK: bhs
304; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
305; CHECK: cmp
306; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]307; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]308
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]309; CHECK-THUMB-LABEL: test13:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]310; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]311; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
312; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
313; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
314; CHECK-THUMB: bhs
315; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
316; CHECK-THUMB: cmp
317; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]318; CHECK-THUMB: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]319 %r = atomicrmw umax i64* %ptr, i64 %val seq_cst
320 ret i64 %r
321}
322