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gerrit-public.fairphone.software / toolchain / llvm-project / e94ee833f9444b629bdbbd9fd08b51a04560c1a0 / . / llvm / lib / Target / AMDGPU / AMDGPUInstructionSelector.h
blob: 68b40b20aca243747c5c6829388beeec6a9d86e8 [file] [log] [blame]
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file declares the targeting of the InstructionSelector class for
11/// AMDGPU.
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
16
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]17#include "AMDGPU.h"
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]18#include "AMDGPUArgumentUsageInfo.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]19#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/SmallVector.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]22
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]23namespace {
24#define GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]25#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]26#include "AMDGPUGenGlobalISel.inc"
27#undef GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]28#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]29}
30
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]31namespace llvm {
32
33class AMDGPUInstrInfo;
34class AMDGPURegisterBankInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]35class GCNSubtarget;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]36class MachineInstr;
37class MachineOperand;
38class MachineRegisterInfo;
39class SIInstrInfo;
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]40class SIMachineFunctionInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]41class SIRegisterInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]42
43class AMDGPUInstructionSelector : public InstructionSelector {
44public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]45 AMDGPUInstructionSelector(const GCNSubtarget &STI,
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]46 const AMDGPURegisterBankInfo &RBI,
47 const AMDGPUTargetMachine &TM);
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]48
Daniel Sandersf76f3152017-11-16 00:46:35 +0000[diff] [blame]49 bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]50 static const char *getName();
Daniel Sandersf76f3152017-11-16 00:46:35 +0000[diff] [blame]51
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]52private:
53 struct GEPInfo {
54 const MachineInstr &GEP;
55 SmallVector<unsigned, 2> SgprParts;
56 SmallVector<unsigned, 2> VgprParts;
57 int64_t Imm;
58 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
59 };
60
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]61 /// tblgen-erated 'select' implementation.
62 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
63
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]64 MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
Tom Stellard1e0edad2018-05-10 21:20:10 +0000[diff] [blame]65 bool selectCOPY(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]66 bool selectG_CONSTANT(MachineInstr &I) const;
67 bool selectG_ADD(MachineInstr &I) const;
68 bool selectG_GEP(MachineInstr &I) const;
Tom Stellard3f1c6fe2018-06-21 23:38:20 +0000[diff] [blame]69 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
Tom Stellarda9284732018-06-14 19:26:37 +0000[diff] [blame]70 bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
Tom Stellard390a5f42018-07-13 21:05:14 +0000[diff] [blame]71 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
72 CodeGenCoverage &CoverageInfo) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]73 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
74 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
75 SmallVectorImpl<GEPInfo> &AddrInfo) const;
76 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
77 bool selectG_LOAD(MachineInstr &I) const;
78 bool selectG_STORE(MachineInstr &I) const;
79
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]80 InstructionSelector::ComplexRendererFns
Tom Stellard26fac0f2018-06-22 02:54:57 +0000[diff] [blame]81 selectVCSRC(MachineOperand &Root) const;
82
83 InstructionSelector::ComplexRendererFns
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]84 selectVSRC0(MachineOperand &Root) const;
85
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]86 InstructionSelector::ComplexRendererFns
87 selectVOP3Mods0(MachineOperand &Root) const;
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]88 InstructionSelector::ComplexRendererFns
Tom Stellard9a653572018-06-22 02:34:29 +0000[diff] [blame]89 selectVOP3OMods(MachineOperand &Root) const;
90 InstructionSelector::ComplexRendererFns
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]91 selectVOP3Mods(MachineOperand &Root) const;
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]92
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]93 const SIInstrInfo &TII;
94 const SIRegisterInfo &TRI;
95 const AMDGPURegisterBankInfo &RBI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]96 const AMDGPUTargetMachine &TM;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]97 const GCNSubtarget &STI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]98 bool EnableLateStructurizeCFG;
99#define GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]100#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]101#include "AMDGPUGenGlobalISel.inc"
102#undef GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]103#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]104
105#define GET_GLOBALISEL_TEMPORARIES_DECL
106#include "AMDGPUGenGlobalISel.inc"
107#undef GET_GLOBALISEL_TEMPORARIES_DECL
108
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]109protected:
110 AMDGPUAS AMDGPUASI;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]111};
112
113} // End llvm namespace.
114#endif