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gerrit-public.fairphone.software / toolchain / llvm-project / e94ee833f9444b629bdbbd9fd08b51a04560c1a0 / . / llvm / test / CodeGen / AArch64 / arm64-anyregcc.ll
blob: 10989a07990c5aff510172ac7a206adac39aca19 [file] [log] [blame]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]1; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
2
3; Stackmap Header: no constants - 6 callsites
4; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
5; CHECK-NEXT: __LLVM_StackMaps:
6; Header
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]7; CHECK-NEXT: .byte 3
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]8; CHECK-NEXT: .byte 0
9; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]10; Num Functions
11; CHECK-NEXT: .long 8
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]12; Num LargeConstants
13; CHECK-NEXT: .long 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]14; Num Callsites
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]15; CHECK-NEXT: .long 8
16
17; Functions and stack size
18; CHECK-NEXT: .quad _test
19; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]20; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]21; CHECK-NEXT: .quad _property_access1
22; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]23; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]24; CHECK-NEXT: .quad _property_access2
25; CHECK-NEXT: .quad 32
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]26; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]27; CHECK-NEXT: .quad _property_access3
28; CHECK-NEXT: .quad 32
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]29; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]30; CHECK-NEXT: .quad _anyreg_test1
31; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]32; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]33; CHECK-NEXT: .quad _anyreg_test2
34; CHECK-NEXT: .quad 16
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]35; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]36; CHECK-NEXT: .quad _patchpoint_spilldef
37; CHECK-NEXT: .quad 112
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]38; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]39; CHECK-NEXT: .quad _patchpoint_spillargs
40; CHECK-NEXT: .quad 128
Sanjoy Das23f06e52016-09-14 20:22:03 +0000[diff] [blame]41; CHECK-NEXT: .quad 1
Juergen Ributzkae1179922014-03-31 22:14:04 +0000[diff] [blame]42
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]43
44; test
45; CHECK-LABEL: .long L{{.*}}-_test
46; CHECK-NEXT: .short 0
47; 3 locations
48; CHECK-NEXT: .short 3
49; Loc 0: Register
50; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]51; CHECK-NEXT: .byte 0
52; CHECK-NEXT: .short 4
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]53; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]54; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]55; CHECK-NEXT: .long 0
56; Loc 1: Register
57; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]58; CHECK-NEXT: .byte 0
59; CHECK-NEXT: .short 4
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]60; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]61; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]62; CHECK-NEXT: .long 0
63; Loc 2: Constant 3
64; CHECK-NEXT: .byte 4
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]65; CHECK-NEXT: .byte 0
66; CHECK-NEXT: .short 8
67; CHECK-NEXT: .short 0
68; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]69; CHECK-NEXT: .long 3
70define i64 @test() nounwind ssp uwtable {
71entry:
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]72 call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]73 ret i64 0
74}
75
76; property access 1 - %obj is an anyreg call argument and should therefore be in a register
77; CHECK-LABEL: .long L{{.*}}-_property_access1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]78; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]79; 2 locations
80; CHECK-NEXT: .short 2
81; Loc 0: Register <-- this is the return register
82; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]83; CHECK-NEXT: .byte 0
84; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]85; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]86; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]87; CHECK-NEXT: .long 0
88; Loc 1: Register
89; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]90; CHECK-NEXT: .byte 0
91; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]92; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]93; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]94; CHECK-NEXT: .long 0
95define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
96entry:
97 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]98 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]99 ret i64 %ret
100}
101
102; property access 2 - %obj is an anyreg call argument and should therefore be in a register
103; CHECK-LABEL: .long L{{.*}}-_property_access2
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]104; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]105; 2 locations
106; CHECK-NEXT: .short 2
107; Loc 0: Register <-- this is the return register
108; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]109; CHECK-NEXT: .byte 0
110; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]111; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]112; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]113; CHECK-NEXT: .long 0
114; Loc 1: Register
115; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]116; CHECK-NEXT: .byte 0
117; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]118; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]119; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]120; CHECK-NEXT: .long 0
121define i64 @property_access2() nounwind ssp uwtable {
122entry:
123 %obj = alloca i64, align 8
124 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]125 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]126 ret i64 %ret
127}
128
129; property access 3 - %obj is a frame index
130; CHECK-LABEL: .long L{{.*}}-_property_access3
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]131; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]132; 2 locations
133; CHECK-NEXT: .short 2
134; Loc 0: Register <-- this is the return register
135; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]136; CHECK-NEXT: .byte 0
137; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]138; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]139; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]140; CHECK-NEXT: .long 0
141; Loc 1: Direct FP - 8
142; CHECK-NEXT: .byte 2
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]143; CHECK-NEXT: .byte 0
144; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]145; CHECK-NEXT: .short 29
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]146; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]147; CHECK-NEXT: .long -8
148define i64 @property_access3() nounwind ssp uwtable {
149entry:
150 %obj = alloca i64, align 8
151 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]152 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]153 ret i64 %ret
154}
155
156; anyreg_test1
157; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]158; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]159; 14 locations
160; CHECK-NEXT: .short 14
161; Loc 0: Register <-- this is the return register
162; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]163; CHECK-NEXT: .byte 0
164; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]165; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]166; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]167; CHECK-NEXT: .long 0
168; Loc 1: Register
169; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]170; CHECK-NEXT: .byte 0
171; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]172; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]173; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]174; CHECK-NEXT: .long 0
175; Loc 2: Register
176; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]177; CHECK-NEXT: .byte 0
178; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]179; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]180; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]181; CHECK-NEXT: .long 0
182; Loc 3: Register
183; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]184; CHECK-NEXT: .byte 0
185; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]186; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]187; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]188; CHECK-NEXT: .long 0
189; Loc 4: Register
190; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]191; CHECK-NEXT: .byte 0
192; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]193; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]194; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]195; CHECK-NEXT: .long 0
196; Loc 5: Register
197; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]198; CHECK-NEXT: .byte 0
199; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]200; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]201; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]202; CHECK-NEXT: .long 0
203; Loc 6: Register
204; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]205; CHECK-NEXT: .byte 0
206; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]207; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]208; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]209; CHECK-NEXT: .long 0
210; Loc 7: Register
211; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]212; CHECK-NEXT: .byte 0
213; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]214; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]215; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]216; CHECK-NEXT: .long 0
217; Loc 8: Register
218; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]219; CHECK-NEXT: .byte 0
220; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]221; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]222; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]223; CHECK-NEXT: .long 0
224; Loc 9: Register
225; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]226; CHECK-NEXT: .byte 0
227; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]228; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]229; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]230; CHECK-NEXT: .long 0
231; Loc 10: Register
232; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]233; CHECK-NEXT: .byte 0
234; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]235; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]236; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]237; CHECK-NEXT: .long 0
238; Loc 11: Register
239; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]240; CHECK-NEXT: .byte 0
241; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]242; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]243; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]244; CHECK-NEXT: .long 0
245; Loc 12: Register
246; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]247; CHECK-NEXT: .byte 0
248; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]249; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]250; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]251; CHECK-NEXT: .long 0
252; Loc 13: Register
253; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]254; CHECK-NEXT: .byte 0
255; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]256; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]257; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]258; CHECK-NEXT: .long 0
259define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
260entry:
261 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]262 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]263 ret i64 %ret
264}
265
266; anyreg_test2
267; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]268; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]269; 14 locations
270; CHECK-NEXT: .short 14
271; Loc 0: Register <-- this is the return register
272; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]273; CHECK-NEXT: .byte 0
274; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]275; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]276; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]277; CHECK-NEXT: .long 0
278; Loc 1: Register
279; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]280; CHECK-NEXT: .byte 0
281; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]282; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]283; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]284; CHECK-NEXT: .long 0
285; Loc 2: Register
286; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]287; CHECK-NEXT: .byte 0
288; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]289; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]290; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]291; CHECK-NEXT: .long 0
292; Loc 3: Register
293; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]294; CHECK-NEXT: .byte 0
295; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]296; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]297; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]298; CHECK-NEXT: .long 0
299; Loc 4: Register
300; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]301; CHECK-NEXT: .byte 0
302; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]303; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]304; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]305; CHECK-NEXT: .long 0
306; Loc 5: Register
307; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]308; CHECK-NEXT: .byte 0
309; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]310; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]311; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]312; CHECK-NEXT: .long 0
313; Loc 6: Register
314; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]315; CHECK-NEXT: .byte 0
316; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]317; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]318; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]319; CHECK-NEXT: .long 0
320; Loc 7: Register
321; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]322; CHECK-NEXT: .byte 0
323; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]324; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]325; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]326; CHECK-NEXT: .long 0
327; Loc 8: Register
328; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]329; CHECK-NEXT: .byte 0
330; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]331; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]332; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]333; CHECK-NEXT: .long 0
334; Loc 9: Register
335; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]336; CHECK-NEXT: .byte 0
337; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]338; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]339; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]340; CHECK-NEXT: .long 0
341; Loc 10: Register
342; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]343; CHECK-NEXT: .byte 0
344; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]345; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]346; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]347; CHECK-NEXT: .long 0
348; Loc 11: Register
349; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]350; CHECK-NEXT: .byte 0
351; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]352; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]353; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]354; CHECK-NEXT: .long 0
355; Loc 12: Register
356; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]357; CHECK-NEXT: .byte 0
358; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]359; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]360; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]361; CHECK-NEXT: .long 0
362; Loc 13: Register
363; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]364; CHECK-NEXT: .byte 0
365; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]366; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]367; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]368; CHECK-NEXT: .long 0
369define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
370entry:
371 %f = inttoptr i64 281474417671919 to i8*
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]372 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]373 ret i64 %ret
374}
375
376; Test spilling the return value of an anyregcc call.
377;
378; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
379;
380; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
381; CHECK-NEXT: .short 0
382; CHECK-NEXT: .short 3
383; Loc 0: Register (some register that will be spilled to the stack)
384; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]385; CHECK-NEXT: .byte 0
386; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]387; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]388; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]389; CHECK-NEXT: .long 0
390; Loc 1: Register
391; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]392; CHECK-NEXT: .byte 0
393; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]394; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]395; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]396; CHECK-NEXT: .long 0
397; Loc 1: Register
398; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]399; CHECK-NEXT: .byte 0
400; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]401; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]402; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]403; CHECK-NEXT: .long 0
404define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
405entry:
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]406 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]407 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
408 ret i64 %result
409}
410
411; Test spilling the arguments of an anyregcc call.
412;
413; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
414;
415; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
416; CHECK-NEXT: .short 0
417; CHECK-NEXT: .short 5
418; Loc 0: Return a register
419; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]420; CHECK-NEXT: .byte 0
421; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]422; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]423; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]424; CHECK-NEXT: .long 0
425; Loc 1: Arg0 in a Register
426; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]427; CHECK-NEXT: .byte 0
428; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]429; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]430; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]431; CHECK-NEXT: .long 0
432; Loc 2: Arg1 in a Register
433; CHECK-NEXT: .byte 1
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]434; CHECK-NEXT: .byte 0
435; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]436; CHECK-NEXT: .short {{[0-9]+}}
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]437; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]438; CHECK-NEXT: .long 0
439; Loc 3: Arg2 spilled to FP -96
440; CHECK-NEXT: .byte 3
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]441; CHECK-NEXT: .byte 0
442; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]443; CHECK-NEXT: .short 29
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]444; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]445; CHECK-NEXT: .long -96
446; Loc 4: Arg3 spilled to FP - 88
447; CHECK-NEXT: .byte 3
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]448; CHECK-NEXT: .byte 0
449; CHECK-NEXT: .short 8
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]450; CHECK-NEXT: .short 29
Sanjoy Dasba0daee2017-04-28 04:48:42 +0000[diff] [blame]451; CHECK-NEXT: .short 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]452; CHECK-NEXT: .long -88
453define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
454entry:
455 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
David Blaikie23af6482015-04-16 23:24:18 +0000[diff] [blame]456 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]457 ret i64 %result
458}
459
460declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
461declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)