Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 4bcfcc14bdffa4a4e5dd948a746e07077ecc4a1b / . / llvm / lib / Target / PowerPC / Disassembler / PPCDisassembler.cpp
blob: d0cd49ec9b08e235efb57e47dd92bbeb2c649633 [file] [log] [blame]
Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]1//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "PPC.h"
11#include "llvm/MC/MCDisassembler.h"
12#include "llvm/MC/MCFixedLenDisassembler.h"
13#include "llvm/MC/MCInst.h"
14#include "llvm/MC/MCSubtargetInfo.h"
15#include "llvm/Support/MemoryObject.h"
16#include "llvm/Support/TargetRegistry.h"
17
18using namespace llvm;
19
20typedef MCDisassembler::DecodeStatus DecodeStatus;
21
22namespace {
23class PPCDisassembler : public MCDisassembler {
24public:
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000[diff] [blame]25 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
26 : MCDisassembler(STI, Ctx) {}
Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]27 virtual ~PPCDisassembler() {}
28
29 // Override MCDisassembler.
30 virtual DecodeStatus getInstruction(MCInst &instr,
31 uint64_t &size,
32 const MemoryObject &region,
33 uint64_t address,
34 raw_ostream &vStream,
Craig Topper73156022014-03-02 09:09:27 +0000[diff] [blame]35 raw_ostream &cStream) const override;
Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]36};
37} // end anonymous namespace
38
39static MCDisassembler *createPPCDisassembler(const Target &T,
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000[diff] [blame]40 const MCSubtargetInfo &STI,
41 MCContext &Ctx) {
42 return new PPCDisassembler(STI, Ctx);
Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]43}
44
45extern "C" void LLVMInitializePowerPCDisassembler() {
46 // Register the disassembler for each target.
47 TargetRegistry::RegisterMCDisassembler(ThePPC32Target,
48 createPPCDisassembler);
49 TargetRegistry::RegisterMCDisassembler(ThePPC64Target,
50 createPPCDisassembler);
51 TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget,
52 createPPCDisassembler);
53}
54
55// FIXME: These can be generated by TableGen from the existing register
56// encoding values!
57
58static const unsigned CRRegs[] = {
59 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
60 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
61};
62
63static const unsigned CRBITRegs[] = {
64 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
65 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
66 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
67 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
68 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
69 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
70 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
71 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
72};
73
74static const unsigned FRegs[] = {
75 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
76 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
77 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
78 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
79 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
80 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
81 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
82 PPC::F28, PPC::F29, PPC::F30, PPC::F31
83};
84
85static const unsigned VRegs[] = {
86 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
87 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
88 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
89 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
90 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
91 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
92 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
93 PPC::V28, PPC::V29, PPC::V30, PPC::V31
94};
95
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]96static const unsigned VSRegs[] = {
97 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
98 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
99 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
100 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
101 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
102 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
103 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
104 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
105
106 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
107 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
108 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
109 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
110 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
111 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
112 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
113 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
114};
115
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]116static const unsigned VSFRegs[] = {
117 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
118 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
119 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
120 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
121 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
122 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
123 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
124 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
125
126 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
127 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
128 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
129 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
130 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
131 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
132 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
133 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
134};
135
Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]136static const unsigned GPRegs[] = {
137 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
138 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
139 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
140 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
141 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
142 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
143 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
144 PPC::R28, PPC::R29, PPC::R30, PPC::R31
145};
146
147static const unsigned GP0Regs[] = {
148 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
149 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
150 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
151 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
152 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
153 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
154 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
155 PPC::R28, PPC::R29, PPC::R30, PPC::R31
156};
157
158static const unsigned G8Regs[] = {
159 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
160 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
161 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
162 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
163 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
164 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
165 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
166 PPC::X28, PPC::X29, PPC::X30, PPC::X31
167};
168
169template <std::size_t N>
170static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
171 const unsigned (&Regs)[N]) {
172 assert(RegNo < N && "Invalid register number");
173 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
174 return MCDisassembler::Success;
175}
176
177static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
178 uint64_t Address,
179 const void *Decoder) {
180 return decodeRegisterClass(Inst, RegNo, CRRegs);
181}
182
183static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
184 uint64_t Address,
185 const void *Decoder) {
186 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
187}
188
189static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
190 uint64_t Address,
191 const void *Decoder) {
192 return decodeRegisterClass(Inst, RegNo, FRegs);
193}
194
195static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
196 uint64_t Address,
197 const void *Decoder) {
198 return decodeRegisterClass(Inst, RegNo, FRegs);
199}
200
201static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
202 uint64_t Address,
203 const void *Decoder) {
204 return decodeRegisterClass(Inst, RegNo, VRegs);
205}
206
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]207static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
208 uint64_t Address,
209 const void *Decoder) {
210 return decodeRegisterClass(Inst, RegNo, VSRegs);
211}
212
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]213static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
214 uint64_t Address,
215 const void *Decoder) {
216 return decodeRegisterClass(Inst, RegNo, VSFRegs);
217}
218
Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]219static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
220 uint64_t Address,
221 const void *Decoder) {
222 return decodeRegisterClass(Inst, RegNo, GPRegs);
223}
224
225static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
226 uint64_t Address,
227 const void *Decoder) {
228 return decodeRegisterClass(Inst, RegNo, GP0Regs);
229}
230
231static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
232 uint64_t Address,
233 const void *Decoder) {
234 return decodeRegisterClass(Inst, RegNo, G8Regs);
235}
236
237#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
238#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
239
240template<unsigned N>
241static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
242 int64_t Address, const void *Decoder) {
243 assert(isUInt<N>(Imm) && "Invalid immediate");
244 Inst.addOperand(MCOperand::CreateImm(Imm));
245 return MCDisassembler::Success;
246}
247
248template<unsigned N>
249static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
250 int64_t Address, const void *Decoder) {
251 assert(isUInt<N>(Imm) && "Invalid immediate");
252 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
253 return MCDisassembler::Success;
254}
255
256static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
257 int64_t Address, const void *Decoder) {
258 // Decode the memri field (imm, reg), which has the low 16-bits as the
259 // displacement and the next 5 bits as the register #.
260
261 uint64_t Base = Imm >> 16;
262 uint64_t Disp = Imm & 0xFFFF;
263
264 assert(Base < 32 && "Invalid base register");
265
266 switch (Inst.getOpcode()) {
267 default: break;
268 case PPC::LBZU:
269 case PPC::LHAU:
270 case PPC::LHZU:
271 case PPC::LWZU:
272 case PPC::LFSU:
273 case PPC::LFDU:
274 // Add the tied output operand.
275 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
276 break;
277 case PPC::STBU:
278 case PPC::STHU:
279 case PPC::STWU:
280 case PPC::STFSU:
281 case PPC::STFDU:
282 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
283 break;
284 }
285
286 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp)));
287 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
288 return MCDisassembler::Success;
289}
290
291static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
292 int64_t Address, const void *Decoder) {
293 // Decode the memrix field (imm, reg), which has the low 14-bits as the
294 // displacement and the next 5 bits as the register #.
295
296 uint64_t Base = Imm >> 14;
297 uint64_t Disp = Imm & 0x3FFF;
298
299 assert(Base < 32 && "Invalid base register");
300
301 if (Inst.getOpcode() == PPC::LDU)
302 // Add the tied output operand.
303 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
304 else if (Inst.getOpcode() == PPC::STDU)
305 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
306
307 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
308 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
309 return MCDisassembler::Success;
310}
311
312static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
313 int64_t Address, const void *Decoder) {
314 // The cr bit encoding is 0x80 >> cr_reg_num.
315
316 unsigned Zeros = countTrailingZeros(Imm);
317 assert(Zeros < 8 && "Invalid CR bit value");
318
319 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros]));
320 return MCDisassembler::Success;
321}
322
323#include "PPCGenDisassemblerTables.inc"
324
325DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
326 const MemoryObject &Region,
327 uint64_t Address,
328 raw_ostream &os,
329 raw_ostream &cs) const {
330 // Get the four bytes of the instruction.
331 uint8_t Bytes[4];
332 Size = 4;
333 if (Region.readBytes(Address, Size, Bytes) == -1) {
334 Size = 0;
335 return MCDisassembler::Fail;
336 }
337
338 // The instruction is big-endian encoded.
339 uint32_t Inst = (Bytes[0] << 24) |
340 (Bytes[1] << 16) |
341 (Bytes[2] << 8) |
342 (Bytes[3] << 0);
343
344 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
345}
346