blob: bb85fb9f2a2a32d96b9fc573692e21a6466f2bcc [file] [log] [blame]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00001; Test sign extensions from a halfword to an i64.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Test register extension, starting with an i32.
6define i64 @f1(i64 %a) {
7; CHECK: f1:
8; CHECK: lghr %r2, %r2
Richard Sandifordec8693d2013-06-27 09:49:34 +00009; CHECK: br %r14
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000010 %half = trunc i64 %a to i16
11 %ext = sext i16 %half to i64
12 ret i64 %ext
13}
14
15; ...and again with an i64.
16define i64 @f2(i32 %a) {
17; CHECK: f2:
18; CHECK: lghr %r2, %r2
Richard Sandifordec8693d2013-06-27 09:49:34 +000019; CHECK: br %r14
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000020 %half = trunc i32 %a to i16
21 %ext = sext i16 %half to i64
22 ret i64 %ext
23}
24
25; Check LGH with no displacement.
26define i64 @f3(i16 *%src) {
27; CHECK: f3:
28; CHECK: lgh %r2, 0(%r2)
29; CHECK: br %r14
30 %half = load i16 *%src
31 %ext = sext i16 %half to i64
32 ret i64 %ext
33}
34
35; Check the high end of the LGH range.
36define i64 @f4(i16 *%src) {
37; CHECK: f4:
38; CHECK: lgh %r2, 524286(%r2)
39; CHECK: br %r14
40 %ptr = getelementptr i16 *%src, i64 262143
41 %half = load i16 *%ptr
42 %ext = sext i16 %half to i64
43 ret i64 %ext
44}
45
46; Check the next halfword up, which needs separate address logic.
47; Other sequences besides this one would be OK.
48define i64 @f5(i16 *%src) {
49; CHECK: f5:
50; CHECK: agfi %r2, 524288
51; CHECK: lgh %r2, 0(%r2)
52; CHECK: br %r14
53 %ptr = getelementptr i16 *%src, i64 262144
54 %half = load i16 *%ptr
55 %ext = sext i16 %half to i64
56 ret i64 %ext
57}
58
59; Check the high end of the negative LGH range.
60define i64 @f6(i16 *%src) {
61; CHECK: f6:
62; CHECK: lgh %r2, -2(%r2)
63; CHECK: br %r14
64 %ptr = getelementptr i16 *%src, i64 -1
65 %half = load i16 *%ptr
66 %ext = sext i16 %half to i64
67 ret i64 %ext
68}
69
70; Check the low end of the LGH range.
71define i64 @f7(i16 *%src) {
72; CHECK: f7:
73; CHECK: lgh %r2, -524288(%r2)
74; CHECK: br %r14
75 %ptr = getelementptr i16 *%src, i64 -262144
76 %half = load i16 *%ptr
77 %ext = sext i16 %half to i64
78 ret i64 %ext
79}
80
81; Check the next halfword down, which needs separate address logic.
82; Other sequences besides this one would be OK.
83define i64 @f8(i16 *%src) {
84; CHECK: f8:
85; CHECK: agfi %r2, -524290
86; CHECK: lgh %r2, 0(%r2)
87; CHECK: br %r14
88 %ptr = getelementptr i16 *%src, i64 -262145
89 %half = load i16 *%ptr
90 %ext = sext i16 %half to i64
91 ret i64 %ext
92}
93
94; Check that LGH allows an index.
95define i64 @f9(i64 %src, i64 %index) {
96; CHECK: f9:
97; CHECK: lgh %r2, 524287(%r3,%r2)
98; CHECK: br %r14
99 %add1 = add i64 %src, %index
100 %add2 = add i64 %add1, 524287
101 %ptr = inttoptr i64 %add2 to i16 *
102 %half = load i16 *%ptr
103 %ext = sext i16 %half to i64
104 ret i64 %ext
105}