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gerrit-public.fairphone.software / toolchain / llvm-project / edc71abedd4d32750f7d08751af12a873134d32b / . / llvm / lib / Target / AArch64 / Utils / AArch64BaseInfo.h
blob: 2ae6f521acdc7e4e1a6063459bb5141c3d0fdea4 [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains small standalone helper functions and enum definitions for
11// the AArch64 target useful for the compiler back-end and the MC libraries.
12// As such, it deliberately does not include references to LLVM core
13// code gen types, passes, etc..
14//
15//===----------------------------------------------------------------------===//
16
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame]17#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]19
20// FIXME: Is it easiest to fix this layering violation by moving the .inc
21// #includes from AArch64MCTargetDesc.h to here?
22#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringSwitch.h"
25#include "llvm/Support/ErrorHandling.h"
26
27namespace llvm {
28
29inline static unsigned getWRegFromXReg(unsigned Reg) {
30 switch (Reg) {
31 case AArch64::X0: return AArch64::W0;
32 case AArch64::X1: return AArch64::W1;
33 case AArch64::X2: return AArch64::W2;
34 case AArch64::X3: return AArch64::W3;
35 case AArch64::X4: return AArch64::W4;
36 case AArch64::X5: return AArch64::W5;
37 case AArch64::X6: return AArch64::W6;
38 case AArch64::X7: return AArch64::W7;
39 case AArch64::X8: return AArch64::W8;
40 case AArch64::X9: return AArch64::W9;
41 case AArch64::X10: return AArch64::W10;
42 case AArch64::X11: return AArch64::W11;
43 case AArch64::X12: return AArch64::W12;
44 case AArch64::X13: return AArch64::W13;
45 case AArch64::X14: return AArch64::W14;
46 case AArch64::X15: return AArch64::W15;
47 case AArch64::X16: return AArch64::W16;
48 case AArch64::X17: return AArch64::W17;
49 case AArch64::X18: return AArch64::W18;
50 case AArch64::X19: return AArch64::W19;
51 case AArch64::X20: return AArch64::W20;
52 case AArch64::X21: return AArch64::W21;
53 case AArch64::X22: return AArch64::W22;
54 case AArch64::X23: return AArch64::W23;
55 case AArch64::X24: return AArch64::W24;
56 case AArch64::X25: return AArch64::W25;
57 case AArch64::X26: return AArch64::W26;
58 case AArch64::X27: return AArch64::W27;
59 case AArch64::X28: return AArch64::W28;
60 case AArch64::FP: return AArch64::W29;
61 case AArch64::LR: return AArch64::W30;
62 case AArch64::SP: return AArch64::WSP;
63 case AArch64::XZR: return AArch64::WZR;
64 }
65 // For anything else, return it unchanged.
66 return Reg;
67}
68
69inline static unsigned getXRegFromWReg(unsigned Reg) {
70 switch (Reg) {
71 case AArch64::W0: return AArch64::X0;
72 case AArch64::W1: return AArch64::X1;
73 case AArch64::W2: return AArch64::X2;
74 case AArch64::W3: return AArch64::X3;
75 case AArch64::W4: return AArch64::X4;
76 case AArch64::W5: return AArch64::X5;
77 case AArch64::W6: return AArch64::X6;
78 case AArch64::W7: return AArch64::X7;
79 case AArch64::W8: return AArch64::X8;
80 case AArch64::W9: return AArch64::X9;
81 case AArch64::W10: return AArch64::X10;
82 case AArch64::W11: return AArch64::X11;
83 case AArch64::W12: return AArch64::X12;
84 case AArch64::W13: return AArch64::X13;
85 case AArch64::W14: return AArch64::X14;
86 case AArch64::W15: return AArch64::X15;
87 case AArch64::W16: return AArch64::X16;
88 case AArch64::W17: return AArch64::X17;
89 case AArch64::W18: return AArch64::X18;
90 case AArch64::W19: return AArch64::X19;
91 case AArch64::W20: return AArch64::X20;
92 case AArch64::W21: return AArch64::X21;
93 case AArch64::W22: return AArch64::X22;
94 case AArch64::W23: return AArch64::X23;
95 case AArch64::W24: return AArch64::X24;
96 case AArch64::W25: return AArch64::X25;
97 case AArch64::W26: return AArch64::X26;
98 case AArch64::W27: return AArch64::X27;
99 case AArch64::W28: return AArch64::X28;
100 case AArch64::W29: return AArch64::FP;
101 case AArch64::W30: return AArch64::LR;
102 case AArch64::WSP: return AArch64::SP;
103 case AArch64::WZR: return AArch64::XZR;
104 }
105 // For anything else, return it unchanged.
106 return Reg;
107}
108
109static inline unsigned getBRegFromDReg(unsigned Reg) {
110 switch (Reg) {
111 case AArch64::D0: return AArch64::B0;
112 case AArch64::D1: return AArch64::B1;
113 case AArch64::D2: return AArch64::B2;
114 case AArch64::D3: return AArch64::B3;
115 case AArch64::D4: return AArch64::B4;
116 case AArch64::D5: return AArch64::B5;
117 case AArch64::D6: return AArch64::B6;
118 case AArch64::D7: return AArch64::B7;
119 case AArch64::D8: return AArch64::B8;
120 case AArch64::D9: return AArch64::B9;
121 case AArch64::D10: return AArch64::B10;
122 case AArch64::D11: return AArch64::B11;
123 case AArch64::D12: return AArch64::B12;
124 case AArch64::D13: return AArch64::B13;
125 case AArch64::D14: return AArch64::B14;
126 case AArch64::D15: return AArch64::B15;
127 case AArch64::D16: return AArch64::B16;
128 case AArch64::D17: return AArch64::B17;
129 case AArch64::D18: return AArch64::B18;
130 case AArch64::D19: return AArch64::B19;
131 case AArch64::D20: return AArch64::B20;
132 case AArch64::D21: return AArch64::B21;
133 case AArch64::D22: return AArch64::B22;
134 case AArch64::D23: return AArch64::B23;
135 case AArch64::D24: return AArch64::B24;
136 case AArch64::D25: return AArch64::B25;
137 case AArch64::D26: return AArch64::B26;
138 case AArch64::D27: return AArch64::B27;
139 case AArch64::D28: return AArch64::B28;
140 case AArch64::D29: return AArch64::B29;
141 case AArch64::D30: return AArch64::B30;
142 case AArch64::D31: return AArch64::B31;
143 }
144 // For anything else, return it unchanged.
145 return Reg;
146}
147
148
149static inline unsigned getDRegFromBReg(unsigned Reg) {
150 switch (Reg) {
151 case AArch64::B0: return AArch64::D0;
152 case AArch64::B1: return AArch64::D1;
153 case AArch64::B2: return AArch64::D2;
154 case AArch64::B3: return AArch64::D3;
155 case AArch64::B4: return AArch64::D4;
156 case AArch64::B5: return AArch64::D5;
157 case AArch64::B6: return AArch64::D6;
158 case AArch64::B7: return AArch64::D7;
159 case AArch64::B8: return AArch64::D8;
160 case AArch64::B9: return AArch64::D9;
161 case AArch64::B10: return AArch64::D10;
162 case AArch64::B11: return AArch64::D11;
163 case AArch64::B12: return AArch64::D12;
164 case AArch64::B13: return AArch64::D13;
165 case AArch64::B14: return AArch64::D14;
166 case AArch64::B15: return AArch64::D15;
167 case AArch64::B16: return AArch64::D16;
168 case AArch64::B17: return AArch64::D17;
169 case AArch64::B18: return AArch64::D18;
170 case AArch64::B19: return AArch64::D19;
171 case AArch64::B20: return AArch64::D20;
172 case AArch64::B21: return AArch64::D21;
173 case AArch64::B22: return AArch64::D22;
174 case AArch64::B23: return AArch64::D23;
175 case AArch64::B24: return AArch64::D24;
176 case AArch64::B25: return AArch64::D25;
177 case AArch64::B26: return AArch64::D26;
178 case AArch64::B27: return AArch64::D27;
179 case AArch64::B28: return AArch64::D28;
180 case AArch64::B29: return AArch64::D29;
181 case AArch64::B30: return AArch64::D30;
182 case AArch64::B31: return AArch64::D31;
183 }
184 // For anything else, return it unchanged.
185 return Reg;
186}
187
188namespace AArch64CC {
189
190// The CondCodes constants map directly to the 4-bit encoding of the condition
191// field for predicated instructions.
192enum CondCode { // Meaning (integer) Meaning (floating-point)
193 EQ = 0x0, // Equal Equal
194 NE = 0x1, // Not equal Not equal, or unordered
195 HS = 0x2, // Unsigned higher or same >, ==, or unordered
196 LO = 0x3, // Unsigned lower Less than
197 MI = 0x4, // Minus, negative Less than
198 PL = 0x5, // Plus, positive or zero >, ==, or unordered
199 VS = 0x6, // Overflow Unordered
200 VC = 0x7, // No overflow Not unordered
201 HI = 0x8, // Unsigned higher Greater than, or unordered
202 LS = 0x9, // Unsigned lower or same Less than or equal
203 GE = 0xa, // Greater than or equal Greater than or equal
204 LT = 0xb, // Less than Less than, or unordered
205 GT = 0xc, // Greater than Greater than
206 LE = 0xd, // Less than or equal <, ==, or unordered
207 AL = 0xe, // Always (unconditional) Always (unconditional)
208 NV = 0xf, // Always (unconditional) Always (unconditional)
209 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
210 Invalid
211};
212
213inline static const char *getCondCodeName(CondCode Code) {
214 switch (Code) {
215 default: llvm_unreachable("Unknown condition code");
216 case EQ: return "eq";
217 case NE: return "ne";
218 case HS: return "hs";
219 case LO: return "lo";
220 case MI: return "mi";
221 case PL: return "pl";
222 case VS: return "vs";
223 case VC: return "vc";
224 case HI: return "hi";
225 case LS: return "ls";
226 case GE: return "ge";
227 case LT: return "lt";
228 case GT: return "gt";
229 case LE: return "le";
230 case AL: return "al";
231 case NV: return "nv";
232 }
233}
234
235inline static CondCode getInvertedCondCode(CondCode Code) {
Artyom Skrobov0d22e2a2014-05-29 11:34:50 +0000[diff] [blame]236 // To reverse a condition it's necessary to only invert the low bit:
237
238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]239}
240
241/// Given a condition code, return NZCV flags that would satisfy that condition.
242/// The flag bits are in the format expected by the ccmp instructions.
243/// Note that many different flag settings can satisfy a given condition code,
244/// this function just returns one of them.
245inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
246 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
247 enum { N = 8, Z = 4, C = 2, V = 1 };
248 switch (Code) {
249 default: llvm_unreachable("Unknown condition code");
250 case EQ: return Z; // Z == 1
251 case NE: return 0; // Z == 0
252 case HS: return C; // C == 1
253 case LO: return 0; // C == 0
254 case MI: return N; // N == 1
255 case PL: return 0; // N == 0
256 case VS: return V; // V == 1
257 case VC: return 0; // V == 0
258 case HI: return C; // C == 1 && Z == 0
259 case LS: return 0; // C == 0 || Z == 1
260 case GE: return 0; // N == V
261 case LT: return N; // N != V
262 case GT: return 0; // Z == 0 && N == V
263 case LE: return Z; // Z == 1 || N != V
264 }
265}
266} // end namespace AArch64CC
267
268/// Instances of this class can perform bidirectional mapping from random
269/// identifier strings to operand encodings. For example "MSR" takes a named
270/// system-register which must be encoded somehow and decoded for printing. This
271/// central location means that the information for those transformations is not
272/// duplicated and remains in sync.
273///
274/// FIXME: currently the algorithm is a completely unoptimised linear
275/// search. Obviously this could be improved, but we would probably want to work
276/// out just how often these instructions are emitted before working on it. It
277/// might even be optimal to just reorder the tables for the common instructions
278/// rather than changing the algorithm.
279struct AArch64NamedImmMapper {
280 struct Mapping {
281 const char *Name;
282 uint32_t Value;
283 };
284
285 template<int N>
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]286 AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
287 : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]288
289 StringRef toString(uint32_t Value, bool &Valid) const;
290 uint32_t fromString(StringRef Name, bool &Valid) const;
291
292 /// Many of the instructions allow an alternative assembly form consisting of
293 /// a simple immediate. Currently the only valid forms are ranges [0, N) where
294 /// N being 0 indicates no immediate syntax-form is allowed.
295 bool validImm(uint32_t Value) const;
296protected:
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]297 const Mapping *Mappings;
298 size_t NumMappings;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]299 uint32_t TooBigImm;
300};
301
302namespace AArch64AT {
303 enum ATValues {
304 Invalid = -1, // Op0 Op1 CRn CRm Op2
305 S1E1R = 0x43c0, // 01 000 0111 1000 000
306 S1E2R = 0x63c0, // 01 100 0111 1000 000
307 S1E3R = 0x73c0, // 01 110 0111 1000 000
308 S1E1W = 0x43c1, // 01 000 0111 1000 001
309 S1E2W = 0x63c1, // 01 100 0111 1000 001
310 S1E3W = 0x73c1, // 01 110 0111 1000 001
311 S1E0R = 0x43c2, // 01 000 0111 1000 010
312 S1E0W = 0x43c3, // 01 000 0111 1000 011
313 S12E1R = 0x63c4, // 01 100 0111 1000 100
314 S12E1W = 0x63c5, // 01 100 0111 1000 101
315 S12E0R = 0x63c6, // 01 100 0111 1000 110
316 S12E0W = 0x63c7 // 01 100 0111 1000 111
317 };
318
319 struct ATMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]320 const static Mapping ATMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]321
322 ATMapper();
323 };
324
325}
326namespace AArch64DB {
327 enum DBValues {
328 Invalid = -1,
329 OSHLD = 0x1,
330 OSHST = 0x2,
331 OSH = 0x3,
332 NSHLD = 0x5,
333 NSHST = 0x6,
334 NSH = 0x7,
335 ISHLD = 0x9,
336 ISHST = 0xa,
337 ISH = 0xb,
338 LD = 0xd,
339 ST = 0xe,
340 SY = 0xf
341 };
342
343 struct DBarrierMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]344 const static Mapping DBarrierMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]345
346 DBarrierMapper();
347 };
348}
349
350namespace AArch64DC {
351 enum DCValues {
352 Invalid = -1, // Op1 CRn CRm Op2
353 ZVA = 0x5ba1, // 01 011 0111 0100 001
354 IVAC = 0x43b1, // 01 000 0111 0110 001
355 ISW = 0x43b2, // 01 000 0111 0110 010
356 CVAC = 0x5bd1, // 01 011 0111 1010 001
357 CSW = 0x43d2, // 01 000 0111 1010 010
358 CVAU = 0x5bd9, // 01 011 0111 1011 001
359 CIVAC = 0x5bf1, // 01 011 0111 1110 001
360 CISW = 0x43f2 // 01 000 0111 1110 010
361 };
362
363 struct DCMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]364 const static Mapping DCMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]365
366 DCMapper();
367 };
368
369}
370
371namespace AArch64IC {
372 enum ICValues {
373 Invalid = -1, // Op1 CRn CRm Op2
374 IALLUIS = 0x0388, // 000 0111 0001 000
375 IALLU = 0x03a8, // 000 0111 0101 000
376 IVAU = 0x1ba9 // 011 0111 0101 001
377 };
378
379
380 struct ICMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]381 const static Mapping ICMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]382
383 ICMapper();
384 };
385
386 static inline bool NeedsRegister(ICValues Val) {
387 return Val == IVAU;
388 }
389}
390
391namespace AArch64ISB {
392 enum ISBValues {
393 Invalid = -1,
394 SY = 0xf
395 };
396 struct ISBMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]397 const static Mapping ISBMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]398
399 ISBMapper();
400 };
401}
402
403namespace AArch64PRFM {
404 enum PRFMValues {
405 Invalid = -1,
406 PLDL1KEEP = 0x00,
407 PLDL1STRM = 0x01,
408 PLDL2KEEP = 0x02,
409 PLDL2STRM = 0x03,
410 PLDL3KEEP = 0x04,
411 PLDL3STRM = 0x05,
412 PLIL1KEEP = 0x08,
413 PLIL1STRM = 0x09,
414 PLIL2KEEP = 0x0a,
415 PLIL2STRM = 0x0b,
416 PLIL3KEEP = 0x0c,
417 PLIL3STRM = 0x0d,
418 PSTL1KEEP = 0x10,
419 PSTL1STRM = 0x11,
420 PSTL2KEEP = 0x12,
421 PSTL2STRM = 0x13,
422 PSTL3KEEP = 0x14,
423 PSTL3STRM = 0x15
424 };
425
426 struct PRFMMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]427 const static Mapping PRFMMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]428
429 PRFMMapper();
430 };
431}
432
433namespace AArch64PState {
434 enum PStateValues {
435 Invalid = -1,
436 SPSel = 0x05,
437 DAIFSet = 0x1e,
438 DAIFClr = 0x1f
439 };
440
441 struct PStateMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]442 const static Mapping PStateMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]443
444 PStateMapper();
445 };
446
447}
448
449namespace AArch64SE {
450 enum ShiftExtSpecifiers {
451 Invalid = -1,
452 LSL,
453 MSL,
454 LSR,
455 ASR,
456 ROR,
457
458 UXTB,
459 UXTH,
460 UXTW,
461 UXTX,
462
463 SXTB,
464 SXTH,
465 SXTW,
466 SXTX
467 };
468}
469
470namespace AArch64Layout {
471 enum VectorLayout {
472 Invalid = -1,
473 VL_8B,
474 VL_4H,
475 VL_2S,
476 VL_1D,
477
478 VL_16B,
479 VL_8H,
480 VL_4S,
481 VL_2D,
482
483 // Bare layout for the 128-bit vector
484 // (only show ".b", ".h", ".s", ".d" without vector number)
485 VL_B,
486 VL_H,
487 VL_S,
488 VL_D
489 };
490}
491
492inline static const char *
493AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
494 switch (Layout) {
495 case AArch64Layout::VL_8B: return ".8b";
496 case AArch64Layout::VL_4H: return ".4h";
497 case AArch64Layout::VL_2S: return ".2s";
498 case AArch64Layout::VL_1D: return ".1d";
499 case AArch64Layout::VL_16B: return ".16b";
500 case AArch64Layout::VL_8H: return ".8h";
501 case AArch64Layout::VL_4S: return ".4s";
502 case AArch64Layout::VL_2D: return ".2d";
503 case AArch64Layout::VL_B: return ".b";
504 case AArch64Layout::VL_H: return ".h";
505 case AArch64Layout::VL_S: return ".s";
506 case AArch64Layout::VL_D: return ".d";
507 default: llvm_unreachable("Unknown Vector Layout");
508 }
509}
510
511inline static AArch64Layout::VectorLayout
512AArch64StringToVectorLayout(StringRef LayoutStr) {
513 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
514 .Case(".8b", AArch64Layout::VL_8B)
515 .Case(".4h", AArch64Layout::VL_4H)
516 .Case(".2s", AArch64Layout::VL_2S)
517 .Case(".1d", AArch64Layout::VL_1D)
518 .Case(".16b", AArch64Layout::VL_16B)
519 .Case(".8h", AArch64Layout::VL_8H)
520 .Case(".4s", AArch64Layout::VL_4S)
521 .Case(".2d", AArch64Layout::VL_2D)
522 .Case(".b", AArch64Layout::VL_B)
523 .Case(".h", AArch64Layout::VL_H)
524 .Case(".s", AArch64Layout::VL_S)
525 .Case(".d", AArch64Layout::VL_D)
526 .Default(AArch64Layout::Invalid);
527}
528
529namespace AArch64SysReg {
530 enum SysRegROValues {
531 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
532 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
533 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
534 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
535 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
536 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
537 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
538 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
539 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
540 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
541 CTR_EL0 = 0xd801, // 11 011 0000 0000 001
542 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
543 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
544 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
545 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
546 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
547 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
548 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
549 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
550 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
551 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
552 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
553 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
554 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
555 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
556 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
557 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
558 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
559 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
560 ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
561 ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
562 ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
563 ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
564 ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
565 ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
566 ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
567 ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
568 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
569 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
570 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
571 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
572 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
573 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
574 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
575 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
576 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
577 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
578 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
579
580 // Trace registers
581 TRCSTATR = 0x8818, // 10 001 0000 0011 000
582 TRCIDR8 = 0x8806, // 10 001 0000 0000 110
583 TRCIDR9 = 0x880e, // 10 001 0000 0001 110
584 TRCIDR10 = 0x8816, // 10 001 0000 0010 110
585 TRCIDR11 = 0x881e, // 10 001 0000 0011 110
586 TRCIDR12 = 0x8826, // 10 001 0000 0100 110
587 TRCIDR13 = 0x882e, // 10 001 0000 0101 110
588 TRCIDR0 = 0x8847, // 10 001 0000 1000 111
589 TRCIDR1 = 0x884f, // 10 001 0000 1001 111
590 TRCIDR2 = 0x8857, // 10 001 0000 1010 111
591 TRCIDR3 = 0x885f, // 10 001 0000 1011 111
592 TRCIDR4 = 0x8867, // 10 001 0000 1100 111
593 TRCIDR5 = 0x886f, // 10 001 0000 1101 111
594 TRCIDR6 = 0x8877, // 10 001 0000 1110 111
595 TRCIDR7 = 0x887f, // 10 001 0000 1111 111
596 TRCOSLSR = 0x888c, // 10 001 0001 0001 100
597 TRCPDSR = 0x88ac, // 10 001 0001 0101 100
598 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
599 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
600 TRCLSR = 0x8bee, // 10 001 0111 1101 110
601 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
602 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
603 TRCDEVID = 0x8b97, // 10 001 0111 0010 111
604 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
605 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
606 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
607 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
608 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
609 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
610 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
611 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
612 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
613 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
614 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
615 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
616 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
617
618 // GICv3 registers
619 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
620 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
621 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
622 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
623 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
624 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
625 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
626 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
627 };
628
629 enum SysRegWOValues {
630 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
631 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
632 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
633
634 // Trace Registers
635 TRCOSLAR = 0x8884, // 10 001 0001 0000 100
636 TRCLAR = 0x8be6, // 10 001 0111 1100 110
637
638 // GICv3 registers
639 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
640 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
641 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
642 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
643 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
644 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
645 };
646
647 enum SysRegValues {
648 Invalid = -1, // Op0 Op1 CRn CRm Op2
649 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
650 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
651 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
652 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
653 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
654 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
655 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
656 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
657 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
658 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
659 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
660 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
661 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
662 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
663 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
664 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
665 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
666 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
667 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
668 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
669 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
670 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
671 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
672 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
673 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
674 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
675 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
676 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
677 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
678 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
679 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
680 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
681 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
682 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
683 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
684 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
685 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
686 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
687 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
688 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
689 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
690 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
691 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
692 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
693 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
694 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
695 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
696 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
697 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
698 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
699 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
700 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
701 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
702 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
703 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
704 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
705 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
706 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
707 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
708 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
709 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
710 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
711 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
712 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
713 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
714 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
715 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
716 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
717 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
718 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
719 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
720 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
721 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
722 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
723 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
724 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
725 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
726 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
727 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
728 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
729 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
730 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
731 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
732 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
733 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
734 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
735 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
736 HCR_EL2 = 0xe088, // 11 100 0001 0001 000
737 SCR_EL3 = 0xf088, // 11 110 0001 0001 000
738 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
739 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
740 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
741 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
742 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
743 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
744 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
745 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
746 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
747 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
748 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
749 TCR_EL1 = 0xc102, // 11 000 0010 0000 010
750 TCR_EL2 = 0xe102, // 11 100 0010 0000 010
751 TCR_EL3 = 0xf102, // 11 110 0010 0000 010
752 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
753 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
754 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
755 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
756 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
757 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
758 ELR_EL1 = 0xc201, // 11 000 0100 0000 001
759 ELR_EL2 = 0xe201, // 11 100 0100 0000 001
760 ELR_EL3 = 0xf201, // 11 110 0100 0000 001
761 SP_EL0 = 0xc208, // 11 000 0100 0001 000
762 SP_EL1 = 0xe208, // 11 100 0100 0001 000
763 SP_EL2 = 0xf208, // 11 110 0100 0001 000
764 SPSel = 0xc210, // 11 000 0100 0010 000
765 NZCV = 0xda10, // 11 011 0100 0010 000
766 DAIF = 0xda11, // 11 011 0100 0010 001
767 CurrentEL = 0xc212, // 11 000 0100 0010 010
768 SPSR_irq = 0xe218, // 11 100 0100 0011 000
769 SPSR_abt = 0xe219, // 11 100 0100 0011 001
770 SPSR_und = 0xe21a, // 11 100 0100 0011 010
771 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
772 FPCR = 0xda20, // 11 011 0100 0100 000
773 FPSR = 0xda21, // 11 011 0100 0100 001
774 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
775 DLR_EL0 = 0xda29, // 11 011 0100 0101 001
776 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
777 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
778 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
779 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
780 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
781 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
782 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
783 ESR_EL1 = 0xc290, // 11 000 0101 0010 000
784 ESR_EL2 = 0xe290, // 11 100 0101 0010 000
785 ESR_EL3 = 0xf290, // 11 110 0101 0010 000
786 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
787 FAR_EL1 = 0xc300, // 11 000 0110 0000 000
788 FAR_EL2 = 0xe300, // 11 100 0110 0000 000
789 FAR_EL3 = 0xf300, // 11 110 0110 0000 000
790 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
791 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
792 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
793 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
794 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
795 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
796 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
797 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
798 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
799 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
800 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
801 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
802 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
803 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
804 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
805 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
806 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
807 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
808 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
809 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
810 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
811 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
812 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
813 RMR_EL1 = 0xc602, // 11 000 1100 0000 010
814 RMR_EL2 = 0xe602, // 11 100 1100 0000 010
815 RMR_EL3 = 0xf602, // 11 110 1100 0000 010
816 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
817 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
818 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
819 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
820 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
821 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
822 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
823 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
824 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
825 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
826 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
827 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
828 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
829 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
830 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
831 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
832 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
833 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
834 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
835 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
836 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
837 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
838 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
839 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
840 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
841 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
842 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
843 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
844 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
845 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
846 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
847 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
848 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
849 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
850 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
851 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
852 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
853 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
854 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
855 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
856 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
857 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
858 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
859 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
860 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
861 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
862 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
863 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
864 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
865 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
866 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
867 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
868 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
869 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
870 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
871 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
872 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
873 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
874 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
875 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
876 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
877 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
878 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
879 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
880 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
881 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
882 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
883 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
884 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
885 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
886 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
887 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
888 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
889 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
890 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
891 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
892 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
893 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
894 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
895 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
896 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
897 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
898 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
899 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
900 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
901
902 // Trace registers
903 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
904 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
905 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
906 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
907 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
908 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
909 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
910 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
911 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
912 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
913 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
914 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
915 TRCQCTLR = 0x8809, // 10 001 0000 0001 001
916 TRCVICTLR = 0x8802, // 10 001 0000 0000 010
917 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
918 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
919 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
920 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
921 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
922 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
923 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
924 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
925 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
926 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
927 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
928 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
929 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
930 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
931 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
932 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
933 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
934 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
935 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
936 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
937 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
938 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
939 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
940 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
941 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
942 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
943 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
944 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
945 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
946 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
947 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
948 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
949 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
950 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
951 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
952 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
953 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
954 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
955 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
956 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
957 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
958 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
959 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
960 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
961 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
962 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
963 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
964 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
965 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
966 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
967 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
968 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
969 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
970 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
971 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
972 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
973 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
974 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
975 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
976 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
977 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
978 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
979 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
980 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
981 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
982 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
983 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
984 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
985 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
986 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
987 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
988 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
989 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
990 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
991 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
992 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
993 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
994 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
995 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
996 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
997 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
998 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
999 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
1000 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
1001 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
1002 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
1003 TRCPDCR = 0x88a4, // 10 001 0001 0100 100
1004 TRCACVR0 = 0x8900, // 10 001 0010 0000 000
1005 TRCACVR1 = 0x8910, // 10 001 0010 0010 000
1006 TRCACVR2 = 0x8920, // 10 001 0010 0100 000
1007 TRCACVR3 = 0x8930, // 10 001 0010 0110 000
1008 TRCACVR4 = 0x8940, // 10 001 0010 1000 000
1009 TRCACVR5 = 0x8950, // 10 001 0010 1010 000
1010 TRCACVR6 = 0x8960, // 10 001 0010 1100 000
1011 TRCACVR7 = 0x8970, // 10 001 0010 1110 000
1012 TRCACVR8 = 0x8901, // 10 001 0010 0000 001
1013 TRCACVR9 = 0x8911, // 10 001 0010 0010 001
1014 TRCACVR10 = 0x8921, // 10 001 0010 0100 001
1015 TRCACVR11 = 0x8931, // 10 001 0010 0110 001
1016 TRCACVR12 = 0x8941, // 10 001 0010 1000 001
1017 TRCACVR13 = 0x8951, // 10 001 0010 1010 001
1018 TRCACVR14 = 0x8961, // 10 001 0010 1100 001
1019 TRCACVR15 = 0x8971, // 10 001 0010 1110 001
1020 TRCACATR0 = 0x8902, // 10 001 0010 0000 010
1021 TRCACATR1 = 0x8912, // 10 001 0010 0010 010
1022 TRCACATR2 = 0x8922, // 10 001 0010 0100 010
1023 TRCACATR3 = 0x8932, // 10 001 0010 0110 010
1024 TRCACATR4 = 0x8942, // 10 001 0010 1000 010
1025 TRCACATR5 = 0x8952, // 10 001 0010 1010 010
1026 TRCACATR6 = 0x8962, // 10 001 0010 1100 010
1027 TRCACATR7 = 0x8972, // 10 001 0010 1110 010
1028 TRCACATR8 = 0x8903, // 10 001 0010 0000 011
1029 TRCACATR9 = 0x8913, // 10 001 0010 0010 011
1030 TRCACATR10 = 0x8923, // 10 001 0010 0100 011
1031 TRCACATR11 = 0x8933, // 10 001 0010 0110 011
1032 TRCACATR12 = 0x8943, // 10 001 0010 1000 011
1033 TRCACATR13 = 0x8953, // 10 001 0010 1010 011
1034 TRCACATR14 = 0x8963, // 10 001 0010 1100 011
1035 TRCACATR15 = 0x8973, // 10 001 0010 1110 011
1036 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
1037 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
1038 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
1039 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
1040 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
1041 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
1042 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
1043 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
1044 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
1045 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
1046 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
1047 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
1048 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
1049 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
1050 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
1051 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
1052 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
1053 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
1054 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
1055 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
1056 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
1057 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
1058 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
1059 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
1060 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
1061 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
1062 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
1063 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
1064 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
1065 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
1066 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
1067 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
1068 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
1069 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
1070 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
1071 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
1072 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
1073 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
1074 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
1075
1076 // GICv3 registers
1077 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
1078 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
1079 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
1080 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
1081 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
1082 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
1083 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
1084 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
1085 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
1086 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
1087 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
1088 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
1089 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
1090 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
1091 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
1092 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
1093 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
1094 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
1095 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
1096 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
1097 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
1098 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
1099 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
1100 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
1101 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
1102 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
1103 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
1104 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
1105 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
1106 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
1107 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
1108 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
1109 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
1110 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
1111 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
1112 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
1113 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
1114 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
1115 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
1116 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
1117 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
1118 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
1119 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
1120 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
1121 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
1122 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
1123 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
1124 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
1125 };
1126
1127 // Cyclone specific system registers
1128 enum CycloneSysRegValues {
1129 CPM_IOACC_CTL_EL3 = 0xff90
1130 };
1131
1132 // Note that these do not inherit from AArch64NamedImmMapper. This class is
1133 // sufficiently different in its behaviour that I don't believe it's worth
1134 // burdening the common AArch64NamedImmMapper with abstractions only needed in
1135 // this one case.
1136 struct SysRegMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]1137 static const AArch64NamedImmMapper::Mapping SysRegMappings[];
1138 static const AArch64NamedImmMapper::Mapping CycloneSysRegMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1139
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]1140 const AArch64NamedImmMapper::Mapping *InstMappings;
1141 size_t NumInstMappings;
Michael Kuperstein29704e72015-03-24 12:56:59 +0000[diff] [blame]1142 uint64_t FeatureBits;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1143
Michael Kuperstein29704e72015-03-24 12:56:59 +0000[diff] [blame]1144 SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1145 uint32_t fromString(StringRef Name, bool &Valid) const;
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]1146 std::string toString(uint32_t Bits) const;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1147 };
1148
1149 struct MSRMapper : SysRegMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]1150 static const AArch64NamedImmMapper::Mapping MSRMappings[];
Michael Kuperstein29704e72015-03-24 12:56:59 +0000[diff] [blame]1151 MSRMapper(uint64_t FeatureBits);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1152 };
1153
1154 struct MRSMapper : SysRegMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]1155 static const AArch64NamedImmMapper::Mapping MRSMappings[];
Michael Kuperstein29704e72015-03-24 12:56:59 +0000[diff] [blame]1156 MRSMapper(uint64_t FeatureBits);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1157 };
1158
1159 uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
1160}
1161
1162namespace AArch64TLBI {
1163 enum TLBIValues {
1164 Invalid = -1, // Op0 Op1 CRn CRm Op2
1165 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
1166 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
1167 VMALLE1IS = 0x4418, // 01 000 1000 0011 000
1168 ALLE2IS = 0x6418, // 01 100 1000 0011 000
1169 ALLE3IS = 0x7418, // 01 110 1000 0011 000
1170 VAE1IS = 0x4419, // 01 000 1000 0011 001
1171 VAE2IS = 0x6419, // 01 100 1000 0011 001
1172 VAE3IS = 0x7419, // 01 110 1000 0011 001
1173 ASIDE1IS = 0x441a, // 01 000 1000 0011 010
1174 VAAE1IS = 0x441b, // 01 000 1000 0011 011
1175 ALLE1IS = 0x641c, // 01 100 1000 0011 100
1176 VALE1IS = 0x441d, // 01 000 1000 0011 101
1177 VALE2IS = 0x641d, // 01 100 1000 0011 101
1178 VALE3IS = 0x741d, // 01 110 1000 0011 101
1179 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
1180 VAALE1IS = 0x441f, // 01 000 1000 0011 111
1181 IPAS2E1 = 0x6421, // 01 100 1000 0100 001
1182 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
1183 VMALLE1 = 0x4438, // 01 000 1000 0111 000
1184 ALLE2 = 0x6438, // 01 100 1000 0111 000
1185 ALLE3 = 0x7438, // 01 110 1000 0111 000
1186 VAE1 = 0x4439, // 01 000 1000 0111 001
1187 VAE2 = 0x6439, // 01 100 1000 0111 001
1188 VAE3 = 0x7439, // 01 110 1000 0111 001
1189 ASIDE1 = 0x443a, // 01 000 1000 0111 010
1190 VAAE1 = 0x443b, // 01 000 1000 0111 011
1191 ALLE1 = 0x643c, // 01 100 1000 0111 100
1192 VALE1 = 0x443d, // 01 000 1000 0111 101
1193 VALE2 = 0x643d, // 01 100 1000 0111 101
1194 VALE3 = 0x743d, // 01 110 1000 0111 101
1195 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
1196 VAALE1 = 0x443f // 01 000 1000 0111 111
1197 };
1198
1199 struct TLBIMapper : AArch64NamedImmMapper {
Vladimir Sukharevedc71ab2015-03-26 17:57:39 +0000[diff] [blame^]1200 const static Mapping TLBIMappings[];
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1201
1202 TLBIMapper();
1203 };
1204
1205 static inline bool NeedsRegister(TLBIValues Val) {
1206 switch (Val) {
1207 case VMALLE1IS:
1208 case ALLE2IS:
1209 case ALLE3IS:
1210 case ALLE1IS:
1211 case VMALLS12E1IS:
1212 case VMALLE1:
1213 case ALLE2:
1214 case ALLE3:
1215 case ALLE1:
1216 case VMALLS12E1:
1217 return false;
1218 default:
1219 return true;
1220 }
1221 }
1222}
1223
1224namespace AArch64II {
1225 /// Target Operand Flag enum.
1226 enum TOF {
1227 //===------------------------------------------------------------------===//
1228 // AArch64 Specific MachineOperand flags.
1229
1230 MO_NO_FLAG,
1231
Kristof Beylsaea84612015-03-04 09:12:08 +0000[diff] [blame]1232 MO_FRAGMENT = 0xf,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1233
1234 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
1235 /// offset of the 4K page containing the symbol. This is used with the
1236 /// ADRP instruction.
1237 MO_PAGE = 1,
1238
1239 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
1240 /// that symbol within a 4K page. This offset is added to the page address
1241 /// to produce the complete address.
1242 MO_PAGEOFF = 2,
1243
1244 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
1245 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
1246 MO_G3 = 3,
1247
1248 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
1249 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
1250 MO_G2 = 4,
1251
1252 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
1253 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
1254 MO_G1 = 5,
1255
1256 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
1257 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
1258 MO_G0 = 6,
1259
Kristof Beylsaea84612015-03-04 09:12:08 +0000[diff] [blame]1260 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
1261 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
1262 /// by-12-bits instruction.
1263 MO_HI12 = 7,
1264
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1265 /// MO_GOT - This flag indicates that a symbol operand represents the
1266 /// address of the GOT entry for the symbol, rather than the address of
1267 /// the symbol itself.
Kristof Beylsaea84612015-03-04 09:12:08 +0000[diff] [blame]1268 MO_GOT = 0x10,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1269
1270 /// MO_NC - Indicates whether the linker is expected to check the symbol
1271 /// reference for overflow. For example in an ADRP/ADD pair of relocations
1272 /// the ADRP usually does check, but not the ADD.
Kristof Beylsaea84612015-03-04 09:12:08 +0000[diff] [blame]1273 MO_NC = 0x20,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1274
1275 /// MO_TLS - Indicates that the operand being accessed is some kind of
1276 /// thread-local symbol. On Darwin, only one type of thread-local access
1277 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
1278 /// referee will affect interpretation.
Kristof Beylsaea84612015-03-04 09:12:08 +0000[diff] [blame]1279 MO_TLS = 0x40,
Asiri Rathnayake369c0302014-09-10 13:54:38 +0000[diff] [blame]1280
1281 /// MO_CONSTPOOL - This flag indicates that a symbol operand represents
1282 /// the address of a constant pool entry for the symbol, rather than the
1283 /// address of the symbol itself.
Kristof Beylsaea84612015-03-04 09:12:08 +0000[diff] [blame]1284 MO_CONSTPOOL = 0x80
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1285 };
1286} // end namespace AArch64II
1287
1288} // end namespace llvm
1289
1290#endif