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gerrit-public.fairphone.software / toolchain / llvm-project / 0184206ff7e729e8de05acc96fcb5c1eb84291e9 / . / llvm / test / CodeGen / AArch64 / directcond.ll
blob: 0ddc59c5cac31dd41cb7b77c08c650dc555dba91 [file] [log] [blame]
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
Tim Northoverdb2860f42014-04-14 13:18:48 +0000[diff] [blame]2; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]3; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
Kevin Qin022d3952014-04-25 09:44:20 +0000[diff] [blame]4; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]5
6define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]7; CHECK-LABEL: test_select_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]8 %val = select i1 %bit, i32 %a, i32 %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]9; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
10; CHECK-AARCH64: tst w0, [[ONE]]
11; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]12; CHECK-NEXT: csel w0, w1, w2, ne
13
14 ret i32 %val
15}
16
17define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]18; CHECK-LABEL: test_select_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]19 %val = select i1 %bit, i64 %a, i64 %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]20; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
21; CHECK-AARCH64: tst w0, [[ONE]]
22; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]23; CHECK-NEXT: csel x0, x1, x2, ne
24
25 ret i64 %val
26}
27
28define float @test_select_float(i1 %bit, float %a, float %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]29; CHECK-LABEL: test_select_float:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]30 %val = select i1 %bit, float %a, float %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]31; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
32; CHECK-AARCH64: tst w0, [[ONE]]
33; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]34; CHECK-NEXT: fcsel s0, s0, s1, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]35; CHECK-NOFP-NOT: fcsel
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]36 ret float %val
37}
38
39define double @test_select_double(i1 %bit, double %a, double %b) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]40; CHECK-LABEL: test_select_double:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]41 %val = select i1 %bit, double %a, double %b
Tim Northoverb6abe802014-04-14 12:51:06 +0000[diff] [blame]42; CHECK-AARCH64: movz [[ONE:w[0-9]+]], #1
43; CHECK-AARCH64: tst w0, [[ONE]]
44; CHECK-ARM64: tst w0, #0x1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]45; CHECK-NEXT: fcsel d0, d0, d1, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]46; CHECK-NOFP-NOT: fcsel
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]47
48 ret double %val
49}
50
51define i32 @test_brcond(i1 %bit) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]52; CHECK-LABEL: test_brcond:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]53 br i1 %bit, label %true, label %false
Tim Northoverdb2860f42014-04-14 13:18:48 +0000[diff] [blame]54; CHECK: tbz {{w[0-9]+}}, #0, {{.?LBB}}
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]55
56true:
57 ret i32 0
58false:
59 ret i32 42
60}
61
62define i1 @test_setcc_float(float %lhs, float %rhs) {
63; CHECK: test_setcc_float
64 %val = fcmp oeq float %lhs, %rhs
65; CHECK: fcmp s0, s1
66; CHECK: csinc w0, wzr, wzr, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]67; CHECK-NOFP-NOT: fcmp
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]68 ret i1 %val
69}
70
71define i1 @test_setcc_double(double %lhs, double %rhs) {
72; CHECK: test_setcc_double
73 %val = fcmp oeq double %lhs, %rhs
74; CHECK: fcmp d0, d1
75; CHECK: csinc w0, wzr, wzr, ne
Amara Emersonf80f95f2013-10-31 09:32:11 +0000[diff] [blame]76; CHECK-NOFP-NOT: fcmp
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]77 ret i1 %val
78}
79
80define i1 @test_setcc_i32(i32 %lhs, i32 %rhs) {
81; CHECK: test_setcc_i32
82 %val = icmp ugt i32 %lhs, %rhs
83; CHECK: cmp w0, w1
84; CHECK: csinc w0, wzr, wzr, ls
85 ret i1 %val
86}
87
88define i1 @test_setcc_i64(i64 %lhs, i64 %rhs) {
89; CHECK: test_setcc_i64
90 %val = icmp ne i64 %lhs, %rhs
91; CHECK: cmp x0, x1
92; CHECK: csinc w0, wzr, wzr, eq
93 ret i1 %val
94}