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Alkis Evlogimenos725021c2003-12-18 13:06:04 +00001//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenos725021c2003-12-18 13:06:04 +00007//
8//===----------------------------------------------------------------------===//
9//
Alkis Evlogimenos5e0e6712004-01-04 23:09:24 +000010// This file implements the TwoAddress instruction pass which is used
11// by most register allocators. Two-Address instructions are rewritten
12// from:
13//
14// A = B op C
15//
16// to:
17//
18// A = B
Alkis Evlogimenos32742642004-02-04 22:17:40 +000019// A op= C
Alkis Evlogimenos725021c2003-12-18 13:06:04 +000020//
Alkis Evlogimenos32742642004-02-04 22:17:40 +000021// Note that if a register allocator chooses to use this pass, that it
22// has to be capable of handling the non-SSA nature of these rewritten
23// virtual registers.
24//
25// It is also worth noting that the duplicate operand of the two
26// address instruction is removed.
Chris Lattnerd835aa62004-01-31 21:07:15 +000027//
Alkis Evlogimenos725021c2003-12-18 13:06:04 +000028//===----------------------------------------------------------------------===//
29
Chandler Carruthed0881b2012-12-03 16:50:05 +000030#include "llvm/ADT/DenseMap.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/Analysis/AliasAnalysis.h"
Jakob Stoklund Olesen24bc5142012-08-03 22:58:34 +000035#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Alkis Evlogimenos725021c2003-12-18 13:06:04 +000036#include "llvm/CodeGen/LiveVariables.h"
Alkis Evlogimenos725021c2003-12-18 13:06:04 +000037#include "llvm/CodeGen/MachineFunctionPass.h"
38#include "llvm/CodeGen/MachineInstr.h"
Bob Wilsona55b8872010-06-15 05:56:31 +000039#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +000040#include "llvm/CodeGen/MachineRegisterInfo.h"
Mehdi Aminib550cb12016-04-18 09:17:29 +000041#include "llvm/CodeGen/Passes.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000042#include "llvm/IR/Function.h"
Evan Cheng30f44ad2011-11-14 19:48:55 +000043#include "llvm/MC/MCInstrItineraries.h"
Andrew Trick608a6982013-04-24 15:54:39 +000044#include "llvm/Support/CommandLine.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000045#include "llvm/Support/Debug.h"
46#include "llvm/Support/ErrorHandling.h"
Benjamin Kramer799003b2015-03-23 19:32:43 +000047#include "llvm/Support/raw_ostream.h"
Alkis Evlogimenos725021c2003-12-18 13:06:04 +000048#include "llvm/Target/TargetInstrInfo.h"
49#include "llvm/Target/TargetMachine.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000050#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +000051#include "llvm/Target/TargetSubtargetInfo.h"
Eugene Zelenkoecefe5a2016-02-02 18:20:45 +000052
Alkis Evlogimenos725021c2003-12-18 13:06:04 +000053using namespace llvm;
54
Chandler Carruth1b9dde02014-04-22 02:02:50 +000055#define DEBUG_TYPE "twoaddrinstr"
56
Chris Lattneraee775a2006-12-19 22:41:21 +000057STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
58STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
Evan Chengabda6652009-01-25 03:53:59 +000059STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
Chris Lattneraee775a2006-12-19 22:41:21 +000060STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
Evan Cheng5c26bde2008-03-13 06:37:55 +000061STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
Evan Cheng30f44ad2011-11-14 19:48:55 +000062STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
63STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
Evan Cheng5c26bde2008-03-13 06:37:55 +000064
Andrew Trick608a6982013-04-24 15:54:39 +000065// Temporary flag to disable rescheduling.
66static cl::opt<bool>
67EnableRescheduling("twoaddr-reschedule",
Evan Chengf85a76f2013-05-02 02:07:32 +000068 cl::desc("Coalesce copies by rescheduling (default=true)"),
69 cl::init(true), cl::Hidden);
Andrew Trick608a6982013-04-24 15:54:39 +000070
Evan Cheng5c26bde2008-03-13 06:37:55 +000071namespace {
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +000072class TwoAddressInstructionPass : public MachineFunctionPass {
73 MachineFunction *MF;
74 const TargetInstrInfo *TII;
75 const TargetRegisterInfo *TRI;
76 const InstrItineraryData *InstrItins;
77 MachineRegisterInfo *MRI;
78 LiveVariables *LV;
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +000079 LiveIntervals *LIS;
80 AliasAnalysis *AA;
81 CodeGenOpt::Level OptLevel;
Evan Cheng5c26bde2008-03-13 06:37:55 +000082
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +000083 // The current basic block being processed.
84 MachineBasicBlock *MBB;
85
Sanjay Patelb53791e2015-12-01 19:32:35 +000086 // Keep track the distance of a MI from the start of the current basic block.
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +000087 DenseMap<MachineInstr*, unsigned> DistanceMap;
Evan Chengc2f95b52009-03-01 02:03:43 +000088
Jakob Stoklund Olesend788e322012-10-26 22:06:00 +000089 // Set of already processed instructions in the current block.
90 SmallPtrSet<MachineInstr*, 8> Processed;
91
Sanjay Patelb53791e2015-12-01 19:32:35 +000092 // A map from virtual registers to physical registers which are likely targets
93 // to be coalesced to due to copies from physical registers to virtual
94 // registers. e.g. v1024 = move r0.
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +000095 DenseMap<unsigned, unsigned> SrcRegMap;
Evan Chengc2f95b52009-03-01 02:03:43 +000096
Sanjay Patelb53791e2015-12-01 19:32:35 +000097 // A map from virtual registers to physical registers which are likely targets
98 // to be coalesced to due to copies to physical registers from virtual
99 // registers. e.g. r1 = move v1024.
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000100 DenseMap<unsigned, unsigned> DstRegMap;
Evan Chengc2f95b52009-03-01 02:03:43 +0000101
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000102 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000103 MachineBasicBlock::iterator OldPos);
Evan Chengc5618eb2008-06-18 07:49:14 +0000104
Eric Christopher28919132015-03-03 22:03:03 +0000105 bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
106
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000107 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
Evan Chengabda6652009-01-25 03:53:59 +0000108
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000109 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000110 MachineInstr *MI, unsigned Dist);
Evan Chengabda6652009-01-25 03:53:59 +0000111
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000112 bool commuteInstruction(MachineInstr *MI,
113 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
Evan Chengc2f95b52009-03-01 02:03:43 +0000114
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000115 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
Evan Cheng09f5be82009-03-30 21:34:07 +0000116
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000117 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
118 MachineBasicBlock::iterator &nmi,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000119 unsigned RegA, unsigned RegB, unsigned Dist);
Evan Cheng09f5be82009-03-30 21:34:07 +0000120
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000121 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
Evan Cheng30f44ad2011-11-14 19:48:55 +0000122
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000123 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000124 MachineBasicBlock::iterator &nmi,
125 unsigned Reg);
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000126 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000127 MachineBasicBlock::iterator &nmi,
128 unsigned Reg);
129
130 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
Evan Cheng30f44ad2011-11-14 19:48:55 +0000131 MachineBasicBlock::iterator &nmi,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000132 unsigned SrcIdx, unsigned DstIdx,
Cameron Zwarichf05c0cb2013-02-24 00:27:26 +0000133 unsigned Dist, bool shouldOnlyCommute);
Evan Cheng30f44ad2011-11-14 19:48:55 +0000134
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000135 bool tryInstructionCommute(MachineInstr *MI,
136 unsigned DstOpIdx,
137 unsigned BaseOpIdx,
138 bool BaseOpKilled,
139 unsigned Dist);
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000140 void scanUses(unsigned DstReg);
Evan Cheng15fed7a2011-03-02 01:08:17 +0000141
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000142 void processCopy(MachineInstr *MI);
Bob Wilson5c7d9ca2009-09-03 20:58:42 +0000143
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000144 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
145 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
146 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
147 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
Jakob Stoklund Olesenda2b6b32012-12-01 01:06:44 +0000148 void eliminateRegSequence(MachineBasicBlock::iterator&);
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +0000149
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000150public:
151 static char ID; // Pass identification, replacement for typeid
152 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
153 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
154 }
Evan Cheng1e4f5522010-05-17 23:24:12 +0000155
Craig Topper4584cd52014-03-07 09:26:03 +0000156 void getAnalysisUsage(AnalysisUsage &AU) const override {
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000157 AU.setPreservesCFG();
Chandler Carruth7b560d42015-09-09 17:55:00 +0000158 AU.addRequired<AAResultsWrapperPass>();
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000159 AU.addPreserved<LiveVariables>();
160 AU.addPreserved<SlotIndexes>();
161 AU.addPreserved<LiveIntervals>();
162 AU.addPreservedID(MachineLoopInfoID);
163 AU.addPreservedID(MachineDominatorsID);
164 MachineFunctionPass::getAnalysisUsage(AU);
165 }
Devang Patel09f162c2007-05-01 21:15:47 +0000166
Sanjay Patelb53791e2015-12-01 19:32:35 +0000167 /// Pass entry point.
Craig Topper4584cd52014-03-07 09:26:03 +0000168 bool runOnMachineFunction(MachineFunction&) override;
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000169};
170} // end anonymous namespace
Alkis Evlogimenos725021c2003-12-18 13:06:04 +0000171
Dan Gohmand78c4002008-05-13 00:00:25 +0000172char TwoAddressInstructionPass::ID = 0;
Owen Anderson8ac477f2010-10-12 19:48:12 +0000173INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
174 "Two-Address instruction pass", false, false)
Chandler Carruth7b560d42015-09-09 17:55:00 +0000175INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
Owen Anderson8ac477f2010-10-12 19:48:12 +0000176INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
Owen Andersondf7a4f22010-10-07 22:25:06 +0000177 "Two-Address instruction pass", false, false)
Dan Gohmand78c4002008-05-13 00:00:25 +0000178
Owen Andersona7aed182010-08-06 18:33:48 +0000179char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
Alkis Evlogimenos71390902003-12-18 22:40:24 +0000180
Cameron Zwarich35c30502013-02-23 04:49:20 +0000181static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
182
Sanjay Patelb53791e2015-12-01 19:32:35 +0000183/// A two-address instruction has been converted to a three-address instruction
184/// to avoid clobbering a register. Try to sink it past the instruction that
185/// would kill the above mentioned register to reduce register pressure.
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000186bool TwoAddressInstructionPass::
187sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
188 MachineBasicBlock::iterator OldPos) {
Eli Friedman8a15a5a2011-09-23 22:41:57 +0000189 // FIXME: Shouldn't we be trying to do this before we three-addressify the
190 // instruction? After this transformation is done, we no longer need
191 // the instruction to be in three-address form.
192
Evan Cheng5c26bde2008-03-13 06:37:55 +0000193 // Check if it's safe to move this instruction.
194 bool SeenStore = true; // Be conservative.
Matthias Braun07066cc2015-05-19 21:22:20 +0000195 if (!MI->isSafeToMove(AA, SeenStore))
Evan Cheng5c26bde2008-03-13 06:37:55 +0000196 return false;
197
198 unsigned DefReg = 0;
199 SmallSet<unsigned, 4> UseRegs;
Bill Wendling19e3c852008-05-10 00:12:52 +0000200
Craig Topperda5168b2015-10-08 06:06:42 +0000201 for (const MachineOperand &MO : MI->operands()) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000202 if (!MO.isReg())
Evan Cheng5c26bde2008-03-13 06:37:55 +0000203 continue;
204 unsigned MOReg = MO.getReg();
205 if (!MOReg)
206 continue;
207 if (MO.isUse() && MOReg != SavedReg)
208 UseRegs.insert(MO.getReg());
209 if (!MO.isDef())
210 continue;
211 if (MO.isImplicit())
212 // Don't try to move it if it implicitly defines a register.
213 return false;
214 if (DefReg)
215 // For now, don't move any instructions that define multiple registers.
216 return false;
217 DefReg = MO.getReg();
218 }
219
220 // Find the instruction that kills SavedReg.
Craig Topperc0196b12014-04-14 00:51:57 +0000221 MachineInstr *KillMI = nullptr;
Cameron Zwarich35c30502013-02-23 04:49:20 +0000222 if (LIS) {
223 LiveInterval &LI = LIS->getInterval(SavedReg);
224 assert(LI.end() != LI.begin() &&
225 "Reg should not have empty live interval.");
226
227 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
228 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
229 if (I != LI.end() && I->start < MBBEndIdx)
230 return false;
231
232 --I;
233 KillMI = LIS->getInstructionFromIndex(I->end);
234 }
235 if (!KillMI) {
Craig Topperda5168b2015-10-08 06:06:42 +0000236 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SavedReg)) {
Cameron Zwarich35c30502013-02-23 04:49:20 +0000237 if (!UseMO.isKill())
238 continue;
239 KillMI = UseMO.getParent();
240 break;
241 }
Evan Cheng5c26bde2008-03-13 06:37:55 +0000242 }
Bill Wendling19e3c852008-05-10 00:12:52 +0000243
Eli Friedman8a15a5a2011-09-23 22:41:57 +0000244 // If we find the instruction that kills SavedReg, and it is in an
245 // appropriate location, we can try to sink the current instruction
246 // past it.
247 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
Jakob Stoklund Olesen420798c2012-08-09 22:08:26 +0000248 KillMI == OldPos || KillMI->isTerminator())
Evan Cheng5c26bde2008-03-13 06:37:55 +0000249 return false;
250
Bill Wendling19e3c852008-05-10 00:12:52 +0000251 // If any of the definitions are used by another instruction between the
252 // position and the kill use, then it's not safe to sink it.
Andrew Trick808a7a62012-02-03 05:12:30 +0000253 //
Bill Wendling19e3c852008-05-10 00:12:52 +0000254 // FIXME: This can be sped up if there is an easy way to query whether an
Evan Chengc5618eb2008-06-18 07:49:14 +0000255 // instruction is before or after another instruction. Then we can use
Bill Wendling19e3c852008-05-10 00:12:52 +0000256 // MachineRegisterInfo def / use instead.
Craig Topperc0196b12014-04-14 00:51:57 +0000257 MachineOperand *KillMO = nullptr;
Evan Cheng5c26bde2008-03-13 06:37:55 +0000258 MachineBasicBlock::iterator KillPos = KillMI;
259 ++KillPos;
Bill Wendling19e3c852008-05-10 00:12:52 +0000260
Evan Chengc5618eb2008-06-18 07:49:14 +0000261 unsigned NumVisited = 0;
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000262 for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) {
Evan Cheng5c26bde2008-03-13 06:37:55 +0000263 MachineInstr *OtherMI = I;
Dale Johannesen12565de2010-02-11 18:22:31 +0000264 // DBG_VALUE cannot be counted against the limit.
265 if (OtherMI->isDebugValue())
266 continue;
Evan Chengc5618eb2008-06-18 07:49:14 +0000267 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
268 return false;
269 ++NumVisited;
Evan Cheng5c26bde2008-03-13 06:37:55 +0000270 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
271 MachineOperand &MO = OtherMI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000272 if (!MO.isReg())
Evan Cheng5c26bde2008-03-13 06:37:55 +0000273 continue;
274 unsigned MOReg = MO.getReg();
275 if (!MOReg)
276 continue;
277 if (DefReg == MOReg)
278 return false;
Bill Wendling19e3c852008-05-10 00:12:52 +0000279
Cameron Zwarich35c30502013-02-23 04:49:20 +0000280 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
Evan Cheng5c26bde2008-03-13 06:37:55 +0000281 if (OtherMI == KillMI && MOReg == SavedReg)
Evan Chengc5618eb2008-06-18 07:49:14 +0000282 // Save the operand that kills the register. We want to unset the kill
283 // marker if we can sink MI past it.
Evan Cheng5c26bde2008-03-13 06:37:55 +0000284 KillMO = &MO;
285 else if (UseRegs.count(MOReg))
286 // One of the uses is killed before the destination.
287 return false;
288 }
289 }
290 }
Jakob Stoklund Olesen420798c2012-08-09 22:08:26 +0000291 assert(KillMO && "Didn't find kill");
Evan Cheng5c26bde2008-03-13 06:37:55 +0000292
Cameron Zwarich35c30502013-02-23 04:49:20 +0000293 if (!LIS) {
294 // Update kill and LV information.
295 KillMO->setIsKill(false);
296 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
297 KillMO->setIsKill(true);
Andrew Trick808a7a62012-02-03 05:12:30 +0000298
Cameron Zwarich35c30502013-02-23 04:49:20 +0000299 if (LV)
300 LV->replaceKillInstruction(SavedReg, KillMI, MI);
301 }
Evan Cheng5c26bde2008-03-13 06:37:55 +0000302
303 // Move instruction to its destination.
304 MBB->remove(MI);
305 MBB->insert(KillPos, MI);
306
Jakob Stoklund Olesen24bc5142012-08-03 22:58:34 +0000307 if (LIS)
Duncan P. N. Exon Smithbe8f8c42016-02-27 20:14:29 +0000308 LIS->handleMove(*MI);
Jakob Stoklund Olesen24bc5142012-08-03 22:58:34 +0000309
Evan Cheng5c26bde2008-03-13 06:37:55 +0000310 ++Num3AddrSunk;
311 return true;
312}
313
Sanjay Patelb53791e2015-12-01 19:32:35 +0000314/// Return the MachineInstr* if it is the single def of the Reg in current BB.
Eric Christopher28919132015-03-03 22:03:03 +0000315static MachineInstr *getSingleDef(unsigned Reg, MachineBasicBlock *BB,
316 const MachineRegisterInfo *MRI) {
317 MachineInstr *Ret = nullptr;
318 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
319 if (DefMI.getParent() != BB || DefMI.isDebugValue())
320 continue;
321 if (!Ret)
322 Ret = &DefMI;
323 else if (Ret != &DefMI)
324 return nullptr;
325 }
326 return Ret;
327}
328
329/// Check if there is a reversed copy chain from FromReg to ToReg:
330/// %Tmp1 = copy %Tmp2;
331/// %FromReg = copy %Tmp1;
332/// %ToReg = add %FromReg ...
333/// %Tmp2 = copy %ToReg;
334/// MaxLen specifies the maximum length of the copy chain the func
335/// can walk through.
336bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
337 int Maxlen) {
338 unsigned TmpReg = FromReg;
339 for (int i = 0; i < Maxlen; i++) {
340 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
341 if (!Def || !Def->isCopy())
342 return false;
343
344 TmpReg = Def->getOperand(1).getReg();
345
346 if (TmpReg == ToReg)
347 return true;
348 }
349 return false;
350}
351
Sanjay Patelb53791e2015-12-01 19:32:35 +0000352/// Return true if there are no intervening uses between the last instruction
353/// in the MBB that defines the specified register and the two-address
354/// instruction which is being processed. It also returns the last def location
355/// by reference.
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000356bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000357 unsigned &LastDef) {
Evan Chengabda6652009-01-25 03:53:59 +0000358 LastDef = 0;
359 unsigned LastUse = Dist;
Owen Andersonb36376e2014-03-17 19:36:09 +0000360 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
Evan Chengabda6652009-01-25 03:53:59 +0000361 MachineInstr *MI = MO.getParent();
Chris Lattnerb06015a2010-02-09 19:54:29 +0000362 if (MI->getParent() != MBB || MI->isDebugValue())
Dale Johannesenc3adf442010-02-09 02:01:46 +0000363 continue;
Evan Chengabda6652009-01-25 03:53:59 +0000364 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
365 if (DI == DistanceMap.end())
366 continue;
367 if (MO.isUse() && DI->second < LastUse)
368 LastUse = DI->second;
369 if (MO.isDef() && DI->second > LastDef)
370 LastDef = DI->second;
371 }
372
373 return !(LastUse > LastDef && LastUse < Dist);
374}
375
Sanjay Patelb53791e2015-12-01 19:32:35 +0000376/// Return true if the specified MI is a copy instruction or an extract_subreg
377/// instruction. It also returns the source and destination registers and
378/// whether they are physical registers by reference.
Evan Chengc2f95b52009-03-01 02:03:43 +0000379static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
380 unsigned &SrcReg, unsigned &DstReg,
381 bool &IsSrcPhys, bool &IsDstPhys) {
382 SrcReg = 0;
383 DstReg = 0;
Jakob Stoklund Olesen37c42a32010-07-16 04:45:42 +0000384 if (MI.isCopy()) {
385 DstReg = MI.getOperand(0).getReg();
386 SrcReg = MI.getOperand(1).getReg();
387 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
388 DstReg = MI.getOperand(0).getReg();
389 SrcReg = MI.getOperand(2).getReg();
390 } else
391 return false;
Evan Chengc2f95b52009-03-01 02:03:43 +0000392
Jakob Stoklund Olesen37c42a32010-07-16 04:45:42 +0000393 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
394 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
395 return true;
Evan Chengc2f95b52009-03-01 02:03:43 +0000396}
397
Sanjay Patelb53791e2015-12-01 19:32:35 +0000398/// Test if the given register value, which is used by the
399/// given instruction, is killed by the given instruction.
Cameron Zwarichc8964782013-02-21 07:02:28 +0000400static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
401 LiveIntervals *LIS) {
402 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
Duncan P. N. Exon Smith3ac9cc62016-02-27 06:40:41 +0000403 !LIS->isNotInMIMap(*MI)) {
Cameron Zwarichc8964782013-02-21 07:02:28 +0000404 // FIXME: Sometimes tryInstructionTransform() will add instructions and
405 // test whether they can be folded before keeping them. In this case it
406 // sets a kill before recursively calling tryInstructionTransform() again.
407 // If there is no interval available, we assume that this instruction is
408 // one of those. A kill flag is manually inserted on the operand so the
409 // check below will handle it.
410 LiveInterval &LI = LIS->getInterval(Reg);
411 // This is to match the kill flag version where undefs don't have kill
412 // flags.
413 if (!LI.hasAtLeastOneValue())
414 return false;
415
Duncan P. N. Exon Smith3ac9cc62016-02-27 06:40:41 +0000416 SlotIndex useIdx = LIS->getInstructionIndex(*MI);
Cameron Zwarichc8964782013-02-21 07:02:28 +0000417 LiveInterval::const_iterator I = LI.find(useIdx);
418 assert(I != LI.end() && "Reg must be live-in to use.");
Cameron Zwarich4e80d9e2013-02-23 04:49:22 +0000419 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
Cameron Zwarichc8964782013-02-21 07:02:28 +0000420 }
421
422 return MI->killsRegister(Reg);
423}
424
Sanjay Patelb53791e2015-12-01 19:32:35 +0000425/// Test if the given register value, which is used by the given
Dan Gohmanad3e5492009-04-08 00:15:30 +0000426/// instruction, is killed by the given instruction. This looks through
427/// coalescable copies to see if the original value is potentially not killed.
428///
429/// For example, in this code:
430///
431/// %reg1034 = copy %reg1024
432/// %reg1035 = copy %reg1025<kill>
433/// %reg1036 = add %reg1034<kill>, %reg1035<kill>
434///
435/// %reg1034 is not considered to be killed, since it is copied from a
436/// register which is not killed. Treating it as not killed lets the
437/// normal heuristics commute the (two-address) add, which lets
438/// coalescing eliminate the extra copy.
439///
Cameron Zwarich384026b2013-02-21 22:58:42 +0000440/// If allowFalsePositives is true then likely kills are treated as kills even
441/// if it can't be proven that they are kills.
Dan Gohmanad3e5492009-04-08 00:15:30 +0000442static bool isKilled(MachineInstr &MI, unsigned Reg,
443 const MachineRegisterInfo *MRI,
Cameron Zwarich94b204b2013-02-21 04:33:02 +0000444 const TargetInstrInfo *TII,
Cameron Zwarich384026b2013-02-21 22:58:42 +0000445 LiveIntervals *LIS,
446 bool allowFalsePositives) {
Dan Gohmanad3e5492009-04-08 00:15:30 +0000447 MachineInstr *DefMI = &MI;
448 for (;;) {
Cameron Zwarich384026b2013-02-21 22:58:42 +0000449 // All uses of physical registers are likely to be kills.
450 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
451 (allowFalsePositives || MRI->hasOneUse(Reg)))
452 return true;
Cameron Zwarichc8964782013-02-21 07:02:28 +0000453 if (!isPlainlyKilled(DefMI, Reg, LIS))
Dan Gohmanad3e5492009-04-08 00:15:30 +0000454 return false;
455 if (TargetRegisterInfo::isPhysicalRegister(Reg))
456 return true;
457 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
458 // If there are multiple defs, we can't do a simple analysis, so just
459 // go with what the kill flag says.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000460 if (std::next(Begin) != MRI->def_end())
Dan Gohmanad3e5492009-04-08 00:15:30 +0000461 return true;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000462 DefMI = Begin->getParent();
Dan Gohmanad3e5492009-04-08 00:15:30 +0000463 bool IsSrcPhys, IsDstPhys;
464 unsigned SrcReg, DstReg;
465 // If the def is something other than a copy, then it isn't going to
466 // be coalesced, so follow the kill flag.
467 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
468 return true;
469 Reg = SrcReg;
470 }
471}
472
Sanjay Patelb53791e2015-12-01 19:32:35 +0000473/// Return true if the specified MI uses the specified register as a two-address
474/// use. If so, return the destination register by reference.
Evan Chengc2f95b52009-03-01 02:03:43 +0000475static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
Evan Chengf85a76f2013-05-02 02:07:32 +0000476 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
Evan Chengc2f95b52009-03-01 02:03:43 +0000477 const MachineOperand &MO = MI.getOperand(i);
478 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
479 continue;
Evan Cheng1361cbb2009-03-19 20:30:06 +0000480 unsigned ti;
481 if (MI.isRegTiedToDefOperand(i, &ti)) {
Evan Chengc2f95b52009-03-01 02:03:43 +0000482 DstReg = MI.getOperand(ti).getReg();
483 return true;
484 }
485 }
486 return false;
487}
488
Sanjay Patelb53791e2015-12-01 19:32:35 +0000489/// Given a register, if has a single in-basic block use, return the use
490/// instruction if it's a copy or a two-address use.
Evan Chengc2f95b52009-03-01 02:03:43 +0000491static
492MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
493 MachineRegisterInfo *MRI,
494 const TargetInstrInfo *TII,
Evan Cheng97871832009-04-14 00:32:25 +0000495 bool &IsCopy,
Evan Chengc2f95b52009-03-01 02:03:43 +0000496 unsigned &DstReg, bool &IsDstPhys) {
Evan Chengf94d6832010-03-03 21:18:38 +0000497 if (!MRI->hasOneNonDBGUse(Reg))
498 // None or more than one use.
Craig Topperc0196b12014-04-14 00:51:57 +0000499 return nullptr;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000500 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
Evan Chengc2f95b52009-03-01 02:03:43 +0000501 if (UseMI.getParent() != MBB)
Craig Topperc0196b12014-04-14 00:51:57 +0000502 return nullptr;
Evan Chengc2f95b52009-03-01 02:03:43 +0000503 unsigned SrcReg;
504 bool IsSrcPhys;
Evan Cheng97871832009-04-14 00:32:25 +0000505 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
506 IsCopy = true;
Evan Chengc2f95b52009-03-01 02:03:43 +0000507 return &UseMI;
Evan Cheng97871832009-04-14 00:32:25 +0000508 }
Evan Chengc2f95b52009-03-01 02:03:43 +0000509 IsDstPhys = false;
Evan Cheng97871832009-04-14 00:32:25 +0000510 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
511 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
Evan Chengc2f95b52009-03-01 02:03:43 +0000512 return &UseMI;
Evan Cheng97871832009-04-14 00:32:25 +0000513 }
Craig Topperc0196b12014-04-14 00:51:57 +0000514 return nullptr;
Evan Chengc2f95b52009-03-01 02:03:43 +0000515}
516
Sanjay Patelb53791e2015-12-01 19:32:35 +0000517/// Return the physical register the specified virtual register might be mapped
518/// to.
Evan Chengc2f95b52009-03-01 02:03:43 +0000519static unsigned
520getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
521 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
522 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
523 if (SI == RegMap.end())
524 return 0;
525 Reg = SI->second;
526 }
527 if (TargetRegisterInfo::isPhysicalRegister(Reg))
528 return Reg;
529 return 0;
530}
531
Sanjay Patelb53791e2015-12-01 19:32:35 +0000532/// Return true if the two registers are equal or aliased.
Evan Chengc2f95b52009-03-01 02:03:43 +0000533static bool
534regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
535 if (RegA == RegB)
536 return true;
537 if (!RegA || !RegB)
538 return false;
539 return TRI->regsOverlap(RegA, RegB);
540}
541
Sanjay Patelb53791e2015-12-01 19:32:35 +0000542/// Return true if it's potentially profitable to commute the two-address
543/// instruction that's being processed.
Evan Chengabda6652009-01-25 03:53:59 +0000544bool
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000545TwoAddressInstructionPass::
546isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
547 MachineInstr *MI, unsigned Dist) {
Evan Cheng822ddde2011-11-16 18:44:48 +0000548 if (OptLevel == CodeGenOpt::None)
549 return false;
550
Evan Chengabda6652009-01-25 03:53:59 +0000551 // Determine if it's profitable to commute this two address instruction. In
552 // general, we want no uses between this instruction and the definition of
553 // the two-address register.
554 // e.g.
555 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
556 // %reg1029<def> = MOV8rr %reg1028
557 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
558 // insert => %reg1030<def> = MOV8rr %reg1028
559 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
560 // In this case, it might not be possible to coalesce the second MOV8rr
561 // instruction if the first one is coalesced. So it would be profitable to
562 // commute it:
563 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
564 // %reg1029<def> = MOV8rr %reg1028
565 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
566 // insert => %reg1030<def> = MOV8rr %reg1029
Andrew Trick808a7a62012-02-03 05:12:30 +0000567 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
Evan Chengabda6652009-01-25 03:53:59 +0000568
Cameron Zwarich9e722ae2013-02-21 07:02:30 +0000569 if (!isPlainlyKilled(MI, regC, LIS))
Evan Chengabda6652009-01-25 03:53:59 +0000570 return false;
571
572 // Ok, we have something like:
573 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
574 // let's see if it's worth commuting it.
575
Evan Chengc2f95b52009-03-01 02:03:43 +0000576 // Look for situations like this:
577 // %reg1024<def> = MOV r1
578 // %reg1025<def> = MOV r0
579 // %reg1026<def> = ADD %reg1024, %reg1025
580 // r0 = MOV %reg1026
581 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
Evan Chengb64e7b72012-05-03 01:45:13 +0000582 unsigned ToRegA = getMappedReg(regA, DstRegMap);
583 if (ToRegA) {
584 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
585 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
Craig Topper12f0d9e2014-11-05 06:43:02 +0000586 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
587 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
588
589 // Compute if any of the following are true:
590 // -RegB is not tied to a register and RegC is compatible with RegA.
591 // -RegB is tied to the wrong physical register, but RegC is.
592 // -RegB is tied to the wrong physical register, and RegC isn't tied.
593 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
594 return true;
595 // Don't compute if any of the following are true:
596 // -RegC is not tied to a register and RegB is compatible with RegA.
597 // -RegC is tied to the wrong physical register, but RegB is.
598 // -RegC is tied to the wrong physical register, and RegB isn't tied.
599 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
600 return false;
Evan Chengb64e7b72012-05-03 01:45:13 +0000601 }
Evan Chengc2f95b52009-03-01 02:03:43 +0000602
Evan Chengabda6652009-01-25 03:53:59 +0000603 // If there is a use of regC between its last def (could be livein) and this
604 // instruction, then bail.
605 unsigned LastDefC = 0;
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000606 if (!noUseAfterLastDef(regC, Dist, LastDefC))
Evan Chengabda6652009-01-25 03:53:59 +0000607 return false;
608
609 // If there is a use of regB between its last def (could be livein) and this
610 // instruction, then go ahead and make this transformation.
611 unsigned LastDefB = 0;
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000612 if (!noUseAfterLastDef(regB, Dist, LastDefB))
Evan Chengabda6652009-01-25 03:53:59 +0000613 return true;
614
Eric Christopher28919132015-03-03 22:03:03 +0000615 // Look for situation like this:
616 // %reg101 = MOV %reg100
617 // %reg102 = ...
618 // %reg103 = ADD %reg102, %reg101
619 // ... = %reg103 ...
620 // %reg100 = MOV %reg103
621 // If there is a reversed copy chain from reg101 to reg103, commute the ADD
622 // to eliminate an otherwise unavoidable copy.
623 // FIXME:
624 // We can extend the logic further: If an pair of operands in an insn has
625 // been merged, the insn could be regarded as a virtual copy, and the virtual
626 // copy could also be used to construct a copy chain.
627 // To more generally minimize register copies, ideally the logic of two addr
628 // instruction pass should be integrated with register allocation pass where
629 // interference graph is available.
630 if (isRevCopyChain(regC, regA, 3))
631 return true;
632
633 if (isRevCopyChain(regB, regA, 3))
634 return false;
635
Evan Chengabda6652009-01-25 03:53:59 +0000636 // Since there are no intervening uses for both registers, then commute
637 // if the def of regC is closer. Its live interval is shorter.
638 return LastDefB && LastDefC && LastDefC > LastDefB;
639}
640
Sanjay Patelb53791e2015-12-01 19:32:35 +0000641/// Commute a two-address instruction and update the basic block, distance map,
642/// and live variables if needed. Return true if it is successful.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000643bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,
644 unsigned RegBIdx,
645 unsigned RegCIdx,
646 unsigned Dist) {
647 unsigned RegC = MI->getOperand(RegCIdx).getReg();
David Greeneac9f8192010-01-05 01:24:21 +0000648 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000649 MachineInstr *NewMI = TII->commuteInstruction(MI, false, RegBIdx, RegCIdx);
Evan Cheng6d897062009-01-23 23:27:33 +0000650
Craig Topperc0196b12014-04-14 00:51:57 +0000651 if (NewMI == nullptr) {
David Greeneac9f8192010-01-05 01:24:21 +0000652 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
Evan Cheng6d897062009-01-23 23:27:33 +0000653 return false;
654 }
655
David Greeneac9f8192010-01-05 01:24:21 +0000656 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
Cameron Zwariche6907bc2013-02-23 23:13:28 +0000657 assert(NewMI == MI &&
658 "TargetInstrInfo::commuteInstruction() should not return a new "
659 "instruction unless it was requested.");
Evan Chengc2f95b52009-03-01 02:03:43 +0000660
661 // Update source register map.
662 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
663 if (FromRegC) {
664 unsigned RegA = MI->getOperand(0).getReg();
665 SrcRegMap[RegA] = FromRegC;
666 }
667
Evan Cheng6d897062009-01-23 23:27:33 +0000668 return true;
669}
670
Sanjay Patelb53791e2015-12-01 19:32:35 +0000671/// Return true if it is profitable to convert the given 2-address instruction
672/// to a 3-address one.
Evan Cheng09f5be82009-03-30 21:34:07 +0000673bool
Evan Cheng15fed7a2011-03-02 01:08:17 +0000674TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
Evan Cheng09f5be82009-03-30 21:34:07 +0000675 // Look for situations like this:
676 // %reg1024<def> = MOV r1
677 // %reg1025<def> = MOV r0
678 // %reg1026<def> = ADD %reg1024, %reg1025
679 // r2 = MOV %reg1026
680 // Turn ADD into a 3-address instruction to avoid a copy.
Evan Cheng15fed7a2011-03-02 01:08:17 +0000681 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
682 if (!FromRegB)
683 return false;
Evan Cheng09f5be82009-03-30 21:34:07 +0000684 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
Evan Cheng15fed7a2011-03-02 01:08:17 +0000685 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
Evan Cheng09f5be82009-03-30 21:34:07 +0000686}
687
Sanjay Patelb53791e2015-12-01 19:32:35 +0000688/// Convert the specified two-address instruction into a three address one.
689/// Return true if this transformation was successful.
Evan Cheng09f5be82009-03-30 21:34:07 +0000690bool
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000691TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
Evan Cheng09f5be82009-03-30 21:34:07 +0000692 MachineBasicBlock::iterator &nmi,
Evan Chengd4fcc052011-02-10 02:20:55 +0000693 unsigned RegA, unsigned RegB,
694 unsigned Dist) {
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000695 // FIXME: Why does convertToThreeAddress() need an iterator reference?
Duncan P. N. Exon Smithf1ff53e2015-10-09 22:56:24 +0000696 MachineFunction::iterator MFI = MBB->getIterator();
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000697 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
Duncan P. N. Exon Smithf1ff53e2015-10-09 22:56:24 +0000698 assert(MBB->getIterator() == MFI &&
699 "convertToThreeAddress changed iterator reference");
Jakob Stoklund Olesen1dfe4fc2012-10-26 23:05:13 +0000700 if (!NewMI)
701 return false;
Evan Cheng09f5be82009-03-30 21:34:07 +0000702
Jakob Stoklund Olesen1dfe4fc2012-10-26 23:05:13 +0000703 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
704 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
705 bool Sunk = false;
Jakob Stoklund Olesen24bc5142012-08-03 22:58:34 +0000706
Cameron Zwarich2ad3ca32013-02-20 22:10:02 +0000707 if (LIS)
Duncan P. N. Exon Smith3ac9cc62016-02-27 06:40:41 +0000708 LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
Evan Cheng09f5be82009-03-30 21:34:07 +0000709
Jakob Stoklund Olesen1dfe4fc2012-10-26 23:05:13 +0000710 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
711 // FIXME: Temporary workaround. If the new instruction doesn't
712 // uses RegB, convertToThreeAddress must have created more
713 // then one instruction.
714 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
Evan Cheng09f5be82009-03-30 21:34:07 +0000715
Jakob Stoklund Olesen1dfe4fc2012-10-26 23:05:13 +0000716 MBB->erase(mi); // Nuke the old inst.
Evan Chengd4fcc052011-02-10 02:20:55 +0000717
Jakob Stoklund Olesen1dfe4fc2012-10-26 23:05:13 +0000718 if (!Sunk) {
719 DistanceMap.insert(std::make_pair(NewMI, Dist));
720 mi = NewMI;
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000721 nmi = std::next(mi);
Evan Cheng09f5be82009-03-30 21:34:07 +0000722 }
723
Jakob Stoklund Olesen1dfe4fc2012-10-26 23:05:13 +0000724 // Update source and destination register maps.
725 SrcRegMap.erase(RegA);
726 DstRegMap.erase(RegB);
727 return true;
Evan Cheng09f5be82009-03-30 21:34:07 +0000728}
729
Sanjay Patelb53791e2015-12-01 19:32:35 +0000730/// Scan forward recursively for only uses, update maps if the use is a copy or
731/// a two-address instruction.
Evan Cheng15fed7a2011-03-02 01:08:17 +0000732void
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000733TwoAddressInstructionPass::scanUses(unsigned DstReg) {
Evan Cheng15fed7a2011-03-02 01:08:17 +0000734 SmallVector<unsigned, 4> VirtRegPairs;
735 bool IsDstPhys;
736 bool IsCopy = false;
737 unsigned NewReg = 0;
738 unsigned Reg = DstReg;
739 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
740 NewReg, IsDstPhys)) {
David Blaikie70573dc2014-11-19 07:49:26 +0000741 if (IsCopy && !Processed.insert(UseMI).second)
Evan Cheng15fed7a2011-03-02 01:08:17 +0000742 break;
743
744 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
745 if (DI != DistanceMap.end())
746 // Earlier in the same MBB.Reached via a back edge.
747 break;
748
749 if (IsDstPhys) {
750 VirtRegPairs.push_back(NewReg);
751 break;
752 }
753 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
754 if (!isNew)
755 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
756 VirtRegPairs.push_back(NewReg);
757 Reg = NewReg;
758 }
759
760 if (!VirtRegPairs.empty()) {
761 unsigned ToReg = VirtRegPairs.back();
762 VirtRegPairs.pop_back();
763 while (!VirtRegPairs.empty()) {
764 unsigned FromReg = VirtRegPairs.back();
765 VirtRegPairs.pop_back();
766 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
767 if (!isNew)
768 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
769 ToReg = FromReg;
770 }
771 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
772 if (!isNew)
773 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
774 }
775}
776
Sanjay Patelb53791e2015-12-01 19:32:35 +0000777/// If the specified instruction is not yet processed, process it if it's a
778/// copy. For a copy instruction, we find the physical registers the
Evan Chengc2f95b52009-03-01 02:03:43 +0000779/// source and destination registers might be mapped to. These are kept in
780/// point-to maps used to determine future optimizations. e.g.
781/// v1024 = mov r0
782/// v1025 = mov r1
783/// v1026 = add v1024, v1025
784/// r1 = mov r1026
785/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
786/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
787/// potentially joined with r1 on the output side. It's worthwhile to commute
788/// 'add' to eliminate a copy.
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000789void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
Evan Chengc2f95b52009-03-01 02:03:43 +0000790 if (Processed.count(MI))
791 return;
792
793 bool IsSrcPhys, IsDstPhys;
794 unsigned SrcReg, DstReg;
795 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
796 return;
797
798 if (IsDstPhys && !IsSrcPhys)
799 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
800 else if (!IsDstPhys && IsSrcPhys) {
Evan Chengf0843802009-04-13 20:04:24 +0000801 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
802 if (!isNew)
803 assert(SrcRegMap[DstReg] == SrcReg &&
804 "Can't map to two src physical registers!");
Evan Chengc2f95b52009-03-01 02:03:43 +0000805
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000806 scanUses(DstReg);
Evan Chengc2f95b52009-03-01 02:03:43 +0000807 }
808
809 Processed.insert(MI);
810}
811
Sanjay Patelb53791e2015-12-01 19:32:35 +0000812/// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
813/// consider moving the instruction below the kill instruction in order to
814/// eliminate the need for the copy.
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000815bool TwoAddressInstructionPass::
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000816rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +0000817 MachineBasicBlock::iterator &nmi,
818 unsigned Reg) {
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000819 // Bail immediately if we don't have LV or LIS available. We use them to find
820 // kills efficiently.
821 if (!LV && !LIS)
Chandler Carruthdb5536f2012-07-15 03:29:46 +0000822 return false;
823
Evan Cheng30f44ad2011-11-14 19:48:55 +0000824 MachineInstr *MI = &*mi;
Andrew Trick808a7a62012-02-03 05:12:30 +0000825 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
Evan Cheng30f44ad2011-11-14 19:48:55 +0000826 if (DI == DistanceMap.end())
827 // Must be created from unfolded load. Don't waste time trying this.
828 return false;
829
Craig Topperc0196b12014-04-14 00:51:57 +0000830 MachineInstr *KillMI = nullptr;
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000831 if (LIS) {
832 LiveInterval &LI = LIS->getInterval(Reg);
833 assert(LI.end() != LI.begin() &&
834 "Reg should not have empty live interval.");
835
836 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
837 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
838 if (I != LI.end() && I->start < MBBEndIdx)
839 return false;
840
841 --I;
842 KillMI = LIS->getInstructionFromIndex(I->end);
843 } else {
844 KillMI = LV->getVarInfo(Reg).findKill(MBB);
845 }
Chandler Carruthdb5536f2012-07-15 03:29:46 +0000846 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
Evan Cheng30f44ad2011-11-14 19:48:55 +0000847 // Don't mess with copies, they may be coalesced later.
848 return false;
849
Evan Cheng7f8e5632011-12-07 07:15:52 +0000850 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
851 KillMI->isBranch() || KillMI->isTerminator())
Evan Cheng30f44ad2011-11-14 19:48:55 +0000852 // Don't move pass calls, etc.
853 return false;
854
855 unsigned DstReg;
856 if (isTwoAddrUse(*KillMI, Reg, DstReg))
857 return false;
858
Evan Cheng7098c4e2011-11-15 06:26:51 +0000859 bool SeenStore = true;
Matthias Braun07066cc2015-05-19 21:22:20 +0000860 if (!MI->isSafeToMove(AA, SeenStore))
Evan Cheng30f44ad2011-11-14 19:48:55 +0000861 return false;
862
863 if (TII->getInstrLatency(InstrItins, MI) > 1)
864 // FIXME: Needs more sophisticated heuristics.
865 return false;
866
867 SmallSet<unsigned, 2> Uses;
Evan Chengb8c55a52011-11-16 03:47:42 +0000868 SmallSet<unsigned, 2> Kills;
Evan Cheng30f44ad2011-11-14 19:48:55 +0000869 SmallSet<unsigned, 2> Defs;
Sanjay Patel0b2a9492015-12-01 19:57:43 +0000870 for (const MachineOperand &MO : MI->operands()) {
Evan Cheng30f44ad2011-11-14 19:48:55 +0000871 if (!MO.isReg())
872 continue;
873 unsigned MOReg = MO.getReg();
874 if (!MOReg)
875 continue;
876 if (MO.isDef())
877 Defs.insert(MOReg);
Evan Chengb8c55a52011-11-16 03:47:42 +0000878 else {
Evan Cheng30f44ad2011-11-14 19:48:55 +0000879 Uses.insert(MOReg);
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000880 if (MOReg != Reg && (MO.isKill() ||
881 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
Evan Chengb8c55a52011-11-16 03:47:42 +0000882 Kills.insert(MOReg);
883 }
Evan Cheng30f44ad2011-11-14 19:48:55 +0000884 }
885
886 // Move the copies connected to MI down as well.
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000887 MachineBasicBlock::iterator Begin = MI;
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000888 MachineBasicBlock::iterator AfterMI = std::next(Begin);
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000889
890 MachineBasicBlock::iterator End = AfterMI;
891 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
892 Defs.insert(End->getOperand(0).getReg());
893 ++End;
Evan Cheng30f44ad2011-11-14 19:48:55 +0000894 }
895
896 // Check if the reschedule will not break depedencies.
897 unsigned NumVisited = 0;
898 MachineBasicBlock::iterator KillPos = KillMI;
899 ++KillPos;
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000900 for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) {
Evan Cheng30f44ad2011-11-14 19:48:55 +0000901 MachineInstr *OtherMI = I;
902 // DBG_VALUE cannot be counted against the limit.
903 if (OtherMI->isDebugValue())
904 continue;
905 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
906 return false;
907 ++NumVisited;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000908 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
909 OtherMI->isBranch() || OtherMI->isTerminator())
Evan Cheng30f44ad2011-11-14 19:48:55 +0000910 // Don't move pass calls, etc.
911 return false;
Sanjay Patel0b2a9492015-12-01 19:57:43 +0000912 for (const MachineOperand &MO : OtherMI->operands()) {
Evan Cheng30f44ad2011-11-14 19:48:55 +0000913 if (!MO.isReg())
914 continue;
915 unsigned MOReg = MO.getReg();
916 if (!MOReg)
917 continue;
918 if (MO.isDef()) {
919 if (Uses.count(MOReg))
920 // Physical register use would be clobbered.
921 return false;
922 if (!MO.isDead() && Defs.count(MOReg))
923 // May clobber a physical register def.
924 // FIXME: This may be too conservative. It's ok if the instruction
925 // is sunken completely below the use.
926 return false;
927 } else {
928 if (Defs.count(MOReg))
929 return false;
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000930 bool isKill = MO.isKill() ||
931 (LIS && isPlainlyKilled(OtherMI, MOReg, LIS));
Evan Chengb8c55a52011-11-16 03:47:42 +0000932 if (MOReg != Reg &&
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000933 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
Evan Cheng30f44ad2011-11-14 19:48:55 +0000934 // Don't want to extend other live ranges and update kills.
935 return false;
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000936 if (MOReg == Reg && !isKill)
Chandler Carruthdb5536f2012-07-15 03:29:46 +0000937 // We can't schedule across a use of the register in question.
938 return false;
939 // Ensure that if this is register in question, its the kill we expect.
940 assert((MOReg != Reg || OtherMI == KillMI) &&
941 "Found multiple kills of a register in a basic block");
Evan Cheng30f44ad2011-11-14 19:48:55 +0000942 }
943 }
944 }
945
946 // Move debug info as well.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000947 while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000948 --Begin;
949
950 nmi = End;
951 MachineBasicBlock::iterator InsertPos = KillPos;
952 if (LIS) {
953 // We have to move the copies first so that the MBB is still well-formed
954 // when calling handleMove().
955 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
956 MachineInstr *CopyMI = MBBI;
957 ++MBBI;
958 MBB->splice(InsertPos, MBB, CopyMI);
Duncan P. N. Exon Smithbe8f8c42016-02-27 20:14:29 +0000959 LIS->handleMove(*CopyMI);
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000960 InsertPos = CopyMI;
961 }
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000962 End = std::next(MachineBasicBlock::iterator(MI));
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000963 }
Evan Cheng30f44ad2011-11-14 19:48:55 +0000964
965 // Copies following MI may have been moved as well.
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000966 MBB->splice(InsertPos, MBB, Begin, End);
Evan Cheng30f44ad2011-11-14 19:48:55 +0000967 DistanceMap.erase(DI);
968
Chandler Carruthdb5536f2012-07-15 03:29:46 +0000969 // Update live variables
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000970 if (LIS) {
Duncan P. N. Exon Smithbe8f8c42016-02-27 20:14:29 +0000971 LIS->handleMove(*MI);
Cameron Zwarich7d13fb42013-02-23 04:49:13 +0000972 } else {
973 LV->removeVirtualRegisterKilled(Reg, KillMI);
974 LV->addVirtualRegisterKilled(Reg, MI);
975 }
Evan Cheng30f44ad2011-11-14 19:48:55 +0000976
Jakob Stoklund Olesen0ef03112012-07-17 17:57:23 +0000977 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
Evan Cheng30f44ad2011-11-14 19:48:55 +0000978 return true;
979}
980
Sanjay Patelb53791e2015-12-01 19:32:35 +0000981/// Return true if the re-scheduling will put the given instruction too close
982/// to the defs of its register dependencies.
Evan Cheng30f44ad2011-11-14 19:48:55 +0000983bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +0000984 MachineInstr *MI) {
Owen Andersonb36376e2014-03-17 19:36:09 +0000985 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
986 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
Evan Cheng30f44ad2011-11-14 19:48:55 +0000987 continue;
Owen Andersonb36376e2014-03-17 19:36:09 +0000988 if (&DefMI == MI)
Evan Cheng30f44ad2011-11-14 19:48:55 +0000989 return true; // MI is defining something KillMI uses
Owen Andersonb36376e2014-03-17 19:36:09 +0000990 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
Evan Cheng30f44ad2011-11-14 19:48:55 +0000991 if (DDI == DistanceMap.end())
992 return true; // Below MI
993 unsigned DefDist = DDI->second;
994 assert(Dist > DefDist && "Visited def already?");
Owen Andersonb36376e2014-03-17 19:36:09 +0000995 if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
Evan Cheng30f44ad2011-11-14 19:48:55 +0000996 return true;
997 }
998 return false;
999}
1000
Sanjay Patelb53791e2015-12-01 19:32:35 +00001001/// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
1002/// consider moving the kill instruction above the current two-address
1003/// instruction in order to eliminate the need for the copy.
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +00001004bool TwoAddressInstructionPass::
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001005rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +00001006 MachineBasicBlock::iterator &nmi,
1007 unsigned Reg) {
Cameron Zwarich7d13fb42013-02-23 04:49:13 +00001008 // Bail immediately if we don't have LV or LIS available. We use them to find
1009 // kills efficiently.
1010 if (!LV && !LIS)
Chandler Carruthdb5536f2012-07-15 03:29:46 +00001011 return false;
1012
Evan Cheng30f44ad2011-11-14 19:48:55 +00001013 MachineInstr *MI = &*mi;
1014 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
1015 if (DI == DistanceMap.end())
1016 // Must be created from unfolded load. Don't waste time trying this.
1017 return false;
1018
Craig Topperc0196b12014-04-14 00:51:57 +00001019 MachineInstr *KillMI = nullptr;
Cameron Zwarich7d13fb42013-02-23 04:49:13 +00001020 if (LIS) {
1021 LiveInterval &LI = LIS->getInterval(Reg);
1022 assert(LI.end() != LI.begin() &&
1023 "Reg should not have empty live interval.");
1024
1025 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
1026 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
1027 if (I != LI.end() && I->start < MBBEndIdx)
1028 return false;
1029
1030 --I;
1031 KillMI = LIS->getInstructionFromIndex(I->end);
1032 } else {
1033 KillMI = LV->getVarInfo(Reg).findKill(MBB);
1034 }
Chandler Carruthdb5536f2012-07-15 03:29:46 +00001035 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
Evan Cheng30f44ad2011-11-14 19:48:55 +00001036 // Don't mess with copies, they may be coalesced later.
1037 return false;
1038
1039 unsigned DstReg;
1040 if (isTwoAddrUse(*KillMI, Reg, DstReg))
1041 return false;
1042
Evan Cheng7098c4e2011-11-15 06:26:51 +00001043 bool SeenStore = true;
Matthias Braun07066cc2015-05-19 21:22:20 +00001044 if (!KillMI->isSafeToMove(AA, SeenStore))
Evan Cheng30f44ad2011-11-14 19:48:55 +00001045 return false;
1046
1047 SmallSet<unsigned, 2> Uses;
1048 SmallSet<unsigned, 2> Kills;
1049 SmallSet<unsigned, 2> Defs;
1050 SmallSet<unsigned, 2> LiveDefs;
Sanjay Patel0b2a9492015-12-01 19:57:43 +00001051 for (const MachineOperand &MO : KillMI->operands()) {
Evan Cheng30f44ad2011-11-14 19:48:55 +00001052 if (!MO.isReg())
1053 continue;
1054 unsigned MOReg = MO.getReg();
1055 if (MO.isUse()) {
1056 if (!MOReg)
1057 continue;
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001058 if (isDefTooClose(MOReg, DI->second, MI))
Evan Cheng30f44ad2011-11-14 19:48:55 +00001059 return false;
Cameron Zwarich7d13fb42013-02-23 04:49:13 +00001060 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
1061 if (MOReg == Reg && !isKill)
Chandler Carruthdb5536f2012-07-15 03:29:46 +00001062 return false;
Evan Cheng30f44ad2011-11-14 19:48:55 +00001063 Uses.insert(MOReg);
Cameron Zwarich7d13fb42013-02-23 04:49:13 +00001064 if (isKill && MOReg != Reg)
Evan Cheng30f44ad2011-11-14 19:48:55 +00001065 Kills.insert(MOReg);
1066 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1067 Defs.insert(MOReg);
1068 if (!MO.isDead())
1069 LiveDefs.insert(MOReg);
1070 }
1071 }
1072
1073 // Check if the reschedule will not break depedencies.
1074 unsigned NumVisited = 0;
1075 MachineBasicBlock::iterator KillPos = KillMI;
1076 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
1077 MachineInstr *OtherMI = I;
1078 // DBG_VALUE cannot be counted against the limit.
1079 if (OtherMI->isDebugValue())
1080 continue;
1081 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1082 return false;
1083 ++NumVisited;
Evan Cheng7f8e5632011-12-07 07:15:52 +00001084 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
1085 OtherMI->isBranch() || OtherMI->isTerminator())
Evan Cheng30f44ad2011-11-14 19:48:55 +00001086 // Don't move pass calls, etc.
1087 return false;
Evan Cheng9ddd69a2011-11-16 03:05:12 +00001088 SmallVector<unsigned, 2> OtherDefs;
Sanjay Patel0b2a9492015-12-01 19:57:43 +00001089 for (const MachineOperand &MO : OtherMI->operands()) {
Evan Cheng30f44ad2011-11-14 19:48:55 +00001090 if (!MO.isReg())
1091 continue;
1092 unsigned MOReg = MO.getReg();
1093 if (!MOReg)
1094 continue;
1095 if (MO.isUse()) {
1096 if (Defs.count(MOReg))
1097 // Moving KillMI can clobber the physical register if the def has
1098 // not been seen.
1099 return false;
1100 if (Kills.count(MOReg))
1101 // Don't want to extend other live ranges and update kills.
1102 return false;
Cameron Zwarich7d13fb42013-02-23 04:49:13 +00001103 if (OtherMI != MI && MOReg == Reg &&
1104 !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))))
Chandler Carruthdb5536f2012-07-15 03:29:46 +00001105 // We can't schedule across a use of the register in question.
1106 return false;
Evan Cheng30f44ad2011-11-14 19:48:55 +00001107 } else {
Evan Cheng9ddd69a2011-11-16 03:05:12 +00001108 OtherDefs.push_back(MOReg);
Evan Cheng30f44ad2011-11-14 19:48:55 +00001109 }
1110 }
Evan Cheng9ddd69a2011-11-16 03:05:12 +00001111
1112 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1113 unsigned MOReg = OtherDefs[i];
1114 if (Uses.count(MOReg))
1115 return false;
1116 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1117 LiveDefs.count(MOReg))
1118 return false;
1119 // Physical register def is seen.
1120 Defs.erase(MOReg);
1121 }
Evan Cheng30f44ad2011-11-14 19:48:55 +00001122 }
1123
1124 // Move the old kill above MI, don't forget to move debug info as well.
1125 MachineBasicBlock::iterator InsertPos = mi;
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00001126 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
Evan Chengf2fc5082011-11-14 21:11:15 +00001127 --InsertPos;
Evan Cheng30f44ad2011-11-14 19:48:55 +00001128 MachineBasicBlock::iterator From = KillMI;
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00001129 MachineBasicBlock::iterator To = std::next(From);
1130 while (std::prev(From)->isDebugValue())
Evan Cheng30f44ad2011-11-14 19:48:55 +00001131 --From;
1132 MBB->splice(InsertPos, MBB, From, To);
1133
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00001134 nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
Evan Cheng30f44ad2011-11-14 19:48:55 +00001135 DistanceMap.erase(DI);
1136
Chandler Carruthdb5536f2012-07-15 03:29:46 +00001137 // Update live variables
Cameron Zwarich7d13fb42013-02-23 04:49:13 +00001138 if (LIS) {
Duncan P. N. Exon Smithbe8f8c42016-02-27 20:14:29 +00001139 LIS->handleMove(*KillMI);
Cameron Zwarich7d13fb42013-02-23 04:49:13 +00001140 } else {
1141 LV->removeVirtualRegisterKilled(Reg, KillMI);
1142 LV->addVirtualRegisterKilled(Reg, MI);
1143 }
Chandler Carruthdb5536f2012-07-15 03:29:46 +00001144
Jakob Stoklund Olesen0ef03112012-07-17 17:57:23 +00001145 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
Evan Cheng30f44ad2011-11-14 19:48:55 +00001146 return true;
1147}
1148
Andrew Kaylor16c4da02015-09-28 20:33:22 +00001149/// Tries to commute the operand 'BaseOpIdx' and some other operand in the
1150/// given machine instruction to improve opportunities for coalescing and
1151/// elimination of a register to register copy.
1152///
1153/// 'DstOpIdx' specifies the index of MI def operand.
1154/// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
1155/// operand is killed by the given instruction.
1156/// The 'Dist' arguments provides the distance of MI from the start of the
1157/// current basic block and it is used to determine if it is profitable
1158/// to commute operands in the instruction.
1159///
1160/// Returns true if the transformation happened. Otherwise, returns false.
1161bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
1162 unsigned DstOpIdx,
1163 unsigned BaseOpIdx,
1164 bool BaseOpKilled,
1165 unsigned Dist) {
1166 unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg();
1167 unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1168 unsigned OpsNum = MI->getDesc().getNumOperands();
1169 unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1170 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1171 // The call of findCommutedOpIndices below only checks if BaseOpIdx
Sanjay Patel96824de2015-12-01 19:19:18 +00001172 // and OtherOpIdx are commutable, it does not really search for
Andrew Kaylor16c4da02015-09-28 20:33:22 +00001173 // other commutable operands and does not change the values of passed
1174 // variables.
1175 if (OtherOpIdx == BaseOpIdx ||
1176 !TII->findCommutedOpIndices(MI, BaseOpIdx, OtherOpIdx))
1177 continue;
1178
1179 unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1180 bool AggressiveCommute = false;
1181
1182 // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
1183 // operands. This makes the live ranges of DstOp and OtherOp joinable.
1184 bool DoCommute =
1185 !BaseOpKilled && isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
1186
1187 if (!DoCommute &&
1188 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
1189 DoCommute = true;
1190 AggressiveCommute = true;
1191 }
1192
1193 // If it's profitable to commute, try to do so.
1194 if (DoCommute && commuteInstruction(MI, BaseOpIdx, OtherOpIdx, Dist)) {
1195 ++NumCommuted;
1196 if (AggressiveCommute)
1197 ++NumAggrCommuted;
1198 return true;
1199 }
1200 }
1201 return false;
1202}
1203
Sanjay Patelb53791e2015-12-01 19:32:35 +00001204/// For the case where an instruction has a single pair of tied register
1205/// operands, attempt some transformations that may either eliminate the tied
1206/// operands or improve the opportunities for coalescing away the register copy.
1207/// Returns true if no copy needs to be inserted to untie mi's operands
1208/// (either because they were untied, or because mi was rescheduled, and will
1209/// be visited again later). If the shouldOnlyCommute flag is true, only
1210/// instruction commutation is attempted.
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001211bool TwoAddressInstructionPass::
Jakob Stoklund Olesen112a44d2012-10-26 21:12:49 +00001212tryInstructionTransform(MachineBasicBlock::iterator &mi,
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001213 MachineBasicBlock::iterator &nmi,
Cameron Zwarichf05c0cb2013-02-24 00:27:26 +00001214 unsigned SrcIdx, unsigned DstIdx,
1215 unsigned Dist, bool shouldOnlyCommute) {
Evan Cheng822ddde2011-11-16 18:44:48 +00001216 if (OptLevel == CodeGenOpt::None)
1217 return false;
1218
Evan Cheng30f44ad2011-11-14 19:48:55 +00001219 MachineInstr &MI = *mi;
Evan Cheng30f44ad2011-11-14 19:48:55 +00001220 unsigned regA = MI.getOperand(DstIdx).getReg();
1221 unsigned regB = MI.getOperand(SrcIdx).getReg();
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001222
1223 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1224 "cannot make instruction into two-address form");
Cameron Zwarich384026b2013-02-21 22:58:42 +00001225 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001226
Evan Chengb64e7b72012-05-03 01:45:13 +00001227 if (TargetRegisterInfo::isVirtualRegister(regA))
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001228 scanUses(regA);
Evan Chengb64e7b72012-05-03 01:45:13 +00001229
Andrew Kaylor16c4da02015-09-28 20:33:22 +00001230 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001231
Quentin Colombet9729fb32015-07-01 23:12:13 +00001232 // If the instruction is convertible to 3 Addr, instead
1233 // of returning try 3 Addr transformation aggresively and
1234 // use this variable to check later. Because it might be better.
1235 // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1236 // instead of the following code.
NAKAMURA Takumi84965032015-09-22 11:14:12 +00001237 // addl %esi, %edi
1238 // movl %edi, %eax
Quentin Colombet9729fb32015-07-01 23:12:13 +00001239 // ret
Andrew Kaylor16c4da02015-09-28 20:33:22 +00001240 if (Commuted && !MI.isConvertibleTo3Addr())
1241 return false;
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001242
Cameron Zwarichf05c0cb2013-02-24 00:27:26 +00001243 if (shouldOnlyCommute)
1244 return false;
1245
Evan Cheng30f44ad2011-11-14 19:48:55 +00001246 // If there is one more use of regB later in the same MBB, consider
1247 // re-schedule this MI below it.
Quentin Colombet40dd5102015-07-06 20:12:54 +00001248 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
Evan Cheng30f44ad2011-11-14 19:48:55 +00001249 ++NumReSchedDowns;
Lang Hames3ad11ff2012-04-09 20:17:30 +00001250 return true;
Evan Cheng30f44ad2011-11-14 19:48:55 +00001251 }
1252
Craig Topper2c4068f2015-10-06 05:39:59 +00001253 // If we commuted, regB may have changed so we should re-sample it to avoid
1254 // confusing the three address conversion below.
1255 if (Commuted) {
1256 regB = MI.getOperand(SrcIdx).getReg();
1257 regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1258 }
1259
Evan Cheng7f8e5632011-12-07 07:15:52 +00001260 if (MI.isConvertibleTo3Addr()) {
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001261 // This instruction is potentially convertible to a true
1262 // three-address instruction. Check if it is profitable.
Evan Cheng15fed7a2011-03-02 01:08:17 +00001263 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001264 // Try to convert it.
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001265 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001266 ++NumConvertedTo3Addr;
1267 return true; // Done with this instruction.
1268 }
1269 }
1270 }
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001271
Quentin Colombet9729fb32015-07-01 23:12:13 +00001272 // Return if it is commuted but 3 addr conversion is failed.
Quentin Colombet40dd5102015-07-06 20:12:54 +00001273 if (Commuted)
Quentin Colombet9729fb32015-07-01 23:12:13 +00001274 return false;
1275
Evan Cheng30f44ad2011-11-14 19:48:55 +00001276 // If there is one more use of regB later in the same MBB, consider
1277 // re-schedule it before this MI if it's legal.
Andrew Trick608a6982013-04-24 15:54:39 +00001278 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
Evan Cheng30f44ad2011-11-14 19:48:55 +00001279 ++NumReSchedUps;
Lang Hames3ad11ff2012-04-09 20:17:30 +00001280 return true;
Evan Cheng30f44ad2011-11-14 19:48:55 +00001281 }
1282
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001283 // If this is an instruction with a load folded into it, try unfolding
1284 // the load, e.g. avoid this:
1285 // movq %rdx, %rcx
1286 // addq (%rax), %rcx
1287 // in favor of this:
1288 // movq (%rax), %rcx
1289 // addq %rdx, %rcx
1290 // because it's preferable to schedule a load than a register copy.
Evan Cheng7f8e5632011-12-07 07:15:52 +00001291 if (MI.mayLoad() && !regBKilled) {
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001292 // Determine if a load can be unfolded.
1293 unsigned LoadRegIndex;
1294 unsigned NewOpc =
Evan Cheng30f44ad2011-11-14 19:48:55 +00001295 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001296 /*UnfoldLoad=*/true,
1297 /*UnfoldStore=*/false,
1298 &LoadRegIndex);
1299 if (NewOpc != 0) {
Evan Cheng6cc775f2011-06-28 19:10:37 +00001300 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1301 if (UnfoldMCID.getNumDefs() == 1) {
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001302 // Unfold the load.
Evan Cheng30f44ad2011-11-14 19:48:55 +00001303 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001304 const TargetRegisterClass *RC =
Andrew Trick32aea352012-05-03 01:14:37 +00001305 TRI->getAllocatableClass(
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001306 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001307 unsigned Reg = MRI->createVirtualRegister(RC);
1308 SmallVector<MachineInstr *, 2> NewMIs;
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001309 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
Evan Cheng0ce84482010-07-02 20:36:18 +00001310 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1311 NewMIs)) {
1312 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1313 return false;
1314 }
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001315 assert(NewMIs.size() == 2 &&
1316 "Unfolded a load into multiple instructions!");
1317 // The load was previously folded, so this is the only use.
1318 NewMIs[1]->addRegisterKilled(Reg, TRI);
1319
1320 // Tentatively insert the instructions into the block so that they
1321 // look "normal" to the transformation logic.
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001322 MBB->insert(mi, NewMIs[0]);
1323 MBB->insert(mi, NewMIs[1]);
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001324
1325 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1326 << "2addr: NEW INST: " << *NewMIs[1]);
1327
1328 // Transform the instruction, now that it no longer has a load.
1329 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1330 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1331 MachineBasicBlock::iterator NewMI = NewMIs[1];
Cameron Zwarich6868f382013-02-24 00:27:29 +00001332 bool TransformResult =
Cameron Zwarichf05c0cb2013-02-24 00:27:26 +00001333 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
Cameron Zwarich1b4c64c2013-02-24 01:26:05 +00001334 (void)TransformResult;
Cameron Zwarich6868f382013-02-24 00:27:29 +00001335 assert(!TransformResult &&
1336 "tryInstructionTransform() should return false.");
1337 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001338 // Success, or at least we made an improvement. Keep the unfolded
1339 // instructions and discard the original.
1340 if (LV) {
Evan Cheng30f44ad2011-11-14 19:48:55 +00001341 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1342 MachineOperand &MO = MI.getOperand(i);
Andrew Trick808a7a62012-02-03 05:12:30 +00001343 if (MO.isReg() &&
Dan Gohman851e4782010-06-22 00:32:04 +00001344 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1345 if (MO.isUse()) {
Dan Gohman2370e2f2010-06-22 02:07:21 +00001346 if (MO.isKill()) {
1347 if (NewMIs[0]->killsRegister(MO.getReg()))
Evan Cheng30f44ad2011-11-14 19:48:55 +00001348 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
Dan Gohman2370e2f2010-06-22 02:07:21 +00001349 else {
1350 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1351 "Kill missing after load unfold!");
Evan Cheng30f44ad2011-11-14 19:48:55 +00001352 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
Dan Gohman2370e2f2010-06-22 02:07:21 +00001353 }
1354 }
Evan Cheng30f44ad2011-11-14 19:48:55 +00001355 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
Dan Gohman2370e2f2010-06-22 02:07:21 +00001356 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1357 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1358 else {
1359 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1360 "Dead flag missing after load unfold!");
1361 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1362 }
1363 }
Dan Gohman851e4782010-06-22 00:32:04 +00001364 }
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001365 }
1366 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1367 }
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001368
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001369 SmallVector<unsigned, 4> OrigRegs;
1370 if (LIS) {
Craig Topperda5168b2015-10-08 06:06:42 +00001371 for (const MachineOperand &MO : MI.operands()) {
1372 if (MO.isReg())
1373 OrigRegs.push_back(MO.getReg());
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001374 }
1375 }
1376
Evan Cheng30f44ad2011-11-14 19:48:55 +00001377 MI.eraseFromParent();
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001378
1379 // Update LiveIntervals.
Cameron Zwarichcaad7e12013-02-20 22:10:00 +00001380 if (LIS) {
1381 MachineBasicBlock::iterator Begin(NewMIs[0]);
1382 MachineBasicBlock::iterator End(NewMIs[1]);
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001383 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
Cameron Zwarichcaad7e12013-02-20 22:10:00 +00001384 }
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001385
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001386 mi = NewMIs[1];
Dan Gohman3c1b3c62010-06-21 22:17:20 +00001387 } else {
1388 // Transforming didn't eliminate the tie and didn't lead to an
1389 // improvement. Clean up the unfolded instructions and keep the
1390 // original.
1391 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1392 NewMIs[0]->eraseFromParent();
1393 NewMIs[1]->eraseFromParent();
1394 }
1395 }
1396 }
1397 }
1398
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001399 return false;
1400}
1401
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001402// Collect tied operands of MI that need to be handled.
1403// Rewrite trivial cases immediately.
1404// Return true if any tied operands where found, including the trivial ones.
1405bool TwoAddressInstructionPass::
1406collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1407 const MCInstrDesc &MCID = MI->getDesc();
1408 bool AnyOps = false;
Jakob Stoklund Olesenade363e2012-09-04 22:59:30 +00001409 unsigned NumOps = MI->getNumOperands();
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001410
1411 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1412 unsigned DstIdx = 0;
1413 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1414 continue;
1415 AnyOps = true;
Jakob Stoklund Olesenfbf45dc2012-08-07 22:47:06 +00001416 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1417 MachineOperand &DstMO = MI->getOperand(DstIdx);
1418 unsigned SrcReg = SrcMO.getReg();
1419 unsigned DstReg = DstMO.getReg();
1420 // Tied constraint already satisfied?
1421 if (SrcReg == DstReg)
1422 continue;
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001423
Jakob Stoklund Olesenfbf45dc2012-08-07 22:47:06 +00001424 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001425
1426 // Deal with <undef> uses immediately - simply rewrite the src operand.
Andrew Tricke3398282013-12-17 04:50:45 +00001427 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001428 // Constrain the DstReg register class if required.
1429 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1430 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1431 TRI, *MF))
1432 MRI->constrainRegClass(DstReg, RC);
Jakob Stoklund Olesenfbf45dc2012-08-07 22:47:06 +00001433 SrcMO.setReg(DstReg);
Andrew Tricke3398282013-12-17 04:50:45 +00001434 SrcMO.setSubReg(0);
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001435 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1436 continue;
1437 }
Jakob Stoklund Olesenfbf45dc2012-08-07 22:47:06 +00001438 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001439 }
1440 return AnyOps;
1441}
1442
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001443// Process a list of tied MI operands that all use the same source register.
1444// The tied pairs are of the form (SrcIdx, DstIdx).
1445void
1446TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1447 TiedPairList &TiedPairs,
1448 unsigned &Dist) {
1449 bool IsEarlyClobber = false;
Cameron Zwarich2991feb2013-02-20 06:46:46 +00001450 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1451 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1452 IsEarlyClobber |= DstMO.isEarlyClobber();
1453 }
1454
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001455 bool RemovedKillFlag = false;
1456 bool AllUsesCopied = true;
1457 unsigned LastCopiedReg = 0;
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001458 SlotIndex LastCopyIdx;
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001459 unsigned RegB = 0;
Andrew Tricke3398282013-12-17 04:50:45 +00001460 unsigned SubRegB = 0;
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001461 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1462 unsigned SrcIdx = TiedPairs[tpi].first;
1463 unsigned DstIdx = TiedPairs[tpi].second;
1464
1465 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1466 unsigned RegA = DstMO.getReg();
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001467
1468 // Grab RegB from the instruction because it may have changed if the
1469 // instruction was commuted.
1470 RegB = MI->getOperand(SrcIdx).getReg();
Andrew Tricke3398282013-12-17 04:50:45 +00001471 SubRegB = MI->getOperand(SrcIdx).getSubReg();
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001472
1473 if (RegA == RegB) {
1474 // The register is tied to multiple destinations (or else we would
1475 // not have continued this far), but this use of the register
1476 // already matches the tied destination. Leave it.
1477 AllUsesCopied = false;
1478 continue;
1479 }
1480 LastCopiedReg = RegA;
1481
1482 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1483 "cannot make instruction into two-address form");
1484
1485#ifndef NDEBUG
1486 // First, verify that we don't have a use of "a" in the instruction
1487 // (a = b + a for example) because our transformation will not
1488 // work. This should never occur because we are in SSA form.
1489 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1490 assert(i == DstIdx ||
1491 !MI->getOperand(i).isReg() ||
1492 MI->getOperand(i).getReg() != RegA);
1493#endif
1494
1495 // Emit a copy.
Andrew Tricke3398282013-12-17 04:50:45 +00001496 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1497 TII->get(TargetOpcode::COPY), RegA);
1498 // If this operand is folding a truncation, the truncation now moves to the
1499 // copy so that the register classes remain valid for the operands.
1500 MIB.addReg(RegB, 0, SubRegB);
1501 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1502 if (SubRegB) {
1503 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1504 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1505 SubRegB) &&
1506 "tied subregister must be a truncation");
1507 // The superreg class will not be used to constrain the subreg class.
Craig Topperc0196b12014-04-14 00:51:57 +00001508 RC = nullptr;
Andrew Tricke3398282013-12-17 04:50:45 +00001509 }
1510 else {
1511 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1512 && "tied subregister must be a truncation");
1513 }
1514 }
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001515
1516 // Update DistanceMap.
1517 MachineBasicBlock::iterator PrevMI = MI;
1518 --PrevMI;
1519 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1520 DistanceMap[MI] = ++Dist;
1521
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001522 if (LIS) {
Duncan P. N. Exon Smith3ac9cc62016-02-27 06:40:41 +00001523 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001524
1525 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1526 LiveInterval &LI = LIS->getInterval(RegA);
1527 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1528 SlotIndex endIdx =
Duncan P. N. Exon Smith3ac9cc62016-02-27 06:40:41 +00001529 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
Matthias Braun13ddb7c2013-10-10 21:28:43 +00001530 LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001531 }
1532 }
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001533
Andrew Tricke3398282013-12-17 04:50:45 +00001534 DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001535
1536 MachineOperand &MO = MI->getOperand(SrcIdx);
1537 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1538 "inconsistent operand info for 2-reg pass");
1539 if (MO.isKill()) {
1540 MO.setIsKill(false);
1541 RemovedKillFlag = true;
1542 }
1543
1544 // Make sure regA is a legal regclass for the SrcIdx operand.
1545 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1546 TargetRegisterInfo::isVirtualRegister(RegB))
Andrew Tricke3398282013-12-17 04:50:45 +00001547 MRI->constrainRegClass(RegA, RC);
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001548 MO.setReg(RegA);
Andrew Tricke3398282013-12-17 04:50:45 +00001549 // The getMatchingSuper asserts guarantee that the register class projected
1550 // by SubRegB is compatible with RegA with no subregister. So regardless of
1551 // whether the dest oper writes a subreg, the source oper should not.
1552 MO.setSubReg(0);
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001553
1554 // Propagate SrcRegMap.
1555 SrcRegMap[RegA] = RegB;
1556 }
1557
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001558 if (AllUsesCopied) {
1559 if (!IsEarlyClobber) {
1560 // Replace other (un-tied) uses of regB with LastCopiedReg.
Sanjay Patel0b2a9492015-12-01 19:57:43 +00001561 for (MachineOperand &MO : MI->operands()) {
Andrew Tricke3398282013-12-17 04:50:45 +00001562 if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB &&
1563 MO.isUse()) {
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001564 if (MO.isKill()) {
1565 MO.setIsKill(false);
1566 RemovedKillFlag = true;
1567 }
1568 MO.setReg(LastCopiedReg);
Andrew Tricke3398282013-12-17 04:50:45 +00001569 MO.setSubReg(0);
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001570 }
1571 }
1572 }
1573
1574 // Update live variables for regB.
1575 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1576 MachineBasicBlock::iterator PrevMI = MI;
1577 --PrevMI;
1578 LV->addVirtualRegisterKilled(RegB, PrevMI);
1579 }
1580
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001581 // Update LiveIntervals.
1582 if (LIS) {
1583 LiveInterval &LI = LIS->getInterval(RegB);
Duncan P. N. Exon Smith3ac9cc62016-02-27 06:40:41 +00001584 SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001585 LiveInterval::const_iterator I = LI.find(MIIdx);
1586 assert(I != LI.end() && "RegB must be live-in to use.");
1587
1588 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1589 if (I->end == UseIdx)
Matthias Braun13ddb7c2013-10-10 21:28:43 +00001590 LI.removeSegment(LastCopyIdx, UseIdx);
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001591 }
1592
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001593 } else if (RemovedKillFlag) {
1594 // Some tied uses of regB matched their destination registers, so
1595 // regB is still used in this instruction, but a kill flag was
1596 // removed from a different tied use of regB, so now we need to add
1597 // a kill flag to one of the remaining uses of regB.
Sanjay Patel0b2a9492015-12-01 19:57:43 +00001598 for (MachineOperand &MO : MI->operands()) {
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001599 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1600 MO.setIsKill(true);
1601 break;
1602 }
1603 }
1604 }
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001605}
1606
Sanjay Patelb53791e2015-12-01 19:32:35 +00001607/// Reduce two-address instructions to two operands.
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001608bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1609 MF = &Func;
1610 const TargetMachine &TM = MF->getTarget();
1611 MRI = &MF->getRegInfo();
Eric Christopher33726202015-01-27 08:48:42 +00001612 TII = MF->getSubtarget().getInstrInfo();
1613 TRI = MF->getSubtarget().getRegisterInfo();
1614 InstrItins = MF->getSubtarget().getInstrItineraryData();
Duncan Sands5a913d62009-01-28 13:14:17 +00001615 LV = getAnalysisIfAvailable<LiveVariables>();
Jakob Stoklund Olesen24bc5142012-08-03 22:58:34 +00001616 LIS = getAnalysisIfAvailable<LiveIntervals>();
Chandler Carruth7b560d42015-09-09 17:55:00 +00001617 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
Evan Cheng822ddde2011-11-16 18:44:48 +00001618 OptLevel = TM.getOptLevel();
Alkis Evlogimenos725021c2003-12-18 13:06:04 +00001619
Misha Brukman6dd644e2004-07-22 15:26:23 +00001620 bool MadeChange = false;
Alkis Evlogimenos725021c2003-12-18 13:06:04 +00001621
David Greeneac9f8192010-01-05 01:24:21 +00001622 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
Andrew Trick808a7a62012-02-03 05:12:30 +00001623 DEBUG(dbgs() << "********** Function: "
Craig Toppera538d832012-08-22 06:07:19 +00001624 << MF->getName() << '\n');
Alkis Evlogimenos26583db2004-02-18 00:35:06 +00001625
Jakob Stoklund Olesen9760f042011-07-29 22:51:22 +00001626 // This pass takes the function out of SSA form.
1627 MRI->leaveSSA();
1628
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001629 TiedOperandMap TiedOperands;
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001630 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1631 MBBI != MBBE; ++MBBI) {
Duncan P. N. Exon Smithf1ff53e2015-10-09 22:56:24 +00001632 MBB = &*MBBI;
Evan Chengc5618eb2008-06-18 07:49:14 +00001633 unsigned Dist = 0;
1634 DistanceMap.clear();
Evan Chengc2f95b52009-03-01 02:03:43 +00001635 SrcRegMap.clear();
1636 DstRegMap.clear();
1637 Processed.clear();
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001638 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
Evan Cheng58324102008-03-27 01:27:25 +00001639 mi != me; ) {
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00001640 MachineBasicBlock::iterator nmi = std::next(mi);
Dale Johannesen8bba1602010-02-10 21:47:48 +00001641 if (mi->isDebugValue()) {
1642 mi = nmi;
1643 continue;
1644 }
Evan Cheng77be42a2010-03-23 20:36:12 +00001645
Jakob Stoklund Olesenda2b6b32012-12-01 01:06:44 +00001646 // Expand REG_SEQUENCE instructions. This will position mi at the first
1647 // expanded instruction.
Evan Cheng4b6abd82010-05-05 18:45:40 +00001648 if (mi->isRegSequence())
Jakob Stoklund Olesenda2b6b32012-12-01 01:06:44 +00001649 eliminateRegSequence(mi);
Evan Cheng4b6abd82010-05-05 18:45:40 +00001650
Evan Chengc5618eb2008-06-18 07:49:14 +00001651 DistanceMap.insert(std::make_pair(mi, ++Dist));
Evan Chengc2f95b52009-03-01 02:03:43 +00001652
Jakob Stoklund Olesen7fa17d42012-10-26 23:05:10 +00001653 processCopy(&*mi);
Evan Chengc2f95b52009-03-01 02:03:43 +00001654
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001655 // First scan through all the tied register uses in this instruction
1656 // and record a list of pairs of tied operands for each register.
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001657 if (!collectTiedOperands(mi, TiedOperands)) {
1658 mi = nmi;
1659 continue;
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001660 }
Alkis Evlogimenos725021c2003-12-18 13:06:04 +00001661
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001662 ++NumTwoAddressInstrs;
Jakob Stoklund Olesena0c72ec2012-08-03 23:57:58 +00001663 MadeChange = true;
Jakob Stoklund Olesen1162a152012-08-03 23:25:45 +00001664 DEBUG(dbgs() << '\t' << *mi);
1665
Chandler Carruth985454e2012-07-18 18:58:22 +00001666 // If the instruction has a single pair of tied operands, try some
1667 // transformations that may either eliminate the tied operands or
1668 // improve the opportunities for coalescing away the register copy.
1669 if (TiedOperands.size() == 1) {
Craig Topperb94011f2013-07-14 04:42:23 +00001670 SmallVectorImpl<std::pair<unsigned, unsigned> > &TiedPairs
Chandler Carruth985454e2012-07-18 18:58:22 +00001671 = TiedOperands.begin()->second;
1672 if (TiedPairs.size() == 1) {
1673 unsigned SrcIdx = TiedPairs[0].first;
1674 unsigned DstIdx = TiedPairs[0].second;
1675 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1676 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1677 if (SrcReg != DstReg &&
Cameron Zwarichf05c0cb2013-02-24 00:27:26 +00001678 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
NAKAMURA Takumi84965032015-09-22 11:14:12 +00001679 // The tied operands have been eliminated or shifted further down
1680 // the block to ease elimination. Continue processing with 'nmi'.
Chandler Carruth985454e2012-07-18 18:58:22 +00001681 TiedOperands.clear();
1682 mi = nmi;
1683 continue;
1684 }
1685 }
1686 }
1687
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001688 // Now iterate over the information collected above.
Craig Topperda5168b2015-10-08 06:06:42 +00001689 for (auto &TO : TiedOperands) {
1690 processTiedPairs(mi, TO.second, Dist);
David Greeneac9f8192010-01-05 01:24:21 +00001691 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
Jakob Stoklund Olesen6b556f82012-06-25 03:27:12 +00001692 }
Bill Wendling19e3c852008-05-10 00:12:52 +00001693
Jakob Stoklund Olesen6b556f82012-06-25 03:27:12 +00001694 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1695 if (mi->isInsertSubreg()) {
1696 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1697 // To %reg:subidx = COPY %subreg
1698 unsigned SubIdx = mi->getOperand(3).getImm();
1699 mi->RemoveOperand(3);
1700 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1701 mi->getOperand(0).setSubReg(SubIdx);
1702 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1703 mi->RemoveOperand(1);
1704 mi->setDesc(TII->get(TargetOpcode::COPY));
1705 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
Jakob Stoklund Olesen70ee3ec2010-07-06 23:26:25 +00001706 }
1707
Bob Wilson5c7d9ca2009-09-03 20:58:42 +00001708 // Clear TiedOperands here instead of at the top of the loop
1709 // since most instructions do not have tied operands.
1710 TiedOperands.clear();
Evan Cheng58324102008-03-27 01:27:25 +00001711 mi = nmi;
Misha Brukman6dd644e2004-07-22 15:26:23 +00001712 }
1713 }
1714
Cameron Zwarich36735812013-02-20 06:46:34 +00001715 if (LIS)
1716 MF->verify(this, "After two-address instruction pass");
1717
Misha Brukman6dd644e2004-07-22 15:26:23 +00001718 return MadeChange;
Alkis Evlogimenos725021c2003-12-18 13:06:04 +00001719}
Evan Cheng4b6abd82010-05-05 18:45:40 +00001720
Jakob Stoklund Olesenda2b6b32012-12-01 01:06:44 +00001721/// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
Evan Cheng4b6abd82010-05-05 18:45:40 +00001722///
Jakob Stoklund Olesenda2b6b32012-12-01 01:06:44 +00001723/// The instruction is turned into a sequence of sub-register copies:
1724///
1725/// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1726///
1727/// Becomes:
1728///
1729/// %dst:ssub0<def,undef> = COPY %v1
1730/// %dst:ssub1<def> = COPY %v2
1731///
1732void TwoAddressInstructionPass::
1733eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1734 MachineInstr *MI = MBBI;
1735 unsigned DstReg = MI->getOperand(0).getReg();
1736 if (MI->getOperand(0).getSubReg() ||
1737 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1738 !(MI->getNumOperands() & 1)) {
1739 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
Craig Topperc0196b12014-04-14 00:51:57 +00001740 llvm_unreachable(nullptr);
Evan Cheng4b6abd82010-05-05 18:45:40 +00001741 }
1742
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001743 SmallVector<unsigned, 4> OrigRegs;
1744 if (LIS) {
1745 OrigRegs.push_back(MI->getOperand(0).getReg());
1746 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)
1747 OrigRegs.push_back(MI->getOperand(i).getReg());
1748 }
1749
Jakob Stoklund Olesenda2b6b32012-12-01 01:06:44 +00001750 bool DefEmitted = false;
1751 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1752 MachineOperand &UseMO = MI->getOperand(i);
1753 unsigned SrcReg = UseMO.getReg();
1754 unsigned SubIdx = MI->getOperand(i+1).getImm();
1755 // Nothing needs to be inserted for <undef> operands.
1756 if (UseMO.isUndef())
1757 continue;
1758
1759 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1760 // might insert a COPY that uses SrcReg after is was killed.
1761 bool isKill = UseMO.isKill();
1762 if (isKill)
1763 for (unsigned j = i + 2; j < e; j += 2)
1764 if (MI->getOperand(j).getReg() == SrcReg) {
1765 MI->getOperand(j).setIsKill();
1766 UseMO.setIsKill(false);
1767 isKill = false;
1768 break;
1769 }
1770
1771 // Insert the sub-register copy.
1772 MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1773 TII->get(TargetOpcode::COPY))
1774 .addReg(DstReg, RegState::Define, SubIdx)
1775 .addOperand(UseMO);
1776
1777 // The first def needs an <undef> flag because there is no live register
1778 // before it.
1779 if (!DefEmitted) {
1780 CopyMI->getOperand(0).setIsUndef(true);
1781 // Return an iterator pointing to the first inserted instr.
1782 MBBI = CopyMI;
1783 }
1784 DefEmitted = true;
1785
1786 // Update LiveVariables' kill info.
1787 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1788 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1789
1790 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1791 }
1792
David Blaikie9db062e2013-02-20 07:39:20 +00001793 MachineBasicBlock::iterator EndMBBI =
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00001794 std::next(MachineBasicBlock::iterator(MI));
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001795
Jakob Stoklund Olesenda2b6b32012-12-01 01:06:44 +00001796 if (!DefEmitted) {
1797 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1798 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1799 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1800 MI->RemoveOperand(j);
1801 } else {
1802 DEBUG(dbgs() << "Eliminated: " << *MI);
1803 MI->eraseFromParent();
1804 }
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001805
1806 // Udpate LiveIntervals.
Cameron Zwarichcaad7e12013-02-20 22:10:00 +00001807 if (LIS)
Cameron Zwarich8e60d4d2013-02-20 06:46:48 +00001808 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
Evan Cheng4b6abd82010-05-05 18:45:40 +00001809}